JPS63272287A - Television signal insertion device - Google Patents

Abstract

PURPOSE:To attain insertion output of an NTSC television signal without using a teloper unit by inserting an inserted picture by one field to a reproduced background picture over plural fields in synchronism with the background picture recorded in advance on a magnetic recording medium. CONSTITUTION:A picture data signal of an inserted picture is stored in a DRAM 22. A picture data signal stored in the DRAM 22 is read while reproducing a video tape with a background picture recorded thereupon and inserted and recorded to one field just before the insertion start position of the NTSC television signal of the background picture. The obtained video tape is reproduced and the reproduced picture data signal is stored once in the DRAM 22 and the picture data signal by one field stored in the DRAM 22 in the next and succeeding fields is read repetitively and the NTSC television signal being the coded picture data signal onto the background picture NTSC television signal of the reproduced background is inserted repetitively and the result is outputted.

Description

[Detailed description of the invention] [Industrial application fields] The present invention relates to a television signal insertion device.

[Prior Art] FIG. 2 is a block diagram of a conventional television signal superimposing device. In FIG. 2, a telopper unit +05 is a playback video tape recorder (hereinafter referred to as a VTR) that plays back a television signal of a background image into which a title picture is inserted.
That's what it means. ) 103 and outputs the synchronizing signal to the video camera lot. video camera 10
1 photographs a title picture 102 in synchronization with the synchronization signal, and a television signal of the photographed title picture is output to a caption unit 105. The caption unit I05 inserts the television signal of the title picture 102 into the television signal output from the reproduction VTR 103 using a known combining method, and the combined television signal is output to the recording VTR 104 and recorded on a videotape.

[Problems to be Solved by the Invention] However, in the conventional example described above, in order to insert and synthesize the television signal of an inserted image such as a predetermined title image with the television signal of another background image, it is necessary to The circuit is complicated and an expensive telopper unit is required.

Furthermore, as described above, since the television signal of another background image into which the television signal of the inserted image is inserted is dubbed, there is a problem in that the image quality of the television signal of this background image deteriorates.

An object of the present invention is to solve the above-mentioned problems, and to solve the problem without deteriorating the image quality of the TV signal of an inserted image such as a title picture or the TV signal of another background image to be inserted, and without requiring a caption unit. To provide a simple and inexpensive television signal insertion device.

[Means for Solving the Problems] The present invention inserts a television signal of a one-minute insertion image into the magnetic recording medium in synchronization with a television signal of a background image recorded in advance on the magnetic recording medium. a recording means for recording; a reproduction storage means for reproducing and storing a television signal of an insert image inserted and recorded on the magnetic recording medium by the recording means; and an insertion image for one minute of the l-field repeatedly read from the reproduction storage means. and inserting means for inserting the television signal of the background image over a plurality of fields into the television signal of the background image to be reproduced in synchronization with the television signal of the background image recorded in advance on the magnetic recording medium. shall be.

[Function] With the above configuration, the recording means outputs the television signal of the inserted image of 1 field to the magnetic recording medium in synchronization with the television signal of the background image recorded in advance on the magnetic recording medium. After the insertion recording is performed on the magnetic recording medium, the reproduction storage means reproduces and stores the television signal of the insertion image inserted and recorded on the magnetic recording medium by the recording means. Next, the inserting means reproduces the television signal of the inserted image for one minute of the l-field, which is repeatedly read out from the reproduction storage means, in synchronization with the television signal of the background image pre-recorded on the magnetic recording medium. The background image is inserted into the television signal over multiple fields. by this,
The television signal of the inserted image is inserted and output in synchronization with the television signal of the background image. Here, since the insertion operation can be performed without dubbing the television signal of the background image, the image quality of the television signal of the background image does not deteriorate.

[Embodiment] FIG. 1 is a block diagram of a VTR equipped with a television signal superimposition device which is an embodiment of the invention.
The TR stores the image data signal of the inserted image in advance in a dynamic random access memory (hereinafter referred to as DRAM).
The image data signal of the inserted image is read out from the DRAM 22, and the image data signal is stored in the NTSC of another background image previously recorded on the videotape.
After inserting and recording into one field before the start field of the television signal, the video tape in which the above-mentioned image data signal was inserted and recorded and the television signal of another background image was recorded is played back, and the above-mentioned image data signal is first transferred to the DRAM. 22, and when the background image is played back in the next field, the image data signal stored in the DRAM 22 is read out and the NTSC television signal of the encoded inserted image is converted into the NTSC television signal of the background image being played back. It is characterized by being inserted.

In FIG. 1, a video camera or VT'R, etc. that outputs an NTSC television signal of an inserted image such as a title is connected to the title video input terminal l, and the NTSC television signal is first automatically transmitted via the title video input terminal l. The gain adjustment circuit (hereinafter referred to as AGC circuit) 2 is manually operated,
After the amplitude of the television signal is adjusted to a predetermined level, 3
．． It is output to the 58M to IZ trap circuit 3, and
It is output to the synchronization separation circuit 4 via the title side of the changeover switch 30.

The synchronization separation circuit 4 extracts a vertical synchronization signal V5sync and a horizontal synchronization signal Hsync from the input television signal and outputs them to the reference signal generator 7. The reference signal generator 7 generates a horizontal drive signal Hd of negative polarity and a planking signal BLK based on the manually generated synchronization signals V5ynC and Hsync.
, a 4 MHz clock signal CK for writing and reading image data signals in the DRAM 22, a burst flag pulse, a clamp pulse, and two of the vertical blanking periods.
It generates a flag pulse F21)1 indicating 1H, outputs a horizontal drive signal Hd to the upper address counter 21 and lower address counter 23 of the storage section 8, and outputs a blanking signal BLK to the upper address counter 21. Further, the reference signal generator 7 outputs the clock signal to the upper and lower address counters 21 and 23 of the storage unit 8 and the DRAM 22, and also outputs the synchronization signal Hsyn.
c and V 5ync, a burst flag pulse, a clamp pulse, and a blanking signal are output to the image processing circuit 9 and the RGB generator I6 of the color processing circuit IO. Furthermore, the reference signal generator 7 generates synchronization signals V 5sync and H
The mixed synchronization signal C5ync containing 5ync is output to the adder 34 and the controller 50, and the flag pulse F'21H indicating 21H of the vertical blanking period is outputted to the flag generation circuit 32 and the flag detection circuit 35.

Here, a phase-locked circuit (hereinafter referred to as a PLL circuit) is used in the output section of the synchronization signals V5sync and Hsync of the reference signal generator 7, and the synchronization signals V5sync and Hsync input from the synchronization separation circuit 4 are Even if the field is missing, the synchronization signal V 5y input earlier
The PLL circuit self-oscillates in synchronization with nc and Hsync, and synchronization signals V5sync and Hsync are output.

On the other hand, the 3.58Ml-1z trap circuit 3 removes the 358MHz color subcarrier signal from the input NTSC television signal of the inserted image and outputs it to the synchronization signal removal circuit 12. The inverting amplifier 1 removes the synchronization signals H5ync and V5ync from the signal.
3 to an analog-to-digital converter (hereinafter referred to as A/D converter) 14. The A/D converter 14 sequentially quantizes the input inverted luminance signal into a binary image data signal of black and white, and transfers the image data signal to the DRAM 2 via the title side of the changeover switch 31.
The signal is output to the data input terminal DI of No. 2, and is also output to the image processing circuit 9 via the a side of the switch 15. Here, the H level image data signal "l" corresponds to one black pixel, while the L level image data signal "0" corresponds to one white pixel.

The storage unit 8 includes a 64-bit DRAM 22 that stores an image data signal of one field of 256×256 dots, and an upper address counter 21 that counts the horizontal drive signal Hd to generate and output an address of the upper 8 bits of the DRAM 22. A lower address counter 23 that counts the horizontal drive signal Hd and generates and outputs a lower 8-bit address.
Consists of. The DRAM 22 operates based on a 4 MHz clock signal, and divides a period of about 60 μs excluding the horizontal synchronization signal H5ync out of the horizontal period of 63.5 μs into 256 parts in the horizontal direction, and divides the horizontal period of 63.5 μs into 256 luminance signals. is expressed as an 8-bit image data signal. Also, NTS
The horizontal period of one field of the C television signal is 262.5, but excluding the blanking signal BLK, the image data signals of 256 horizontal periods are represented by a total of 16 bit image data signals. A memory control circuit 20 has a write/write circuit connected to the circuit 20 and controlled by a controller 50.
A write signal or a read signal is output to the write/read signal input terminal W/R of the DRAM 22 depending on the switching state of the read changeover switch 20a. When a write signal is manually input from the memory control circuit 20 to the terminal W/R of the DRAM 22, the horizontal drive signal I
-Id and the blanking signal BLK are sequentially input to the upper address counter 21, the DRAM 22 starts writing the image data signal of the I field, and the upper and lower address counters 21 and 23 input the horizontal drive signal Hd.
is counted to generate upper and lower addresses, and
Output to 2. In response, the DRAM 22 stores the image data signal input from the D/D converter I4 to the data input terminal DI based on the clock signal CK.

On the other hand, when the read signal is input from the memory control circuit 20 to the terminal W/R of the DRAM 22, and when the horizontal drive signal Hd and the blanking signal BLK are sequentially input to the upper address counter 21, the DRAM 22
starts reading out the image data signal of the I field, and the upper and lower address counters 21 and 23 generate upper and lower addresses and output them to the DRAM 22 in the same manner as described above.

In response to this, the DRAM 22 repeats the stored image data signal for the I field based on the clock signal CK and outputs the image data signal from the data output terminal Do to the switch! 5 to the image processing circuit 9 via the b side of the switch I.
It is output to the control signal input terminal of the switch 5 via the a side of the switch 8. Here, the read operation of the image data signal is repeated until the read signal from the memory control circuit 20 stops.

The operator uses an image processing setting key (not shown) of the mode control circuit 19 to perform predetermined image processing (hereinafter referred to as
This is called image processing for inserted images. ), the mode control circuit 19 outputs a processing setting control signal corresponding to each of the above processes from the image processing circuit 9, and the operator uses a color setting key (not shown) of the mode control circuit 19 to When the colors of the inserted image are set using the I-I level color setting control signal r(C, GC
and BG are output to the respective first input terminals of the AND gates ANDI to AND3 of the color processing circuit IO.

The image processing circuit 9 is a known circuit, and the image data signal input to the circuit 9 is processed by performing the above-mentioned image processing of the inserted image based on the processing setting control signal output from the mode control circuit 19. The image data signal is sent to the color processing circuit I.
The signal is outputted to the second input terminals of the AND gates ANDI to AND3 of O, and is also outputted to the adder 34 via an attenuator 33 that attenuates it to a predetermined level of, for example, 1 Vp-p. The color processing circuit IO is a known circuit, and includes three AND gates AND1 to AND3, and the above AND gates AND! or three gate switches 17 whose output terminals of AND3 are respectively connected to control signal input terminals.
a to 17c, and an RGB generation circuit 16. The RGB generation circuit 16 has red R1 green G and blue B N.
Color subcarrier signals of the TSC television signal are generated and output to the b side of the switch 5 via gate switches 17a to 17c, respectively.

The gate switches 17a to 17c are turned on when an H level signal is input to each control signal input terminal, and are turned off when an L level signal is inputted to each control signal input terminal. Therefore, the black H-level image data signal "BI" is input from the image processing circuit 9 to each second input terminal of the AND gates AND! to 3, and the mode control circuit I9 outputs the color setting control signal RC1GC or BG. When one signal is input to each first input terminal of the AND gates ANDI to AND3, one of the gate switches 17a to 17c corresponding to the AND gates ANDI to AND3 is turned on. , red R1, green G, and blue B, the color subcarrier signal of the NTSC television signal is outputted from the RGB generator 16 to the b side of the switch 5 via the gate switches 17a to 17c.

Note that the b side of the switch 18 is connected to the F (level voltage output terminal) of a known constant voltage power source (not shown).The switch 5 is always switched to the a side, and the control signal input It is switched to the b side only when an H level image data signal is input to the terminal.

The NTSC television signal of another background image into which the NTSC television signal of the inserted image is inserted is inputted to the recording video input terminal 40, and then inputted to the recording processing circuit 42 via the b side of the changeover switch 41.

In the recording processing circuit, after predetermined processing such as FM modulation of the luminance signal and low frequency conversion of the color signal is performed on the NTSC television signal, the REC of the playback/recording switch 43 is performed.
The signal is output to the magnetic head 44 via the side and recorded on the video tape loaded in the VTR.

The signals reproduced from the video tape are transmitted to the magnetic head 44.
and the regeneration processing circuit 4 via the PB side of the changeover switch 43.
5 is input. After the reproduction processing circuit 45 performs predetermined processing on the reproduction signal, such as FM modulation of the luminance FM signal and high frequency conversion of the low frequency conversion color signal to 3.58 MHz, the controller 50 converts only the image data signal. It is output to the buffer memory 47 via the switch 46 which is controlled to pass, and the flag detection circuit 3
2 and the PB side of the selector switch 30, and further,
The signal is output to the video output terminal 6 via the a side of the changeover switch 5.

The buffer memory 47 once stores the human input data signal, and then transfers it to the DRAM 22 via the PB side of the changeover switch 31.
output to the data input terminal DI.

Based on the flag pulse F21H input from the reference signal generator 7, the flag detection circuit 32 detects a start flag pulse ST and an end flag pulse SP inserted into the vertical blanking period 21H from the input reproduced signal. , outputs a flag detection signal to the controller 50 when the pulses ST and SP are detected.

The controller 50 is connected to ground via a memory switch 51, a start switch 52, and an end switch 53, and a recording/playback switch 54 is connected to the controller 5.
Connected to 0. The controller 50 switches the switches I5, 20 according to the switching state of each switch 51 to 54.
a, 30, 31, 41, and 43, the switch 54 is switched to the PB side, and the flag detection circuit 2
When a flag detection signal indicating the detection of the start flag ST is input from 3 to the controller 50, the controller 50 detects the inserted image recorded in the field where the start flag ST is detected based on the manually input mixed synchronization signal C5ync. switch 46 to pass the image data signal of
Turn on. Further, when the selector switch 54 is switched to the REC side and the switch 52 or 53 is turned on,
The controller 50 sends the flag generation signal to the flag generation circuit 5.
In response to this, the flag generation circuit 55 starts the vertical blanking period at 21H immediately after the input of the flag generation signal, based on the flag pulse F21H input from the reference signal generator 7. Flag ST or end flag SP
is output to the adder 34. The adder 34 receives the image data signal of the inserted image input manually from the attenuator 33, the mixed synchronization signal c5ync, and the start flag S'F or end flag S.
P is added and output to the recording processing circuit 42 via the a side of the changeover switch 41.

Using the apparatus configured as described above, the following steps are sequentially performed to insert an insertion image into another background image.

(+) Record a videotape of another background image into which the insert image is inserted.

(2) Store the image data signal of the inserted image in the DRAM 22.

(3) While playing back the videotape on which the background image is recorded, the image data signal stored in the DRAM 22 is read out and inserted and recorded in one field immediately before the insertion start position of the NTSC television signal of the background image. .

(, L) (3) is 2! ! Videotape Honmachi student 17
, the regenerated image data signal is once DRA
M22 and DRAM from the next field onwards.
The image data signal for the I field stored in 22 is repeatedly read out, and the N of the background image being reproduced is
The encoded N of the image data signal is added to the TSC television signal.
A TSC television signal is repeatedly inserted and output.

Hereinafter, the operations and operations of each of the above steps will be explained with reference to FIG.

(1) Recording of background image After loading the videotape for recording the NTSC television signal of the background image into the VTR, turn the selector switch 54 to REC.
Switch to the side. As a result, the controller 50 switches the selector switch 41 to the b side and also switches the selector switch 43 to the REC side. A background image NTSC television signal is then input into the recording video input signal 40, such as from a video camera or another VTR. As a result, the NTSC television signal is output to the magnetic head 44 via the b side of the changeover switch 41, the recording processing circuit 42, and the RFC side of the changeover switch 43, and the recording signal of the NTSC television signal is loaded into the VTR. recorded on videotape.

(2) Storing an inserted image An inserted image such as a black title image is drawn on a white board in advance, and the above-mentioned image processing settings in the image processing circuit 9 and color settings in the color processing circuit 10 are performed. For example, the output terminal of a video camera (not shown) for photographing the inserted image is connected to the title video input terminal I, and the video camera is used to photograph the inserted image. At this time, by turning on the memory switch 51, the controller 50 switches the changeover switch 20a to the W (write) side, the switch 15 to the a side, the changeover switches 30 and 31 to the title side, and the switch 18 to side a. by this,
The switch 5 is switched to the b side, and the write signal is sent from the memory control circuit 20 to the terminal W/ of the DRAM 22.
input to R.

As a result, the NTSC television signal of the inserted image is transmitted through the title video input terminal 1 and the AGC circuit 2 to 3.
The signal is input to the 58 MHz trap circuit 3 and further input to the synchronization separation circuit 4 via the title side of the switch 30. The synchronization separation circuit 4 extracts the synchronization signals Hsync and V5sync from the input NTSC television signal and outputs them to the reference signal generator 7, and in response, the reference signal generator 7 generates the various reference signals mentioned above, Output to each circuit as described above. On the other hand, the NTSC television signal input to the 3.58 MHz trap circuit is outputted to the A/D converter 14 via the synchronization signal removal circuit 12 and the inverting amplifier 13 after only its color subcarrier component is removed. A/D
The converter 14 sequentially 1-bit quantizes the input NTSC television signal, converts it into a binary image data signal, and converts the image data signal to the DR via the title side of the changeover switch 31.
At the same time, the image data signal is output to the video output terminal 6 via the a side of the switch 15, the image processing circuit 9, the color processing circuit 10°, and the b side of the switch 5.
Output to.

Therefore, the brightness signal of the television signal input to the title video input terminal l is inverted and written to the DRAM 22 where it is converted into a binary image data signal, and the image processing set in the image processing circuit 9 is not performed. The NTSC television signal of the inserted image of the set color is output to the video output terminal 6. In other words, the black luminance signal of the manually inputted television signal is converted into an image data signal "VI" at the M
22. Furthermore, by connecting, for example, a CRT display device to the video output terminal 6, an inserted image of a predetermined color that has undergone predetermined image processing can be viewed.

After loading the videotape on which the background image in (1) above is recorded into the VTR and connecting a display device to the video output terminal 6, turn the changeover switch 54 to P.
Switch to side B. In response to this, the controller 50 switches the switches 15, 18 and 41 to the a side, and switches the changeover switches 30, 31 and 43 to the PB side.

Next, when the VTR is put into the playback state, the signals played from the video tape are transmitted through the magnetic head 44 and the switch 43.
The signal is output to the display device 6 via the PB side of the switch 30, the playback processing circuit 45, the a side of the switch 5, and the video output terminal 6, and is further output to the sync separation circuit 4 via the PB side of the switch 30. The synchronization signals Hsync and V5sync are extracted from the signal input to the synchronization separation circuit 4 and output to the reference signal generator 7.
The above-mentioned various reference signals synchronized with the reproduced signal are supplied to each circuit.

Here, when the user wants to insert an insertion image such as a title while playing back and viewing the background image, the start switch 52 is turned on. In response, the controller 50 controls the switch 2.
It switches Oa to the R (read) side and outputs a flag generation signal to the flag generation circuit 55. As a result, the read signal is transmitted from the memory control circuit 20 to the DRAM2.
21 of the vertical blanking period immediately after the switch 52 is turned on, based on the input flag pulse F21H.
A start pulse ST is output to the adder 34 at a high level. Including 21H of this vertical blanking period! Only during the field period, the controller 50 switches the switch 43 from the PB side to the REC side.

As a result, the image data signal for one field stored in the DRAM 22 is outputted to the adder 34 via the b side of the switch 15, the image processing circuit 9, and the attenuator 33.

Therefore, first, at 21H of the vertical blanking period, a start pulse ST is sent from the flag generator 55 to the adder 34, to the a side of the changeover switch 41, to the recording processing circuit 42, to the R side of the changeover switch 43.
It is recorded on the video tape mounted on the EC side and via the magnetic head 44.

Then, in the same way as described above, the DRAM is
The image data signal read from 22 is recorded on the videotape. Further, when the user wants to stop inserting the insertion image after the required number of fields while playing back the background image, the end switch 53 is turned on. As a result, the controller 50 outputs a flag generation signal to the flag generation circuit 55, and in response, the flag generation circuit 55 activates the switch 53 based on the input flag pulse F21H.
The end pulse SP is generated in 21-4 of the vertical blanking period immediately after the controller 5 is turned on, and as described above, the controller 5
When the changeover switch 43 is switched from the PB side to the REC side, the end pulse SP is recorded on the video tape via the magnetic head 44.

Therefore, in the vertical blanking period 21H of the field immediately before the field in which the insertion image is to be inserted, a start pulse ST is recorded on the videotape on which the NTSC television signal of the background image is recorded in synchronization with the NTSC television signal, The image data signal for one field is recorded in the image signal portion of the next one field, and after the required number of fields for which insertion of the insertion image is desired, vertical blanking is erased when the desired insertion of the insertion image is stopped. In period 21H, a termination pulse SP is recorded on the videotape in synchronization with the recorded NTSC television signal.

At this time, the videotape obtained in (3) is transferred to the VTR.
After connecting the display device to the video output terminal 6 in the same way as described above, turn the selector switch 54 to P.
Switch to side B. In response to this, the controller 50 switches the switches 15, 18 and 41 to the a side, and switches the changeover switches 30, 31 and 43 to the PB side. Next, when the VTR is in the playback state (3), the signal played from the videotape is output to the display device 6 via the video output terminal 6 in the same way as described above, and is also sent to the synchronization separation circuit 4 and the flag detection circuit 32. Get output. The synchronization separation circuit 4 and the reference signal generator 7 operate in the same manner as described above, and the various reference signals described above synchronized with the reproduced signal are supplied to each circuit.

During playback, when the flag detection circuit 32 first detects the start flag ST, the flag detection signal is sent to the controller 5.
0, and in response, the controller 50 switches the switch 20a to the W (write) side in order to write the image data signal inserted in the image signal period of one field following the start flag ST into the DRAM 22. , the switch 46 is turned on only during the image signal period, and at this time the memory control circuit 20 outputs a write signal to the terminal W/R of the DRAM 22. As a result, the image data signal for one field reproduced from the video tape is transmitted to the magnetic head 44, the PB side of the changeover switch 43, and the reproduction processing circuit 4.
5, the data is input to the DRAM 22 via the switch 46, the buffer memory 47, and the PB side of the changeover switch 31 and written therein.

After writing the image data signal to the DIIAM 22, the controller 50 switches the switch 20a to the R (read) side, switches the switch 15 to the b side, and
Switch the switch 18 to the a side. As a result, a read signal is input from the memory control circuit 20 to the terminal W/R of the DRAM 22.

Therefore, the image data signal for one field stored in the DRAM 22 is repeatedly read out to the image processing circuit 9 via the b side of the switch I5, and is also input to the control signal input terminal of the switch 5 via the a side of the switch 18. Output. The image data signal input to the image processing circuit 9 is subjected to the above-described preset image processing, and then, in response to the H level image data signal "B", the color processing circuit 10 processes the preset red R1 green G signal. or NT of any one color blue B
The SC television signal is output to the b side of the switch 5. Here, when the L level image data signal "0" is read out from the DRAM 22 and input to the control signal input terminal of the switch 5, the switch 5 is switched to the a side, and the background signal output from the AC'C circuit 2 is The NTSC television signal of the image is output to the video output terminal 6 via the a side of the switch 5.

On the other hand, when the H-level image data signal "B" is read out from the DRAM 22 and input to the control signal input terminal of the switch 5, the switch 5 is switched to the b side, and the color subcarrier is output from the color processing circuit IO. The signal is output to the video signal output terminal 6 via the b side of the switch 5. Therefore, an H level control signal corresponding to the image data signal "B" from the DRAM 22 is input to the control signal input terminal of the switch 5. Since the color subcarrier signal is output to the video signal output terminal 6 only in this case, an insertion image drawn in black in advance can be inserted into the background image in a predetermined color. For example, if a recording VTR is connected to the video output terminal 6, it is possible to record an image in which the inserted image is combined.

When the flag detection circuit 32 detects the end pulse SP after this operation of inserting the NTSC television signal of the inserted image of 1 field into the NTSC television signal of the background image is repeatedly performed over a plurality of predetermined number of fields, The controller 50 instructs the memory control circuit 20 to stop reading the image data signal, and also switches the switch 18 to b.
Switch to the side. As a result, the memory control circuit 20 stops outputting the readout signal, the readout of the image data signal from the DRAM 22 is stopped, and the changeover switch 5 is always switched to the a side, and the N of the inserted image is stopped.
The TSC television signal is not inserted into the background image being played back, and only the background image is output to the display device via the a side of the switch 5 and the video output terminal 6.

As explained above, the VTR equipped with the superimposing device of the present invention inserts and records the inserted image as an image data signal onto a videotape on which the NTSC television signal of the background image is previously recorded. , by writing the inserted and recorded image data signal into the DRAM 22 and then repeatedly reading it, the NTSC of the inserted image is
Since the television signal is inserted into the NTSC television signal of the background image, there is no need to dub the NTSC television signal of the background image as in the conventional example, and there is an advantage that the image quality of the background image does not deteriorate. Further, the VTR of the present invention has the advantage that the circuit for inserting images can be constructed more easily than conventional devices, and furthermore, the VTR can be easily operated and constructed at low cost.

In the above example,! Although one DRAM 22 capable of storing a field image data signal is provided, the present invention is not limited to this, and a plurality of the above DRAMs may be provided and the plurality of DRAMs may be switched. In this case, there is an advantage that the image data signals of a plurality of screens can be stored and an inserted image of the image data signals can be inserted into a photographed image as necessary.

Further, although the image data signal of the inserted image inputted from the title video input terminal l and the image data signal played by the VTR are switched by the changeover switch 31 and inputted to the DRAM 22, the changeover switch 31 is not limited to this. Alternatively, each image data signal may be written to two Drs (AM).

Furthermore, the image to be inserted is preset in the above three colors ItG.
Although the inserted image is inserted in one color among H, it is not limited to this, and the inserted image may be displayed in white or black by providing a constant voltage power supply that outputs a DC voltage of white level or black level. good.

In the above embodiment, the inverting amplifier 13 is used, but the invention is not limited to this, and the luminance signal is A/D converted as it is and stored in the DRAM 22 without using the inverting amplifier 13.
The switch 5 is switched to the b side in response to an L level control signal output from M22, and the DRAM
Image processing may be performed by inverting the image data signal corresponding to the luminance signal read from 22.

Although the above embodiment describes an example of a VTR equipped with a superimpose device that processes color signals, the present invention is not limited to this, and the present invention can be applied to a VTR equipped with a superimpose device that processes black and white television signals. Can be easily applied. Furthermore, the present invention can be easily applied not only to VTRs but also to various magnetic recording and reproducing devices that record signals on magnetic recording media.

[Effects of the Invention] As described in detail above, according to the present invention, in synchronization with the television signal of the background image recorded in advance on the magnetic recording medium,
After inserting and recording the television signal of the inserted image for one field on the magnetic recording medium, and reproducing and storing the television signal of the inserted image recorded on the magnetic recording medium, the television signal of the inserted image for one field is recorded. Since the signal is repeatedly read out and inserted over multiple fields into the background image television signal to be played back in synchronization with the background image television signal pre-recorded on the magnetic recording medium, an expensive telopper unit is required. To provide a television signal insertion device which can insert and output the television signal of the inserted image in synchronization with the television signal of the background image without using a circuit, and thereby has a simple circuit and is inexpensive. be able to. As described above, since the insertion operation can be performed without dubbing the television signal of the background image, there is an advantage that the quality of the television signal of the background image does not deteriorate.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a VTR equipped with a television signal superimposing device according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional television signal superimposing device. 4. Synchronous separation circuit, 5. Switch, 7. Reference signal generator, 8. Storage section, 9. Image processing circuit, 10. Color processing circuit, 22. Dynamic random. Access memory (D
RAM), 31... Selector switch, 42... Recording processing circuit, 43... Recording/playback selector switch, 44... Magnetic head, 45... Playback processing circuit, 50... Controller. Figure 2

Claims (1)

[Claims] (1) a recording means for inserting and recording a television signal of one field's worth of insertion images into the magnetic recording medium in synchronization with a television signal of a background image recorded in advance on a magnetic recording medium; a reproduction storage means for reproducing and storing the television signal of the inserted image inserted and recorded on the recording medium; and a reproduction storage means for reproducing and storing the television signal of the insertion image for one field, which is repeatedly read from the reproduction storage means, which is recorded in advance on the magnetic recording medium. 1. A television signal insertion device comprising: insertion means for inserting a plurality of fields into a television signal of a background image to be reproduced in synchronization with a television signal of a background image.