JPS63269833A - Mh code decoder - Google Patents

Abstract

PURPOSE:To reduce the hardware quantity of a decode logic circuit, by shifting the prescribed number of bits of data in an inputting shift circuit by detecting a prescribed pattern by the decode logic circuit which detects a specific pattern in an MH code. CONSTITUTION:Sixteen bits of the MH code are inputted to a shift register 101, and the low-order 9 bits are supplied to the decode logic circuits 121-123. If continuous 8 bits of the least significant bit is not 0000 0001 in order from the LSB, the circuit 121 outputs a runlength, the designation of a T/M code, and a code length. When the code is an M code, a color inversion signal 105 becomes inactive, and the runlength is integrated even in the next decoding. Also, a circuit 132 becomes inactive, and the next decoding results in white run. When the code is a T code, the signal 105 becomes active, and the runlength is integrated newly from the next decoding. Also, the circuit 132 becomes active, and the next decoding results in black run. A code length integrator 110 generates the same number of shift pulses 112 as that of the code length, and the content of the shift register 101 is shifted by the code length.

Description

[Detailed description of the invention] [Industrial application fields] The present invention relates to an MH code decoder.

[Prior Art] An MH code decoder decodes an MH code and outputs a run length. The code length of MH code is 2 to 1
Up to 3. Therefore, it is sufficient to decode successive 13 bits at a time.

Conventionally, in this type of MH code decoder, consecutive 13-bit codes were manually generated.

FIG. 3 shows an example of a conventional MH code decoder.

In the figure, a shift register 301 is a register that sequentially inputs a code string of MH codes to a decoding logic circuit 302. In the same figure, the most significant bit is MSB, and the least significant bit is LS.
Let it be B. The shift register 301 has 16 bits, and latches the MH code 8 bits at a time in response to a latch signal 311, which will be described later. Further, the held data is shifted one bit at a time in the LSB direction by a shift pulse 312, which will be described later. The decoding logic circuit 302 is realized using a read-only memory (hereinafter referred to as ROM), and manually inputs the MH code from the shift register 301 in 13-bit increments to obtain the run length in the run length integrator 303 and the color inversion circuit 304.
The code lengths are output to the code length integrator 310 for each T code/M code. The run length integrator 303 integrates the run length until a color inversion signal 305 is received from the color inversion circuit 304 .

The color inversion circuit 304 inputs a signal representing T code/M code from the decoding logic circuit 302, and outputs a color inversion signal 305 and a decoding logic selection signal 306 when detecting a T code. Color inversion signal 305 is coupled to run length integrator 303 as previously described. Furthermore, the decoding logic selection signal 306 is output to the decoding logic circuit 302. The code length integrator 310 inputs the code length from the decoding logic circuit 302 and generates the same number of shift pulses 312 as the code length. Furthermore, the code length is integrated and a latch signal 311 is output for every 8 bits.

In the figure, consider the operation of decoding an MH code.

First, a 16-bit MH code is input to the shift register 301 by a start signal (not shown). Assume that the starting point is white run. The lower 13 bits of the 16 manually generated bits are input to the decoding logic circuit 302, and the run length, T code/
Outputs the code length for each M code. If the code is an M code, the color inversion signal 305 becomes inactive and the rerun length is integrated in the next decoding. Also. The decoding logic selection signal 306 is also inactive, and the next decoding will also be a white run. If it is a T code, the color inversion signal 305 becomes active and the run length is newly accumulated from the next decoding. Further, the decoding logic selection signal 306 also becomes active, and the next decoding will be a black run. The code length integrator 310 generates the same number of shift pulses 312 as the code length, and the contents of the shift register 301 are shifted by the code length. In addition, the latch signal 311
When becomes active, an 8-bit MH code is input to the shift register 301. The output of the run length integrator 303 when the code becomes a T code is the decoded data.

In this example, from Table 1, the maximum run length is 2560, so the run length output to the run length integrator 303 is 12 bits.
The code length output to code length integrator 310 is 4 bits. Therefore, if each T code is represented by 1 bit, the output from the decoding logic circuit 302 will be 7 bits in total.

At this time, if the decoding logic circuit 302 is configured with a ROM, the total number of bits will be 2''Xl 7 = 272 bits.

[Problems to be Solved by the Invention] As mentioned above, in the conventional MH code decoder, when the decoding logic circuit is configured with a ROM, the total number of bits is reduced to 2.
There is a problem that the number of bits is +4X17=272, and the amount of hardware is too large.

Therefore, the object of the present invention is to
The objective is to realize an H code decoder.

[Means for Solving the Problems] The present invention provides a decoder for decoding MH codes, and the decoder includes a plurality of decoding logic circuits including a decoding logic circuit for detecting a specific pattern, and a decoding logic circuit for detecting the specific pattern. A decoding logic selection circuit that forms a decoding logic selection signal for determining which one of the decoding logic circuits to select, a multiplexer controlled by the decoding logic selection signal output from the decoding logic selection circuit, and an input shift circuit. When the specific pattern is detected by the decoding logic circuit that detects the specific pattern, the data in the input shift circuit is shifted by a predetermined number of bits.

Therefore, compared to the conventional MH code decoder described above, the present invention has an original content of reducing the amount of hardware of the decoding logic circuit by adding processing to a specific pattern of the Ml code. has.

[Embodiments] Next, embodiments of the present invention will be described with reference to the drawings.

[Strictly superior] FIG. 1 is a block diagram showing a first embodiment of the present invention.

In the figure, a shift register 101 is a register that supplies a code string of MH codes to a decoding logic circuit 121, a decoding logic circuit 122, and a decoding logic circuit 123. In the figure, the upper side is the MSB and the lower side is the LSB. shift register 1
01 is 16 bits, and the MH code is latched 8 bits at a time by a latch signal 111, which will be described later. Furthermore, the data inside is shifted by 1 in the LSB direction by a shift pulse 112, which will be described later.
Shifted bit by bit. In this embodiment, the decoding logic circuit 121 is a decoding logic circuit for white runs, the decoding logic circuit 122 is a decoding logic circuit for black runs and monochrome common runs, and the decoding logic circuit 123 is a decoding logic circuit for some black runs. It is a logic circuit. The decoding logic circuit 121, the decoding logic circuit 122, and the decoding logic circuit 123 all input the MH code from the shift register 101 in 9 bits each, and determine the run length, T code/M code distinction, and code length. Output to multiplexer 130. In addition, the decoding logic circuit 12
2 outputs a continuous zero detection signal. The multiplexer 130 selects one of the pieces of information output from the three decoding logic circuits according to a decoding logic selection signal 132 described later, and sets the Heran length of the run length integrator 103 to
It outputs the T code/M code distinction to the color inversion circuit 104, the code length to the code length integrator 110, and the continuous zero detection signal to the decoding logic selection circuit 131, respectively.

The decoding logic selection circuit 131 outputs a decoding logic selection signal 132 to the multiplexer 130. Run length integrator 10
3, the run length is integrated until the color inversion signal 105 is received from the color inversion circuit 104. The color inversion circuit 104 inputs a signal representing T code/M code from the multiplexer 130, and when detecting the T code, outputs a color inversion signal 105.
and a decoding logic selection signal 132. The code length integrator 110 receives the code length from the multiplexer 130 and generates the same number of shift pulses 112 as the code length. Also, the code length is integrated and the latch signal 111 is generated every 8 bits.
Output.

Next, the operation will be explained. FIG. 4 shows a general flow of the process.

A 16-bit MH code is input to the shift register 101 by a start signal (not shown). For simplicity, assume that the beginning is a white run. The lower 9 bits of the input 16 bits are the decoding logic circuit 121, the decoding logic circuit 122,
A decoding logic circuit 123 is provided. Since the beginning is a white run, the output from the decoding logic circuit 121 is selected by the multiplexer 130. Here, from the relationship in the attached table, if the lowest consecutive 8 bits of the 9 manually generated bits are not "0000 0001" in order from the LSB, the decoding logic circuit 121 will be able to determine the run length, T code/M code. Separately, the code length is output. If the code is an M code, the color inversion signal 105 becomes inactive and the run length is integrated even in the next decoding.

Further, the decoding logic selection signal 132 is also inactive, and the next decoding will also be a white run. If it is a T code, the color inversion signal 105 becomes active and the run length is newly integrated from the next decoding. Further, the decoding logic selection signal 132 also becomes active, and the next decoding becomes a black run. The code length integrator 110 generates the same number of shift pulses 112 as the code length,
The contents of shift register 101 are shifted by an amount outside the code length.

Furthermore, when the latch signal 111 becomes active, the next 8-bit MH code is input to the shift register 101. The output of the run length integrator 103 when the code becomes a T code is the decoded data. If the lowest 8 consecutive bits of the 9 input bits are “0000 000”
1", the decoding logic circuit 121 outputs a continuous zero detection signal in addition to the run length, T code/M code distinction, and code length. At this time, the run length is "0", and the T code /M
The code is M code, and the code length is "4".The color inversion signal 105 becomes inactive and the rerun length is accumulated even in the next decoding.The decoding logic selection circuit 131 detects consecutive zeros. It inputs the signal and the color inversion signal 105 and outputs a decoding logic selection signal 132, instructing to switch the decoding logic circuit to be selected to the decoding logic circuit 122, although the next decoding is also a white run. The code length integrator 110 generates the same number of shift pulses 112 as the code length, that is, 4.The contents of the shift register 101 are shifted by 4 predetermined bits.Next, the shift register 1 is shifted again.
The lower 9 bits from 01 are input to the restoration logic circuit 121, the decoding logic circuit 122, and the decoding logic circuit 123. Due to the operation described above, the output from decoding logic circuit 122 is now selected by multiplexer 130. The following operation is
This is the same as described above.

Next, consider the case of black orchid. shift register 1
The 9 bits of the MH code input from 01 are sent to the decoding logic circuit 121, the decoding logic circuit 122, and the decoding logic circuit 123.
Enter. In the case of a black run, from the relationship in the attached table, if the lowest consecutive 4 bits of the 9 manually generated bits are not "0000" in order from the LSB, the decoding logic circuit 12
3 is selected by multiplexer 130. The decoding logic circuit 123 outputs the run length, T code/M code distinction, and code length. In this case, since the code is a T code, the color inversion signal 105 becomes active and the rerun length is newly integrated from the next decoding.

Further, the decoding logic selection signal 106 also becomes active, and the next decoding becomes a white run. The code length integrator 110 generates the same number of shift pulses 112 as the code length, and the shift register 1
The contents of 01 are shifted by the code length. Furthermore, if the latch signal 111 becomes active, the shift register 10
1, the next 8-bit MH code is input. The output of run length integrator 103 is decoded data. If the lowest 4 consecutive bits of the 9 manually generated bits are “000”
If it is 0, decoding logic circuit 122 is selected. The decoding logic circuit 122 outputs a continuous zero detection signal in addition to the run length, T code/M code distinction, and code length.

The run length at this time is 11011, the T code/M code is an M code, and the code length is 4''.The color inversion signal 105 becomes inactive and the run length is integrated in the next decoding. The decoding logic selection circuit 131 outputs the decoding logic selection signal 106 by manually inputting the continuous zero detection signal and the color inversion signal 105, and decodes the decoding logic circuit to be selected again since there is a black run in the next decoding. The code length integrator 110 generates the same number of shift pulses 112 as the code length, that is, 4. The contents of the shift register 101 are shifted by 4 bits. The lower 9 bits from the shift register 101 are the decoding logic circuit 121, the decoding logic circuit 122, and the decoding logic circuit 1.
I'm 23 years old. Due to the above-described operation, the output from the decoding logic circuit 122 is selected by the multiplexer 130 this time as well. The following operations are similar to those described above.

According to this embodiment, the input to the decoding logic circuit may be 9 bits. Furthermore, since the decoding logic circuit 123 only deals with the case of short black runs, the decoding logic circuit 123 can be constructed from a simple logic circuit. The remaining two decoding logic circuits are R
When trying to configure with OM, the total number of bits is 29X17X
2=17 bits. In addition, the decoding logic circuit 12
Even if you add the hardware of 3 logic circuits, multiplexer 130, and decoding logic selection circuit 131, the
= 272 bits, which is far less than the hardware amount of a ROM.

FIG. 2 is a block diagram showing a second embodiment of the present invention. In the same figure, input register 241, input register 24
2 inputs the MH code using a latch signal 243 and a latch signal 244, which will be described later, respectively. barrel shifter 201
is a register for manually inputting the code string of the MH code to the decoding logic circuit 221, the decoding logic circuit 222, and the decoding logic circuit 223. The barrel shifter 201 has 16 bits, and inputs the code string of the MH code from the manual register 241 and the input register 242 in response to a latch signal 211, which will be described later. In the figure, the top is the MSB and the bottom is the LSB.

Furthermore, the data inside is shifted in the LSB direction by the number of bits indicated by the shift number 213 by a shift pulse 212 to be described later. In this embodiment, the decoding logic circuit 221
is a decoding logic circuit for white run, decoding logic circuit 22
2 is a decoding logic circuit for the black run and the monochrome common run, and a decoding logic circuit 223 is a decoding logic circuit for some of the black runs. Decoding logic circuit 221, decoding logic circuit 2
22, the decoding logic circuit 223 inputs the MH code from the barrel shifter 201 in 9 bits each, and calculates the run length,
Multiplexer 2 determines T code/M code and code length.
Output to 30. The decoding logic circuit 221 and the decoding logic circuit 222 output continuous zero detection signals. The multiplexer 230 selects one of the pieces of information output from the three decoding logic circuits according to a decoding logic selection signal 232 to be described later, and transmits the Heran length of the run length integrator 203 to the color inversion circuit 204. The difference between code/M code,
The code length is sent to the code length integrator 210, and the decoding logic selection circuit 2
A continuous zero detection signal is output to 31, respectively. The decoding logic selection circuit 231 outputs a decoding logic selection signal 232 to the multiplexer 230. The run length integrator 203 is
The run length is integrated until the color inversion signal 205 is received from the color inversion circuit 204. The color inversion circuit 204 is connected to the multiplexer 2
Input a signal indicating the T code/M code from 30,
When it detects that it is a T code, it outputs a color inversion signal 205 and a decoding logic selection signal 206.

The code length integrator 210 receives the code length from the multiplexer 230 and generates a shift pulse 212 and a shift number 213. Further, the code length is integrated and a latch signal 211 is output every 8 bits.

In this embodiment, the operation of code length integrator 210 is different from that in the first embodiment. When the code length is input manually from the multiplexer 230, the code length integrator 210 generates a shift pulse 21.
Generates 2. Also, at this time, a shift number 213 is outputted at the same time, and this value is given by the remainder of 8 of the cumulative value of the code lengths. In addition, the latch signal 211 is transmitted to the barrel shifter 20.
1, and also to either the input register 241 or the manual register 242. The latch signal 243 and the latch signal 244 at this time are generated from the latch signal 211.

In this embodiment, since the MH code is shifted in one clock using a barrel shifter, there is an advantage that processing is faster than in the first embodiment.

[Effects of the Invention] As explained above, according to the present invention, the amount of hardware of the MH code decoder can be reduced.

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[Brief explanation of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention, FIG. 2 is a block diagram showing a second embodiment of the present invention, FIG. 3 is a block diagram showing an example of a conventional MH code decoder, FIG. 4 is a flowchart showing a general flow of processing in the first embodiment. 101, Shift register, 10318. Run length integrator, 104, Color inversion circuit, 105, Color inversion signal, 110, Code length integrator, 111, Latch signal, 112, Shift pulse, 121, 122, 123. ,,decoding logic circuit, 130
, multiplexer 131 , decoding logic selection circuit 132 , decoding logic selection signal 201 , barrel shift 203 , run length integrator 204 , color inversion circuit 205 , , Color inversion signal 210 , Code length integrator 211 , Latch signal 212 , Shift pulse 213 , Shift number 221.222, 223 . ,,decoding logic circuit, 230
, ,Multiplexer, 231, ,Decoding logic selection circuit, 232, ,Decoding logic selection signal, 241.242. ,,input register, 243.244. ,,Latch signal. Patent applicant Kiyoshi Kuwai, agent for NEC Corporation, patent attorney - Figure 1 Figure 3

Claims (1)

[Claims] A decoder for decoding an MH code, the decoder includes a plurality of decoding logic circuits including a decoding logic circuit for detecting a specific pattern, and a decoding circuit for determining which one to select from among the decoding logic circuits for detecting the specific pattern. The decoding logic circuit has a decoding logic selection circuit that forms a logic selection signal, a multiplexer controlled by the decoding logic selection signal output from the decoding logic selection circuit, and an input shift circuit, and detects the specific pattern. An MH code decoder characterized in that when a specific pattern is detected, data in the input shift circuit is shifted by a predetermined number of bits.