JPS63255787A - Portable medium - Google Patents

Abstract

PURPOSE:To generate magnetic data at the reading speed of a reader by generating magnetic data from a magnetic generating member at a driving rate according with an instruction. CONSTITUTION:A contact part 11 arranged in a position according with the standard of an IC card 10, a keyboard part 12, a display part 13 which is arranged on the upper face of the keyboard part 12 and consists of a liquid crystal display element, and magnetic generating members 14 and 14b are provided on the surface of the IC card 10. Information to designate transaction contents is stored in a data memory 31. When the driving rate of magnetic data generation is instructed by the keyboard pat 12, magnetic data is generated from magnetic generating members 14a and 14b at the driving rate according with this instruction by a magnetic generating member control circuit 40.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) The present invention has a built-in CPU, data memory, internal battery, etc., and can be used as a stand-alone card in a calculator or the like.
The present invention relates to portable media such as multifunctional IC cards that are used by inserting them into terminals.

(Prior Art) Conventionally, multifunctional IC cards have been developed that have a built-in CPU, data memory, internal battery, etc., and can be used as a stand-alone card for calculators, time, etc., or can be used by being inserted into a terminal. Among such IC cards, one having a magnetic generation element that generates magnetic data corresponding to the magnetic stripe of a conventional magnetic card is considered. This makes it possible to conduct transactions (shopping) using magnetic stripe readers (external equipment, MS League) currently installed in stores and the like.

In this case, if the reader is a manual type, magnetic data is generated by inserting a start key with the magnetic generation element of the card corresponding to the magnetic head of the reader. In addition, if the reader is an automatic transfer type, the magnetic data can be read by loading a part of the card into the reader and inserting the start key with the magnetism generating element and the reader's magnetic head in correspondence. It's starting to happen.

However, in the above-mentioned magnetic data generation speed there is only one type, although there are automatic conveyance type readers and manual type readers with various reading speeds on the market. For this reason, there was a drawback that it was not possible to handle a wide variety of readers.

(Problems to be Solved by the Invention) As mentioned above, the present invention eliminates the disadvantage of not being able to handle a wide variety of readers, and generates magnetic data in accordance with the reading speed, that is, the drive rate, of the reader. is possible,
A conventional reader can be used as is [Structure of the Invention] (Means for Solving Problems) A portable medium of the present invention includes an input means and a control element for controlling each part including the input means,
A storage means for storing information specifying transaction details, a magnetic generation member for generating magnetic data to an external device, an instruction means for instructing a driving rate of magnetic data generation by the magnetic generation member, and an instruction by the instruction means. It is comprised of a driving means for driving the magnetism generating member at a driving rate and in accordance with the storage contents stored in the storage means.

(Function) This invention provides a magnetic generation member that generates magnetic data instead of a magnetic stripe, instructs the drive rate at which the magnetic data generation member generates magnetic data, and generates the magnetic data at a drive rate according to this instruction. The magnetic data is generated by the members.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

In FIG. 3, 10 is an IC card as a portable medium, which is a multifunctional card having various functions. For example, an online function that is used using a terminal described below, an offline function that allows the IC card 10 to operate independently,
and has a wait state that only counts the clock.

The above offline functions include a calculator mode that can be used as a calculator, a time display mode that displays the time according to the user's clock, a time change mode that changes the time of the user's clock, address, and name. ,
Electronic book mode for registering and reading phone numbers, etc., or IC card 10? It has a shopping mode where it can be used as a U number credit card or a cash card.

On the surface of the IC card 10, there is a contact section (connection means) 11 arranged at a position that matches the card specifications, a keyboard section (display means) 12 consisting of 20 keys, and a liquid crystal display arranged on the top surface of this keyboard section 12. A display section (display means) 13 formed of display elements and a magnetism generating member 14a
, 14b are provided.

” 1. The contact portion 11 includes a plurality of terminals 11a, for example.
~llf. The terminal 11a is for operating power supply voltage (+5V, Vcc), the terminal 11b is for grounding, the terminal 11c is for a clock signal, the terminal 11d is for a reset signal, and the terminals 11e to llf are for data input/output.

The keyboard section 12 includes mode keys (Ml, M2, M3, M4) 12a for specifying processing modes.

Numeric keypad 12b1 Four arithmetic operation keys as function keys, that is, addition (+) key 120. Subtraction (-) key 12
d, division (÷) key 12e1, multiplication +1, (x) key 12f, S decimal point (,) key 12g1, and equal (-) key 12h.

The mode key 12a is used for calculator mode (N11) when offline, that is, when processing is performed only with the IC card 10.
Processing for time display mode (M2), electronic passbook mode (M3), or shopping mode (M4) is selected. Further, in the shopping mode, processing corresponding to the type of card, ie, various credit cards, cash cards, etc., is selected according to the combination of the M4 key and the numeric keypad 12b.

The addition key 12C is used as a NEXT key, that is, a key to advance the display state of the display section 13 to the next step, and the subtraction key 12d is used as a BACK key, that is, a key that returns the display state of the display section 13 to the previous one. The key 12f is used as a start key, the decimal point key 12g is used as a No key and an end key, and the equal key 12h is used as an end key.
is used as a YES key and a power-on key.

The display section 13 is a 16-digit dot matrix with each digit being 5×7.

- The magnetism generating parts 14a and 14b are embedded inside the IC card 10 in alignment with the track position of a magnetic card reader (magnetic head) on the reading side (not shown).

FIG. 4 shows an IC card reading/writing unit 1 used in a terminal such as a personal computer that handles an IC card 10.
This shows the appearance of No. 6. In other words, card insertion slot 1
By connecting with the contact part 11 of the IC card 10 inserted from 7, data in the memory of the IC card 10 can be read or data can be written into the memory.

The IC card reading/writing section 16 is connected to the main body of a personal computer (not shown) by a cable.

Further, the electric circuit of the IC card 10 is constructed as shown in FIG. That is, the contact portion 1
1. Communication control circuit 21, reset control circuit 22, power supply control circuit 23, for example, a 3-volt internal battery (built-in power supply) 25, and a battery check circuit that checks whether the voltage value of this internal battery 25 is above a specified value. 24,
A clock control circuit 26, an oscillator 27 which is a crystal oscillator for arithmetic clock oscillation and outputs a signal with an oscillation frequency (high frequency) of IMHz, a CPU (central processing unit) 28 for control, and a control program is recorded therein. A program ROM 29, a program working memory 30, a data memory 31 that stores a password (for example, 4 digits), data, etc. and is composed of a FROM, a timer 32 used for timing during processing, a calendar circuit 33, and a basic An oscillator 34 which is a crystal oscillator for clock oscillation and always outputs a signal with an oscillation frequency of 32.768KH2 (low frequency and high precision), a display control circuit 35, and a display unit that drives the display unit 13. driver 36
, a keyboard interface 38 as a key input circuit of the keyboard section 12, and the magnetism generating member 1.
It is constituted by a magnetism generating member control circuit 40 that controls 4a and 14b.

Magnetism generating member control for controlling the communication control circuit 21, CPU 28, ROM 29, program working memory 30, data memory 31, timer 32, calendar circuit 33, display control circuit 35, keyboard interface 38, and magnetism generating member 14a114b. The circuits 40 are adapted to be connected by a data bus 20.

When the communication control circuit 21 receives data, that is, the terminal 16
The serial input/output signals supplied from the contact section 11 are converted into parallel data and sent to the data bus 2.
0, and during transmission, that is, parallel data supplied from the data bus 20 is converted into a serial input/output signal and output to the terminal 16 via the contact section 11. In this case, the format contents of the conversion are determined by the terminal device 16 and the IC card 10.

When the reset control circuit 22 goes online, it generates a reset signal and starts the CPU 28.

- When the power distribution control circuit 23 goes online, it switches from being driven by the internal battery 25 to being driven by an external power supply after a predetermined period of time has elapsed, and when it goes offline, that is, when the external voltage drops, it is driven by the external power supply. This is to switch from drive to internal battery 25.

The clock control circuit 26 stops an oscillation circuit 67 that outputs a signal at an oscillation frequency (high frequency) of I NIHZ, which will be described later, during standby, that is, when the key is in standby mode, in an offline mode in which the card operates using the internal battery 25. Furthermore, the supply of clocks to the CPU 28 is also stopped, and the CPU 28 stands by in a completely stopped state. Furthermore, when the oscillation circuit 67 is restarted from a stopped state, the clock control circuit 26 is operated for 500 to 600 m5e until stable oscillation is performed.
During the period c, the clock is outputted as a clock for the CPU 28, and the first person's key is processed.

Furthermore, when the clock control circuit 26 goes online, that is, when a reset signal is supplied, it outputs the watch clock as a clock for the CPU 28 for 500 to 600 m5ec until stable oscillation occurs, and then It is designed to output the IMH2 clock.

The data memory 31 records information corresponding to a plurality of contracted credit cards (companies) and information corresponding to a cash card. The information is read out in accordance with the type of card selected using the numeric keypad 12b according to the numerical keys displayed on the display section 13 and the abbreviations such as credit company names and bank names.

The above information is the same as the information recorded on the conventional magnetic stripe for each card.

For example, first track data corresponding to the first track of the card and second track data corresponding to the second track are stored.

The calendar circuit 33 has a display clock that can be freely set and changed by the card holder, and a transaction clock that sets, for example, world standard time when the card is issued and cannot be changed thereafter. ing.

The display unit control circuit 35 converts the display data supplied from the CPU 28 into a character pattern using a character generator (not shown) configured with an internal ROM, and converts the display data supplied from the CPU 28 into a character pattern on the display unit 13 using a display unit driver 36. It is to be displayed.

The keyboard interface 38 converts keys manually pressed on the keyboard section 12 into key manual signals corresponding to the keys, and outputs the signals to the CPU 28.

When a shopping mode and a card type are specified, the magnetism generating member control circuit 40 controls the data supplied from the data memory 31 via the data bus 20 and the specified data corresponding to the card type. By controlling the drive of the magnetism generators +414a and 14b according to the driving rate (1 to 8KH2, 0.5 to 4KH2) and outputting the first track data and the second track data as magnetic information. , which is in the same state as a conventional magnetic stripe.

For example, if the "1" key in the numeric keypad 12b is pressed when selecting the drive rate, lKH2 is selected as the drive rate for the data for the first track, and 0.5KH2 is selected as the drive rate for the data for the second track. It is now selected.

Also, "2", "3", "4", "5", "6", "7"
”, “8” key is pressed, the driving rate of the data for the first track is 2.3.4.5.6.7 respectively.
．． 8KH2 is selected and the driving rate of the data for the second track is 1.1.5.2.2.5.3.3.5.4K.
H2 is selected. These conditions, that is, the correspondence relationships are stored in advance in the program ROM 29.

The power supply control circuit 23 will be explained in detail using FIG. 5. That is, inverter circuit 51.54.55
, a counter 52, a D-type flip-flop circuit (FF circuit) 53, and a semiconductor switch 56 composed of a MOSFET.
．． 58, a diode 57, and an internal battery 25.

The count value of the counter 52 is a value that is not affected by chattering of the external power supply. The above diode 57
is for protecting the power supply voltage Vout, and when the power supply voltage Vcc from the outside decreases, the power supply voltage Vout will not drop even if the power supply voltage Vcc drops below the memory drive voltage before the semiconductor switch 56 is turned on. As shown, it is protected by an internal battery 25.

The operation of this configuration will be described with reference to the timing chart shown in FIG. That is, when the IC card 10 is not connected to the terminal device 16 through the contact section 11, the semiconductor switch 56 is turned on.
The power supply voltage of the internal battery 25 is applied to each part via the semiconductor switch 56 as the output Vout of the power supply control circuit 22.

Further, when the IC card 10 is connected to the terminal device 16 through the contact section 11, an external power supply voltage Vcc is supplied to the gate of the semiconductor switch 58, and a clock signal CLK is supplied to the counter 52 via the inverter circuit 51. is supplied to the clock terminal ck of. As a result, the counter 52 starts counting, and when the value of the counter 52 reaches a predetermined value, the FF circuit 5
Set 3. Due to the set output Q of the FF circuit 53, a "0" signal is supplied to the gate of the semiconductor switch 58, a "1" signal is supplied to the gate of the semiconductor switch 56, the semiconductor switch 58 is turned on, and the semiconductor switch 56 is turned on.
turns off.

Therefore, the external power supply voltage Vcc is applied to each part via the semiconductor switch 58 as the output Vout of the power supply control circuit 22.

Note that when returning from the online state to the offline state, a reset signal is output from the reset control circuit 22 when the external power supply voltage Vcc decreases. This results in
The reset signal causes the counter 52 and the FF circuit 53 to
is reset. Then, a "1" signal is supplied to the gate of the semiconductor switch 58, a "0" signal is supplied to the gate of the semiconductor switch 56, the semiconductor switch 58 is turned off, and the semiconductor switch 56 is turned on. Therefore, the power supply voltage of the internal battery 25 is applied to each part via the semiconductor switch 56 as the output Vout of the power supply control circuit 22.

The clock control circuit 26 will be explained in detail using FIG. 7. That is, the stop signal HALT from the CPU 28 is supplied to the clock input terminal ck of the FF circuit 62. The set output of this FF circuit 62 is
The machine cycle signal M1 from the CPU 28 is supplied to the clock input terminal ck of this FF circuit 63. The FF circuits 62 and 63 are used for stop mode timing. Above FF circuit 6
The set output of 3 is supplied to the data input terminal of the FF circuit 64, and the clock input terminal ck of this FF circuit 64 is supplied with the clock of 32.763 KH2 from the calendar circuit 33. The reset output of the FF circuit 64 is supplied to the data input terminal of the FF circuit 65, and the clock input terminal ck of the second OFF circuit 65 is supplied with the 32.763KH2 clock from the calendar circuit 33. . The FF circuit 65 is used to stop clock oscillation. The set output of the FF circuit 65 is supplied to one end of a NAND circuit 66, and an oscillation circuit 67 is connected between the output end and the other end of the NAND circuit 66.

Further, the key interrupt signal from the CPU 28 and the reset signal from the reset control circuit 22 are supplied to the reset input Fa R of the FF circuit 62, 63, 64 via the OR circuit 61, and It is supplied to the set input terminal S of the FF circuit 65.

” The two-legged oscillation circuit 67 includes the oscillator 27 having an oscillation frequency of IMHZ, a resistor 68, and a capacitor 70.71.
It is made up of.

The output of the NAND circuit 66 is supplied to the clock input terminal ck of the FF circuit 74 via the inverter circuit 72, and also to one end of the NAND circuit 75 via the inverter circuits 72 and 73.

Further, the reset signal from the reset control circuit 22 is supplied to the set input terminal S of the FF circuit 76, and the clock input terminal ck of the two-OFF circuit 76 is supplied to an OR circuit 84, which will be described later.
output is supplied.

Further, a clock selection signal from the CPU 28 is supplied to the data input terminal D1 and the reset input terminal R of the FF circuit 76. The set output of the FF circuit 76 is FF
It is supplied to the data input end of the circuit 77, and this OFF circuit 7
A clock of 32.763 KH2 from the calendar circuit 33 is supplied to the clock input terminal ck of No. 7.

The set output of the FF circuit 77 is supplied to one end of the NAND circuit 79, and the 32.763 KHz clock from the calendar circuit 33 is supplied to the other end of the NAND circuit 79 via the inverter circuit 78. be done. The output of the NAND circuit 79 is supplied to one end of a NAND circuit 80.

Further, the reset output of the FF circuit 77 is supplied to the data input end of the FF circuit 74, and the set output of this FF circuit 74 is supplied to the other end of the NAND circuit 75. The FF circuit 74 is used for clock switching.

The outputs of the NAND circuits 75 and 79 are supplied to the NAND circuit 80, and the outputs of the NAND circuit 80 are fed to the FF circuits 81 and 81.
3 is supplied to the clock input terminal ck of the FF circuit 81.
The set output of the FF circuit 63 is supplied to the data input terminal of the FF circuit 63 via an inverter circuit 82.

The set output of the FF circuit 81 and the FF circuit 8
The reset output of No. 3 is outputted to the clock input F4 c k of the FF circuit 76 via the OR circuit 84.

Further, the set output of the FF circuit 83 is provided by a NAND circuit 86.
The output of the AND circuit 80 is supplied to the other end of the NAND circuit 86 via an inverter circuit 85. The output of the NAND circuit 86 is output to the CPU 28 as a clock signal.

The operation in such a configuration will be explained. First, the stopped state will be explained. That is, "1" is supplied from the CPU 28 as the clock selection signal. As a result, the FF circuits 76 and 77 are set. Thereby, the watch clock (32,768KH2) is guided to the FF circuits 81.82 and the inverter circuit 85 via the inverter circuit 78 and the NAND circuits 79.80.

Next, restarting from a stopped state will be explained.

That is, a key human interrupt signal is supplied from the CPU 28. Then, the FF circuits 62, 63, and 64 are reset, and the FF circuit 65 is set.

The set output of the FF circuit 65 enables the oscillation circuit 67. As a result, the oscillation circuit 67 resumes oscillation.

Furthermore, by resetting the FF circuit 63, the FF circuit 8
“1” is supplied to the data input end of “1”. As a result, the output of the NAND circuit 80 causes the FF circuit 8 to
1.83 is set and opens the gate of NAND circuit 86.

Therefore, the clock from the inverter circuit 85 is output to the CPU 28 via the NAND circuit 86.

At this time, the oscillation circuit 67 normally oscillates for 50 seconds until it stably oscillates.
0 to 600 msec is required.

As a result, the CPU 28 supplies "0" to the data input end of the FF circuit 76 as a clock selection signal 500 to 600 m5 e after outputting the key human interrupt signal. As a result, the FF circuits 76 and 77 are reset, and the reset output of the FF circuit 77, that is, the "1" signal is supplied to the data input end of the FF circuit 74.

Also, at this time, the clock (IMH2
) is supplied to the clock input terminal of the FF circuit 74 via the inverter circuit 72.

Therefore, the FF circuit 74 is set, and this set output opens the gate of the NAND circuit 75 (.

As a result, the clock (IMH2) generated by the oscillation circuit 67 is generated by the inverter circuit 72.73, the NAND circuit 75.80,
The signal is sequentially output to the CPU 28 via an inverter circuit 85 and a NAND circuit 86.

As a result, by setting the clock selection signal to "O", synchronization is achieved in the FF circuit 74, and the clock is switched from the clock for high-speed processing to the clock for high-speed processing.

Next, a case will be described in which the processing is ended and the system is placed in a stopped state (standby state). That is, by setting the clock selection signal to "1", the FF circuits 76 and 77 are set, the set output of the FF circuit 77, that is, the "1" signal is supplied to the NAND circuit 79, and the gate of the NAND circuit 79 is opened. There is. Therefore, the clock for the watch consists of the inverter circuit 78, the NAND circuit 79.80, and the inverter circuit 8.
5, and is output to the CPU 28 via the NAND circuit 86.

As a result, the watch clock is output to the CPU 28 again.

Next, a stop signal is supplied from the CPU 28 to the data input end of the FF circuit 62. Then, the FF circuit 62 is set, and the set output is supplied to the data input end of the FF circuit 63. Then, the FF circuit 63 is set by the machine cycle signal M1 from the CPU 28, and a "0" signal is supplied to the data input terminal of the FF circuit 81. As a result, the set output of the FF circuit 63 is changed to the set output of the FF circuit 81.8.
After sending two pulses in step 3, the gate of the NAND circuit 86 is closed to stop outputting the clock to the CPU 28. As a result, the CPU 28 is brought to a halted state.

Further, the set output of the FF circuit 63 is the FF circuit 64.
After sending two pulses at step 65, the gate of the NAND circuit 66 is closed to stop the oscillation by the oscillation circuit 67.

As a result, after stopping the output of the clock to the CPU 28, the oscillation circuit 67 is stopped.

In this way, the clock control circuit 26 operates as an oscillator 27.
In order to cover the rising edge of the crystal oscillation caused by this, the clock for the watch and the clock for the IMH2 are effectively switched.

The calendar circuit 33 will be explained in detail using FIG. 8. That is, the oscillator 34 of 32.768 KH2
A frequency dividing circuit 91 outputs signals every second from output terminals a and b by dividing the oscillation output of the frequency dividing circuit 9.
A counter 92 that outputs a signal every 10 seconds by counting the signal from the output terminal a of No. 1, and a counter 92 of No. 20.
A counter 93 that outputs a signal every 60 seconds, that is, every minute, by counting the signals from this counter 93, a counter 94 that outputs a signal every 10 minutes by counting the signals from this counter 93, and a counter 94 that outputs a signal every 10 minutes by counting the signals from this counter 93. A counter 95 that outputs a signal every 60 minutes, that is, every hour, by counting the signals from this counter 95, and a counter 96 that outputs a signal every 24 hours, that is, every day, by counting the signals from this counter 95. A counter 97 outputs a signal every 10 seconds by counting the signal from the output terminal of the circuit 91, and a signal 9 is output every 60 seconds, that is, every minute by counting the signal from this counter 97. a counter 98 that outputs a signal every 10 minutes by counting the signal from this counter 98;
9. A counter 1 that outputs a signal every 60 minutes, that is, every hour, by counting the signal from this counter 99.
00, and a counter 101 that outputs a signal every 24 hours, that is, every day by counting the signals from this counter 100.

Here, the counters 92 to 96 constitute a transaction clock that counts seconds, minutes, and hours, and the counters 97 to 1 constitute a clock for counting seconds, minutes, and hours.
01 constitutes a display clock that counts seconds, minutes, and hours. The contents of the counters 97 to 101, that is, the counted values, can be changed using the keyboard section 12, while the contents of the counters 92 to 96, that is, the counted values cannot be changed using the keyboard section 12.

In addition, the year, month, day, and day of the week are displayed on the counter 9 every 24 hours.
6. An interrupt request is output to the CPU 28 by the signal from 101. Thereby, the CPU 28 uses the data memory 31 to update the year, month, day and day of the week of the corresponding area. Furthermore, as shown in FIG. 9, the phases of the base clocks of 1 second are shifted in the two clocks, so that interrupts do not occur at the same time.

The magnetism generating member control circuit 40 will be described in detail using FIG. 10. That is, command data supplied from the CPU 28 via the data bus 20 is supplied to the command FF circuit 110. This FF circuit 1
10 consists of four FF circuits, and depending on the command data supplied from the data bus 20, a clock selection signal corresponding to the drive rate for the first track is output from the output terminal 110a, a start signal is output from the output terminal 110b, or a start signal is output from the output terminal 110c. A clock selection signal corresponding to the drive rate for the second track is output from the output terminal 110d, and a start signal is output from the output terminal 110d.

A command write start signal from the CPU 28 is supplied to the clock input terminal cp of the lHaFF circuit 110. The clock selection signal corresponding to the drive rate indicates each selected frequency.

The clock selection signal output from the output terminal 110a of the FF circuit 110 is transmitted to the input terminals 5o-52 of the selection circuit 111.
supplied to The input terminal of this selection circuit 111 is supplied with eight types of signals having frequencies of 1 to 8KH2 from a clock generation circuit 127. The selection circuit 111 selects the F
According to the clock selection signal from the output terminal 110a of the F circuit 110, when the drive rate of the reader is "1", lKH
If the 2KH2 signal is selected and output from the output terminal Y, and the reader drive rate is "2", the 2KH2 signal is selected and output from the output terminal Y, and the reader drive rate is "3". case,
If the 3KH2 signal is selected and output from the output terminal Y, and the reader drive rate is "4", the 4KH2 signal is selected and output from the output terminal Y, and the reader drive rate is "5". In this case, select the 5KH2 signal and output it from the output terminal Y,
When the reader drive rate is "6", the 6KH2 signal is selected and output from the output terminal Y, and the reader drive rate is "6".
If the reading rate is "7", the 7KH2 signal is selected and output from the output terminal Y, and if the reader drive rate is "8", the 8KH2 signal is selected and output from the output terminal Y.

The start signal output from the output end 110b of the FF circuit 110 and the output of the selection circuit 111 are supplied to a timing circuit 112.

This timing circuit 112 generates a hexadecimal clock,
Clock input terminal c of parallel/serial conversion circuit 115
The first clock d1 is supplied to the load input terminal of the parallel/serial conversion circuit 115 as a load signal. Further, the timing circuit 112 has data “0”.
Select circuit 11 for selecting clock for data “1” and clock for data “1”
6.

Further, first track data as magnetic data supplied from the CPU 28 via the data bus 20 (varies depending on the type of card selected) is supplied to the data latch circuit 113.
A data write start signal is supplied from the CPU 28.

The data latch circuit 113 operates on the data bus 2 when a data write start signal is supplied from the CPU 28.
It latches magnetic data of 7 bits supplied from 0 onwards.

The data latched in the data latch circuit 113 is 7
It is supplied to the data input terminal IN of the parallel/serial conversion circuit 115 for bits. The parallel/serial conversion circuit 115 loads the data from the data latch circuit 113 in response to the supplied load signal, shifts the loaded data in order, and converts the data into 1-bit signals (
The output signal is converted into a 1" signal or a 0 signal) and output.

The output of the parallel/serial conversion circuit 115 is supplied to the input terminal S of the selection circuit 116. This selection circuit 11
6 selects and outputs the clock for data "1" supplied from the timing circuit 112 when a "1" signal is supplied to the input terminal S, and a "0" signal is supplied to the input terminal S. In this case, the clock for data "0" supplied from the timing circuit 112 is selected and output. The output of the selection circuit 116 is the J-KFF circuit 11
The set output and reset output of this J-KFF circuit 117 are supplied to a driver 118.

This driver 118 generates a magnetic field by driving the magnetism generating member 14a in response to a signal from the FF circuit 117. For example, when the FF circuit 117 is set, it generates a magnetic field as shown by arrow C, and when it is reset, it generates a magnetic field as shown by arrow d.

Incidentally, a timing chart of the main parts of the magnetism generating member control circuit 40 is as shown in FIG.

In the selection circuit 116, as shown in FIG.
The clock cycle ratio for data "1" and "0" is 1:2. This clog J-
By operating the KFF circuit 117 in the inversion mode, "1" and "O" signals in the format required as magnetic data (data for the first track) are obtained and drive the magnetism generating member 14a. .

Further, the data write start signal from the CPU 28 is inverted and supplied to the set input terminal of the empty detection OFF circuit 114, and the reset input terminal of the second OFF circuit 114 receives the first clock signal from the timing circuit 1]2. is inverted and supplied. As a result, when the data of the data latch circuit 113 is loaded into the data latch circuit 115, the FF circuit 114 is set and the FF circuit 1
14 set outputs, ie, buffer empty signals, are supplied to the CPU 28.

As a result, the CPU 28 determines that the next data can be set, and transfers the next data to the data latch circuit 1.
Output to 13. In this way, the CPU 28
While sensing the output of the F circuit 114, the data is set in order, and after all the data is output, the command write start signal and the data write start signal are turned off. 11
2 stops generating the signal, and the operation ends.

Note that each of the circuits 111 to 118 is a circuit for the first track, and the circuit for the second track also includes a clock generation circuit 128, a selection circuit 119, and a timing circuit 1.
20, data latch circuit 121, empty detection FF circuit 12
2. Parallel/serial conversion circuit 123, selection circuit 12
4, a J-KFF circuit 125, and a driver 126. However, the timing circuit 120 is
The parts that operate in the system are different. Further, the selection circuit 119 is supplied to the input terminal S o=82. Eight types of signals having frequencies of 0.5 to 4.0 KH2 are supplied to the input terminal of the selection circuit 119 from the clock generation circuit 128. The selection circuit 119 drives the reader according to the clock selection signal from the output terminal 110C of the FF circuit 110, and selects a signal of 0.5KH2 when the signal is "1", and selects a signal of 0.5KH2 when the signal is "2". Please select the 1,0KH2 signal and select "
3", select the 1.5KH2 signal, "4", select the 2.0KH2 signal, and "5", select the 2.0KH2 signal.
Select 5KH2 signal, if "6", 3,0KH2
In the case of "7", the 3.5KH2 signal is selected, and in the case of "8", the 4.0KH2 signal is selected and output from the output terminal Y.

As described above, the magnetism generating member control circuit 40 generates a magnetic field using the magnetic data of a predetermined credit card or cash card selectively read out from the data memory 31 at a generation speed according to a designated drive rate. By doing so, the magnetic head on the reader side (not shown)
is supplied with the same signal as when reading a conventional magnetic stripe. For example, data for the first track is outputted by the magnetism generating member 14a in response to the first track of the card, and data for the second track is outputted by the magnetism generating member 14b in response to the second track. There is.

Next, the operation in such a configuration will be explained.

First, we will explain the offline function used by the card alone. That is, when the mode key 12a, that is, the M1 key, is used to specify the calculator mode, the calculator can be used as a calculator using the numeric keypad 12b and the four arithmetic operation keys 12.

Also, by pressing the mode key 12a, that is, the M2 key,
When the time display mode is specified, the CPU 28 reads the seconds, minutes, and hours for the display clock from the counters 97 to 101 in the calendar circuit 33, and also reads the seconds, minutes, and hours from the counters 97 to 101 in the calendar circuit 33, and
The year, month, day, and day of the week for the display clock are read from , converted into a specified format, and output to the display control circuit 35 . As a result, the display section control circuit 35 is controlled internally.

A character generator (not shown) is used to convert it into a character pattern, and a display unit driver 36 is used to convert it into a character pattern on the display unit 1.
Display in 3.

Furthermore, when the electronic book mode is specified using the mode key 12a, that is, the M3 key, the CPU 28 uses the data memory 31
The address, name, telephone number, etc. stored in the computer are read out and displayed on the display section 13. Further, when registering the address, name, etc. in the electronic book, this is done using, for example, the mode key 12a and the numeric keypad 12b. That is, "A" is rMl,2", rBJ is rM2.2", and "C" is rM3.
．． 2'', rDJ is rMl, 3'', etc. can be specified.

Further, the shopping mode will be explained with reference to the flowchart shown in FIG. For example, mode key 12a
When the shopping mode is specified using the M4 key, the user then selects the type of contracted credit card or cash card using the numeric keypad 12b, and selects the drive rate corresponding to the reader (external device).

For example, the number keys displayed on the display section 13 and the abbreviations such as credit company names, bank names, etc.
Use b to select the type of contract credit card or cash card. In addition, in response to the message "Please select the drive rate of the reader using the numeric keypad" displayed on the display unit 13, the drive rate of the reader for reading can be specified by pressing one key on the numeric keypad 12b. do.

” By making the above selection, the CPU 28 reads the first track data and the second track data from the data memory 31 as data (72 characters) corresponding to the selected credit card or cash card.
It is output to the magnetism generating member control circuit 40. Also, CPU2
8 outputs the selected and designated drive rate to the magnetism generating member control circuit 40. Further, the CPU 28 outputs command data, a command write start signal, and a data write start signal to the magnetism generating member control circuit 40.

Next, when the start key (multiplication key 12f) is turned on, the CPU 28 outputs a start signal to the magnetism generating member control circuit 40. As a result, the magnetism generating member control circuit 40 alternately generates a magnetic field from the magnetism generating member 14a according to the data for the first track of the two-legged credit, and generates a magnetic field according to the data for the second track of the credit. By generating the signal from the generating member 14b, the same signal as in the conventional case of reading the magnetic stripe of the first track is supplied to the magnetic head (not shown) on the reader side. In this case, if the drive rate is specified by the "1" key, the lKH2 signal is selected as the drive clock for the first track, and magnetic data is generated from the magnetic generation member 14a at a generation speed according to this signal. be done. Also, 0.5K is used as the drive clock for the second track.
The H2 signal is selected, and magnetic data is generated from the magnetic generation member 14b at a generation speed corresponding to this signal.

In addition, when the above drive rate is specified by the "2" key, ... "8" key, the signals 2, ...8KH2 are selected as the drive clock for the first track, and according to this signal. Magnetic data with different generation speeds are generated from the magnetic generation member 14a, and the signals 1, . The magnetism is generated from the magnetism generating member 14b.

As a result, in shopping mode, it can be used as a conventional credit card.

The output of the above magnetic data usually ends once, but if the start key (multiplication key 12f) continues to be pressed, the data will be output continuously, that is, once for the two trunks.
Repeatedly output batch data.

Next, the online function used by inserting the IC card 10 into the terminal 16 will be explained. That is,
Insert the IC card 10 into the insertion slot 17 of the terminal 16.

Then, the IC card 10 is accepted, and the connection section inside the terminal 16 and the contact section 11 of the IC card 10 are connected. Accordingly, when an external power supply voltage is supplied via the contact portion 11, the power supply control circuit 23 switches from driving by the internal battery 25 to driving by the external power supply voltage, as described above. In addition, the reset control circuit 2
2 generates a reset signal and starts the CPU 28. After this activation, if the CPU 28 confirms that it is operating online, it performs online processing according to the contents of the program ROM 29. This online processing involves exchanging data and writing new data into the IC card 10 by updating data between the terminal 16 and the IC card 10.

As mentioned above, according to the drive rate of the reader specified by the key, magnetic data can be generated at a generation speed corresponding to that drive rate, and conventional readers can be used as is, and data can be transferred correctly. can.

In the above embodiment, the drive rate of the reader is specified using the display on the display, but the invention is not limited to this, and it may be specified using a combination of various keys. For example, by inputting the 1 key and the start key, the generation frequency as the drive rate is specified as 1KH2, and by inputting the 2 key and the start key, the generation frequency as the drive rate is specified as 2KH2.
2 may be specified.

Alternatively, a number corresponding to the type of reader may be input. In this case, the drive rate corresponding to each number is stored in advance in the memory. Furthermore, the frequency corresponding to the type of reader may be manually input directly.

In addition, although an IC card is used, the present invention is not limited to this, as long as it has a data memory and a control element, and selectively outputs human output from the outside. It may be a shape.

[Effects of the Invention] As detailed above, according to the present invention, the reader can generate magnetic data in accordance with the reading speed, that is, the drive rate, and the conventional reader can be used as is, and data can be transferred correctly. It is possible to provide a portable medium that can perform the following operations.

[Brief explanation of the drawing]

The drawings are for explaining one embodiment of the present invention, and FIG. 1 is a flowchart for explaining the operation in the shopping mode, and FIG. 2 is a schematic diagram of the electric circuit of the IC card (14
Figure 3 is a plan view showing the configuration of the IC card;
FIG. 4 is a diagram showing a terminal that handles IC cards, FIG. 5 is a diagram showing an example of the configuration of a power supply control circuit, FIG. 6 is a timing chart for explaining the operation of the main parts in FIG. 5, and FIG. Figure 8 shows the configuration of the clock control circuit, Figure 8 is a schematic block diagram of the calendar circuit, Figure 9 shows the output timing of signals from the frequency dividing circuit, and Figure 10 shows the magnetic generation member control circuit. Diagrams showing configuration examples, FIGS. 11 and 12
This figure is a timing chart for explaining the operation of the main parts in FIG. 10. 10... IC card (portable medium), 11... Contact section, 12... Keyboard section, 12a... Mode key, 12b... Numeric keypad, 12c... Addition key (NEXT key), 12d--Subtraction key, 12e
Division key, 12f... Multiplication key (start key), 12
g... Decimal point key (No key, end key), 12h
...Equal key (YES key), 13...Display section,
14a, 14b... Magnetism generating member, 16... Terminal, 23... Power supply control circuit, 25... Internal battery,
28... CPU (control element), 31... data memory (storage means), 40... magnetism generating member control circuit (drive means). Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure 3 Figure 5

Claims (4)

[Claims] (1) A portable medium that has an input means and a control element that controls each part including the input means, a storage means that stores information specifying transaction details, and a magnetic generator that generates magnetic data to an external device. a member, an instruction means for instructing a drive rate for generating magnetic data by the magnetism generating member, and an instruction means for instructing the magnetism generating member at a drive rate instructed by the instruction means and in accordance with the memory content stored in the storage means. A portable medium comprising: a drive means for driving; (2) The portable medium according to claim 1, wherein the instruction by the instruction means indicates a drive rate that is within a reading range of an external device. (3) The portable medium according to claim 1, wherein the instruction means is performed by the input means. (4) The portable medium according to claim 1, wherein the drive rate is the magnetic data generation speed.