JPS63255786A - Portable medium - Google Patents

Abstract

PURPOSE:To eliminate the need of precise positioning between the read position of a reader and a magnetic generating element to improve the operability by generating magnetic data from a magnetic generating member during instruction of an indicating means. CONSTITUTION:A contact part 11 arranged in a position according with the standard of an IC card 10, a keyboard part 12, a display part 13 which is arranged on the upper face of the keyboard part 12 and consists of a liquid crystal display element, and magnetic generating members 14a and 14b are provided on the surface of the IC card 10. Information to designate transaction contents is stored in a data memory 31; and while generation of magnetic data is instructed by the keyboard part 12, magnetic generating members 14a and 14b are driven and controlled in accordance with stored contents of the data memory 31 by a magnetic generating member control circuit 40.

Description

[Detailed Description of the Invention] [Purpose of the Invention (Industrial Application Field) The present invention has a built-in CPU, data memory, internal battery, etc., and can be used as a stand-alone card in a calculator, etc.
The present invention relates to portable media such as multifunctional IC cards that are used by inserting them into terminals.

(Prior Art) Conventionally, multifunctional IC cards have been developed that have a built-in CPU, data memory, internal battery, etc., and can be used as a stand-alone card for calculators, time, etc., or can be used by being inserted into a terminal. Among such IC cards, one having a magnetic generation element that generates magnetic data corresponding to the magnetic stripe of a conventional magnetic card has been considered. This makes it possible to conduct transactions (shopping) using magnetic stripe readers (MS readers) currently installed in stores and the like.

In this case, if the reader is a manual type, magnetic data is generated by inserting a start key with the magnetic generation element of the card corresponding to the magnetic head of the reader. In addition, if the reader is an automatic transfer type, the magnetic data can be read by loading a part of the card into the reader and inserting the start key with the magnetism generating element and the reader's magnetic head in correspondence. It's starting to happen.

However, in the case of the above-mentioned automatic transport type, there is almost no problem, but in the case of the manual type, the reading range of the magnetic head is narrow, making it difficult to align the magnetic head and the magnetic generation element of the card. It had the disadvantage of poor operability. That is, even though magnetic data is generated by inserting the start key, there are cases where the magnetic head cannot read it, and the start key must be inserted again.

(Problems to be Solved by the Invention) As mentioned above, this invention eliminates the drawbacks that it is difficult to align the reading position of the reader and the magnetism generating element, and the operability is poor. [Structure of the Invention] (Means for Solving the Problems) The portable medium of the present invention eliminates the need for detailed alignment with the generating element. In those having
A storage means for storing information specifying transaction details, a magnetic generation member for generating magnetic data, an instruction means for instructing the generation of magnetic data by the magnetism generation member, and the above-mentioned storage while the instruction means is giving an instruction. It is comprised of a driving means for driving the magnetism generating member according to the memory contents stored in the means.

(Function) This invention provides a magnetic generation member that generates magnetic data instead of the magnetic stripe, and while an instruction is given by the instruction means for instructing the generation of magnetic data by the magnetic generation member, the magnetic generation member generates magnetic data. Magnetic data is generated by the members.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

In FIG. 3, 10 is an IC card as a portable medium, which is a multifunctional card having various functions. For example, an online function that is used using a terminal described below, an offline function that allows the IC card 10 to operate independently,
and has a wait state that only counts the clock.

The above offline functions include a calculator mode that can be used as a calculator, a time display mode that displays the time according to the user's clock, a time change mode that changes the time of the user's clock, address, and name. ,
Electronic width mode for registering and reading phone numbers, etc., or using the IC card 10 with multiple credit cards,
It has a shopping mode where it can be used as a cash card.

1-On the surface of the IC card 10, there are contact portions (connection means) 11.20 arranged at positions that match the card specifications.
A keyboard section (display means) 12 consisting of keys, a display section (display means) 13 disposed on the -1- side of the keyboard section 12 and formed of a liquid crystal display element, and magnetism generating members 14a and 14b are provided. There is.

The contact portion 11 includes, for example, a plurality of terminals 11a to 11a.
It is configured by llf. The terminal 11a is for operating power supply voltage (+5V, Vcc), the terminal 11b is for grounding, the terminal 11c is for a clock signal, the terminal lid is for a reset signal, and the terminals 11e to llf are for data input/output.

The keyboard section 12 includes mode keys (Ml, M2, M3, M4) 12a for specifying processing modes, and a numeric keypad 12b.
1 Four arithmetic operation keys as function keys: 1 addition (+) key 1201 subtraction (-) key 12 d1 division (÷)
It is composed of a key 12e, a multiplication (x) key 12f, a decimal point (,) key 12g, and an equal (=) key 12h.

The mode key 12a is used to select processing for heavy duty mode (Ml), time display mode (M2), electronic passbook mode (M3), or shopping mode (M4) when offline, that is, when performing processing using only the IC card 10. It is supposed to be done. Further, in the shopping mode, processing corresponding to the type of card, ie, various credit cards, cash cards, etc., is selected according to the combination of the M4 key and the numeric keypad 12b.

The addition key 12C is used as a NEXT key, that is, a key to advance the display state of the display section 13 to the next step, and the subtraction key 12d is used as a BACK key, that is, a key that returns the display state of the display section 13 to the previous one. The key 12f is used as a start key, the decimal point key 12g is used as a No key and an end key, and the equal key 12h is used as an end key.
is used as a YES key and a power-on key.

The display section 13 is a 16-digit dot matrix with each digit being 5×7.

The magnetism generating members 14a and 14b are embedded inside the IC card 10 in alignment with the track position t of a magnetic card league (magnetic head) on the reading side (not shown).

FIG. 4 shows an IC card reading/writing unit 1 used in a terminal such as a personal computer that handles an IC card 10.
This shows the appearance of No. 6. In other words, card insertion slot 1
By connecting with the contact part 11 of the IC card 10 inserted from 7, data in the memory of the IC card 10 can be read or data can be written into the memory.

The IC card reading/writing section 16 is connected to the main body of a personal computer (not shown) by a cable.

Further, the electric circuit of the IC card 10 is constructed as shown in FIG. That is, the contact portion 1
1. Communication control circuit 21, reset control circuit 22, power supply control circuit 23, for example, a 3-volt internal battery (built-in power supply) 25, and a battery check circuit that checks whether the voltage value of this internal battery 25 is above a specified value. 24,
A clock control circuit 26, an oscillator 27 which is a crystal oscillator for arithmetic clock oscillation and outputs a signal with an oscillation frequency (high frequency) of 1 kiHz, a CPU (central processing unit) 28 for control, and a control program recorded therein. 2 program ROMs, a program working memory 30, a data memory 31 consisting of a FROM, in which a password (for example, 4 digits), data, etc. are recorded, and a timer 32 used for timing during processing operations.
, a calendar circuit 33, an oscillator 34 that has a crystal oscillator for basic clock oscillation and always outputs a signal with an oscillation frequency of 32.768 KHz (low frequency and high precision), a display control circuit 35, and the display section. 13, a keyboard interface 38 as a key input circuit of the keyboard section 12, and a magnetism generating member control circuit 4 that controls the magnetism generating member 14a114b.
Consists of 0.

The communication control circuit 21, CPU 28, ROM 29, program working memory 30, data memory 31, timer 32, calendar circuit 33, display control circuit 35, keyboard interface 38, and magnetism generation for controlling the magnetism generation members 14a and 14b. Component control circuit 40
are connected by a data bus 20.

When the communication control circuit 21 receives data, that is, the terminal 16
The serial input/output signals supplied from the contact section 11 are converted into parallel data and sent to the data bus 2.
0, and during transmission, that is, parallel data supplied from the data bus 20 is converted into a serial input/output signal and output to the terminal 16 via the contact section 11. In this case, the format contents of the conversion are determined by the terminal device 16 and the IC card 10.

When the reset control circuit 22 goes online, it generates a reset signal and starts the CPU 28.

When the power supply control circuit 23 goes online, it switches from being driven by the internal battery 25 to being driven by an external power supply after a predetermined period of time has elapsed, and when it goes offline, that is, when the external voltage drops, it switches from being driven by the external power source to being driven by the external power source. This is to switch to driving by the battery 25.

The clock control circuit 26 stops an oscillation circuit 67 that outputs a signal at an oscillation frequency (high frequency) of the IMH 2, which will be described later, during standby, that is, when the key is in standby mode, in an offline mode in which the card operates with the internal battery 25.
Furthermore, the supply of clocks to the CPU 28 is also stopped, and the CPU 28 stands by in a completely stopped state. Further, when the oscillation circuit 67 is restarted from a stopped state, the clock control circuit 26 outputs the clock for the clock as a clock for the CPU 28 for 500 to 600 m5ec until stable oscillation is performed. - processing is performed.

Furthermore, when the clock control circuit 26 goes online, that is, when a reset signal is supplied, it outputs the watch clock as a clock for the CPU 28 for 500 to 600 m5ec until stable oscillation occurs, and then It is designed to output an IMHZ clock.

”-2 The data memory 31 records information corresponding to multiple credit cards (companies) with which you have a contract and information corresponding to a cash card, which is selected by the combination of the M4 key and the numeric keypad 12b. Alternatively, the information is read out in accordance with the type of card selected using the numeric keypad 12b according to the numerical keys displayed on the display section 13 and the abbreviations such as credit company name, bank name, etc.

” The bipedal information is the same as the information recorded on the conventional magnetic stripe for each card.

For example, first track data corresponding to the first track of the card and second track data corresponding to the second track are stored.

The calendar circuit 33 has a display clock that can be freely set and changed by the card holder, and a transaction clock that sets, for example, world standard time when the cart is issued and cannot be changed thereafter. ing.

- The display unit control circuit 35 converts the display data supplied from the CPU 28 into a character pattern using a character generator (not shown) configured with an internal ROM, and converts the display data supplied from the CPU 28 into a character pattern using the display unit driver 36. 13.

The keyboard interface 38 converts keys input on the keyboard section 12 into human input signals corresponding to keys, and outputs the signals to the CPU 28.

When a shopping mode and a card type are specified, the magnetism generating member control circuit 40 controls the data and reading device supplied from the data memory 31 via the data bus 20 in accordance with the card type. By controlling the drive of the magnetism generating members 14a and 14b according to the drive rate corresponding to manual reading or automatic conveyance reading, and outputting first track data and second track data as magnetic information. , which is in the same state as a conventional magnetic stripe.

For example, in the case of manual reading, a drive rate with a fast reading speed is selected, and in the case of automatic conveyance reading, a drive rate with a slow reading speed is selected.

The magnetism generating member control circuit 40 controls the magnetism generating member 14 corresponding to the track designated by the operator in accordance with the type of card when the shopping mode is designated.
Magnetic information (first track data or second track data) is generated from either a1 or 14b.

For example, the "1" key and the division key 1 in the numeric keypad 12b
By inputting 2e, the first track is designated, the generation of magnetism for the first track by the magnetism generating member 14a is selected, and the "2" key in the numeric keypad 12b and the division key 12 are pressed.
By inputting "e", the second track is designated, and the generation of magnetism for the second track by the magnetism generating member 14b is selected.

The power supply control circuit 23 will be explained in detail using FIG. 5. That is, inverter circuit 51.54.55
, a counter 52, a D-type flip-flop circuit (FF circuit) 53, and a semiconductor switch 56 composed of a MOSFET.
．． 58, a diode 57, and an internal battery 25.

The count value of the counter 52 is a value that is not affected by chattering of the external power supply. The above diode 57
is for protecting the power supply voltage Vout, and when the power supply voltage Vcc from the outside decreases, the power supply voltage Vout will not drop even if the power supply voltage Vcc drops below the memory drive voltage before the semiconductor switch 56 is turned on. As shown, it is protected by an internal battery 25.

The operation of this configuration will be explained with reference to the timing chart shown in FIG. That is, when the IC card 10 is not connected to the terminal device 16 through the contact section 11, the semiconductor switch 56 is turned on.
The power supply voltage of the internal battery 25 is applied to each part via the semiconductor switch 56 as the output Vout of the power supply control circuit 22.

Further, when the IC card 10 is connected to the terminal device 16 through the contact section 11, an external power supply voltage Vcc is supplied to the gate of the semiconductor switch 58, and a clock signal CLK is supplied to the counter 52 via the inverter circuit 51. is supplied to the clock terminal ck of. As a result, the counter 52 starts counting, and when the value of the counter 52 reaches a predetermined value, the FF circuit 5
Set 3. 20 By the set output Q of the FF circuit 53, a “0” signal is supplied to the gate of the semiconductor switch 58, a “1” signal is supplied to the gate of the semiconductor switch 56, the semiconductor switch 58 is turned on, and the semiconductor switch 58 is turned on.
6 is off. Therefore, the external power supply voltage VCC
is applied to each part via the semiconductor switch 58 as the output Vout of the power supply control circuit 22.

Note that when returning from the online state to the offline state, a reset signal is output from the reset control circuit 22 when the external power supply voltage Vcc decreases. This results in
The reset signal causes the counter 52 and the FF circuit 53 to
is reset. Then, a "1" signal is supplied to the gate of the semiconductor switch 58, a "0" signal is supplied to the gate of the semiconductor switch 56, the semiconductor switch 58 is turned off, and the semiconductor switch 56 is turned on. Therefore, the power supply voltage of the internal battery 25 is applied to each part via the semiconductor switch 56 as the output Vout of the power supply control circuit 22.

The clock control circuit 26 will be explained in detail using FIG. 7. That is, the stop signal HALT from the CPU 28 is supplied to the clock input terminal ck of the FF circuit 62. The set output of this FF circuit 62 is
The clock input terminal ck of this FF circuit 63 is supplied with the machine cycle signal M1 from the CPU 28. The FF circuits 62 and 63 are used for stop mode timing. Above FF circuit 6
The set output of 3 is supplied to the data input terminal of the FF circuit 64, and the clock input terminal ck of this FF circuit 64 is supplied with the clock of 32.763KH2 from the calendar circuit 33. The reset output of the FF circuit 64 is supplied to the data input terminal of the FF circuit 65, and the clock input terminal ck of this FF circuit 65 is supplied with the clock of 32.763KH2 from the calendar circuit 33. . The FF circuit 65 is used to stop clock oscillation. The set output of the FF circuit 65 is supplied to one end of a NAND circuit 66, and an oscillation circuit 67 is connected between the output end and the other end of the NAND circuit 66.

Further, the key human interrupt signal from the CPU 28 and the reset signal from the reset control circuit 22 are supplied to the reset input terminals R of the FF circuits 62, 63, and 64 via the OR circuit 61, and circuit 6
It is supplied to the set input terminal S of No. 5.

The oscillation circuit 67 includes an oscillator 27 having an oscillation frequency of IMH2, a resistor 68, and capacitors 70 and 71.

The output of the NAND circuit 66 is supplied to the clock input terminal ck of the FF circuit 74 via the inverter circuit 72, and also to one end of the NAND circuit 75 via the inverter circuits 72 and 73.

Further, reset No. 18 from the reset control circuit 22 is supplied to the set input terminal S of the FF circuit 76, and this FF
An OR circuit 8, which will be described later, is connected to the clock input terminal ck of the circuit 76.
4 outputs are supplied.

Further, a clock selection signal from the CPU 28 is supplied to the data input terminal D1 and the reset input terminal R of the FF circuit 76. The set output of the FF circuit 76 is supplied to the data input end of the FF circuit 77.
A clock of 32.763KH2 from the calendar circuit 33 is supplied to the clock input terminal ck of the clock.

The set output of the FF circuit 77 is supplied to one end of a NAND circuit 79, and the clock of 32.763KH2 from the calendar circuit 33 is supplied to the other end of the NAND circuit 79 via an inverter circuit 78. . The output of the NAND circuit 79 is supplied to one end of a NAND circuit 80.

Further, the reset output of the FF circuit 77 is supplied to the data input end of the FF circuit 74, and the set output of this FF circuit 74 is supplied to the other end of the NAND circuit 75. The FF circuit 74 is used for clock switching.

-1- The output of the NAND circuit 75 and 79 is the NAND circuit 80.
The output of this NAND circuit 80 is supplied to an FF circuit 81.
．． The set output of the FF circuit 63 is supplied to the data input terminal of the FF circuit 81 via the inverter circuit 82.

The set output of the FF circuit 81 and the FF circuit 8
The reset output No. 3 is outputted to the clock input terminal ck of the FF circuit 76 via the OR circuit 84.

Further, the set output of the FF circuit 83 is provided by a NAND circuit 86.
The output of the AND circuit 80 is supplied to the other end of the NAND circuit 86 via an inverter circuit 85. The output of the NAND circuit 86 is output to the CPU 28 as a clock signal.

The operation in such a configuration will be explained. First, the stopped state will be explained. That is, "1" is supplied from the CPU 28 as the clock selection signal. As a result, the FF circuits 76 and 77 are set. Thereby, the watch clock (32,768KH2) is guided to the FF circuits 81.82 and the inverter circuit 85 via the inverter circuit 78 and the NAND circuits 79.80.

Next, restarting from a stopped state will be explained.

That is, a key human interrupt signal is supplied from the CPU 28. Then, the FF circuits 62, 63, and 64 are reset, and the FF circuit 65 is set.

The set output of the FF circuit 65 enables the oscillation circuit 67. As a result, the oscillation circuit 67 resumes oscillation.

In addition, by resetting the above-mentioned FFIEli path 63,
"1" is supplied to the data input end of the F circuit 81. As a result, the output of the NAND circuit 80 causes F
F circuits 81 and 83 are set and the gate of NAND circuit 86 is opened. Therefore, the clock from the inverter circuit 85 is output to the CPU 28 via the NAND circuit 86.

At this time, the oscillation circuit 67 normally oscillates for 50 seconds until it stably oscillates.
0~600m5ec is required.

As a result, the CPO 28 outputs "0" as the clock selection signal to the data input end of the FF circuit 76 500 to 600 m5ec after outputting the key human interrupt signal.
t- feed. As a result, the FF circuits 76 and 77 are reset, and the reset output of the FF circuit 77, that is, the "1" signal is supplied to the data input end of the FF circuit 74.

Also, at this time, the clock (I M
HZ) is supplied to the clock input terminal of the FF circuit 74 via the inverter circuit 72.

Therefore, the FF circuit 74 is set, and the set output opens the gate of the NAND circuit 75.

As a result, the clock (LM HZ
) is an inverter circuit 72.73, a NAND circuit 75.8
0, is outputted to the CPU 28 via an inverter circuit 85 and a NAND circuit 86 in sequence.

Thereby, by setting the clock selection signal to "0", synchronization is achieved in the FF circuit 74, and the clock is switched from the clock for high-speed processing to the clock for high-speed processing.

Next, a case will be described in which the process is terminated and the system is placed in a stopped state (standby state). That is, by setting the clock selection signal to 1", the FF circuits 76 and 77 are set, the set output of the FF circuit 77, that is, the "1" signal is supplied to the NAND circuit 79, and the gate of the NAND circuit 79 is opened. .Therefore, the clock for the watch consists of the inverter circuit 78, the NAND circuit 79.80, and the inverter circuit 8.
5, and is output to the CPU 28 via the NAND circuit 86.

As a result, the watch clock is output to the CPU 28 again.

Next, a stop signal is supplied from the CPU 28 to the data input end of the FF circuit 62. Then, the FF circuit 62 is set, and the set output is supplied to the data input end of the FF circuit 63. Then, the FF circuit 63 is set by the machine cycle signal M1 from the CPU 28, and a "0" signal is supplied to the data input a2D of the FF circuit 81.

As a result, the set output of the FF circuit 63 is transferred to the FF circuit 81.
．． After sending two pulses at step 83, the gate of the NAND circuit 86 is closed to stop outputting the clock to the CPU 28. As a result, the CPU 28 is brought to a halted state.

Further, the set output of the FF circuit 63 is the FF circuit 64.
After sending two pulses at step 65, the gate of the NAND circuit 66 is closed to stop the oscillation by the oscillation circuit 67.

As a result, after stopping the output of the clock to the CPU 28, the oscillation circuit 67 is stopped.

In this way, the clock control circuit 26 operates as an oscillator 27.
In order to cover the rising edge of crystal oscillation caused by this, the watch clock and IMHz clock are effectively switched.

The calendar circuit 33 will be explained in detail using FIG. 8. That is, a frequency divider circuit 91 outputs signals every second from output terminals a and b by dividing the oscillation output of the 32.768K HZ oscillator 34, and a signal from output terminal a of this frequency divider circuit 91. By counting 1
A counter 92 outputs a signal every 0 seconds, and by counting the signals from this counter 92, 60 seconds or 1
A counter 93 that outputs a signal every minute, this counter 9
A counter 94 that outputs a signal every 10 minutes by counting the signal from 3, a counter 95 that outputs a signal every 60 minutes, that is, every hour, by counting the signal from this counter 94, and a counter 20. A counter 96 outputs a signal every 24 hours, that is, every 10, by counting the signal from the frequency dividing circuit 95, and a counter outputs a signal every 10 seconds by counting the signal from the output terminal of the frequency dividing circuit 91. 97, a counter 98 that outputs a signal every 60 seconds, that is, every minute, by counting the signal from this counter 97; a counter 99, which outputs a signal every 10 minutes by counting the signal from this counter 98; , a counter 100 that outputs a signal every 60 minutes, that is, every hour, by counting the signal from this counter 99, and a counter that outputs a signal every 24 hours, that is, every 10, by counting the signal from this counter 100. It is composed of 101.

The counters 92 to 96 constitute a transaction clock that counts seconds, minutes, and hours, and the counters 97 to 96 constitute a clock for counting seconds, minutes, and hours.
101 constitutes a display clock that counts seconds, minutes, and hours. ] The contents of the counters 97 to 101, that is, the counted values, can be changed using the keyboard section 12, and the contents of the counters 92 to 96, that is, the counted values cannot be changed using the keyboard section 12. There is.

In addition, the year, month, day, and day of the week are displayed on the counter 9 every 24 hours.
6. An interrupt request is output to the CPU 28 by the signal from 101. Thereby, the CPU 28 uses the data memory 31 to update the year/month/day and day of the week of the corresponding area. Furthermore, as shown in FIG. 9, the two clocks have a one-second reference clock phase shifted from each other, so that interrupts do not occur at the same time.

The magnetism generating member control circuit 40 will be explained in detail using FIG. 10. That is, command data supplied from the CPU 28 via the data bus 20 is supplied to the command FF circuit 110. This FF circuit 1
10 consists of four OFF circuits, and depending on the command data supplied from the data bus 20, a clock selection signal corresponding to the drive rate for the first track is output from the output terminal 110a, a start signal is output from the output terminal 110b, or a start signal is output from the output terminal 110C. A clock selection signal corresponding to the drive rate for the second track is output from the output terminal 110d, and a start signal is output from the output terminal 110d.

5 at the clock input terminal cp of the FF circuit 110,]
: The command write start signal from the CPU 28 is being supplied. -1- The clock selection signal corresponding to the drive rate indicates whether the type of reader is manual reading or automatic conveyance reading.

-1- The clock selection signal output from the output terminal 110a of the FF circuit 110 is supplied to the input terminal S of the selection circuit 111. An input terminal A of this selection circuit 111 is supplied with a signal having a frequency of 8KHZ from an oscillator (not shown), and an input terminal B is supplied with a signal having a frequency of 4KH2 from an oscillator (not shown).

In response to the clock selection signal from the FF circuit 110, the selection circuit 111 selects the signal at the input terminal A when the type of reader is manual reading, and outputs it from the output terminal Y.
If the type of reader is an automatic conveyance type reader, the signal at the input end B is selected and output from the output end Y.

The start signal output from the output end 110b of the FF circuit 110 and the output of the selection circuit 111 are supplied to a timing circuit 112.

This timing circuit 112 generates a hexadecimal clock,
Clock input terminal C of parallel/serial conversion circuit 115
The first clock is supplied to the load input terminal of the parallel/serial conversion circuit 115 as a load signal. Further, the timing circuit 112 has a data ladder 0"
Select circuit 11 for selecting clock for data “1” and clock for data “1”
6.

In addition, first track data as magnetic data supplied from the -2 CPU 28 via the data bus 20 (varies depending on the type of card selected) is supplied to the data latch circuit 113.
3 is supplied with a data write start signal from the CPU 28.

The data latch circuit 113 operates on the data bus 2 when a data write start signal is supplied from the CPU 28.
It latches magnetic data of 7 bits supplied from 0 onwards.

The data latched in the data latch circuit 113 is 7
It is supplied to the data input terminal IN of the parallel/serial conversion circuit 115 for bits. The parallel/serial conversion circuit 115 loads the data from the data latch circuit 113 in response to the supplied load signal, shifts the loaded data in order, and converts the data into 1-bit signals (
The signal is converted into a "1" signal or a "0" signal and output.

The output of the parallel/serial conversion circuit 115 is supplied to the input terminal S of the selection circuit 116. This selection circuit 11
6 selects and outputs the clock for data "1" supplied from the timing circuit 112 when a "1" signal is supplied to the input terminal S, and a "0" signal is supplied to the input terminal S. In this case, the clock for data "0" supplied from the timing circuit 112 is selected and output. The output of the selection circuit 116 is J-KFF circuit 1
The set output and reset output of this J-KFF circuit 117 are supplied to a driver 118.

This driver 118 generates a magnetic field by driving the magnetism generating member 14a in accordance with the signal from the FFn1D path 117. For example, the above FF
When the circuit 117 is set, it generates a magnetic field as shown by arrow C, and when it is reset, it generates a magnetic field as shown by arrow d.

Incidentally, a timing chart of the main parts of the magnetism generating member control circuit 40 is as shown in FIG.

In the selection circuit 116, as shown in FIG.
The clock cycle ratio for data "1" and "0" is 1:2. J-K with this clock
By operating the FF circuit 117 in the inversion mode, "1" and "0" signals in the format required as magnetic data (data for the first track) are obtained, and the magnetic generation member 1
4a.

Further, the data write start signal from the CPU 28 is inverted and supplied to the set input terminal of the empty detection FF circuit 114, and the reset input terminal of this FF circuit 114 receives the first clock from the timing circuit 112. When the data of the data latch circuit 113 is inverted (supplied) and loaded into the data latch circuit 115, the FF circuit 114 sets the
The set output of the F circuit 114, ie, the buffer empty signal, is supplied to the upper CPU 28.

As a result, the CPU 28 determines that the next data can be set, and transfers the next data to the data latch circuit 1.
Output to 13. In this way, the CPU 28
Data is set in order while sensing the output of the F circuit 114, and after all data is output, the command write start signal and data write start signal are turned off. As a result, the timing circuit 112
The signal generation stops and the operation ends.

Note that each of the circuits 111 to 118 described above is a circuit for the first track, and the circuit for the second track also includes a selection circuit 119, a timing circuit 120, and a data latch circuit 1.
21, empty detection FF circuit 122, parallel/serial conversion circuit 123, selection circuit 124, J-KFF circuit 125
, and a driver 126. However, the location where the timing circuit 120 operates in quinary is different.

As described above, the magnetism generating member control circuit 40 generates a magnetic field in accordance with the magnetic data of a predetermined credit card or cash card selectively read out from the data memory 31, thereby generating a magnetic field on the reading device side. A head (not shown) is provided with the same signals as when reading a conventional magnetic stripe. For example, the magnetism generating member 1 corresponds to the first track of the card.
4a outputs data for the first track, and the magnetism generating member 14b outputs second track data corresponding to the second track.

Next, the operation in such a configuration will be explained.

First, we will explain the offline function used by the card alone. That is, when the calculator mode is designated using the mode key 12a, that is, the M1 key, the calculator can be used as a calculator using the numeric keypad 12b and the four arithmetic operation keys 12c.

Also, by pressing the mode key 128, that is, the M2 key,
When the time display mode is specified, the CPU 28 reads the seconds, minutes, and hours for the display clock from the counters 97 to 101 in the calendar circuit 33, and also reads the seconds, minutes, and hours from the counters 97 to 101 in the calendar circuit 33, and
The year/month/day and day of the week for the display clock are read from , converted into a specified format, and output to the display control circuit 35. As a result, the display unit control circuit 35 uses an internal character generator (not shown) to convert the character pattern into a character pattern, and uses the display unit driver 36 to convert the display unit 1 into a character pattern.
Display in 3.

Furthermore, when the electronic width mode is specified using the mode key 12a, that is, the M3 key, the CPU 28 uses the data memory 31
The address, name, telephone number, etc. stored in the computer are read out and displayed on the display section 13. Further, when registering the above-mentioned address, name, etc. in the electronic width, for example, the mode key 12a and the numeric keypad 12b are used. That is, rAJ is rMl,2'', rBJ is rM2.2'', rcJ is rM3
．． 2'', rDJ is rMl, 3'', etc. can be specified.

Further, the shopping mode will be explained with reference to the flowchart shown in FIG. For example, mode key 12a
If you specify the shopping mode using the M4 key, then select the type of contract credit card or cash card using the numeric keypad 12b, select the type of output terminal, that is, whether it is a reader, manual type, or automatic conveyance type, and Select whether to output the data for the first track or the data for the second track.

For example, the number keys displayed on the display section 13 and the abbreviations such as credit company names, bank names, etc.
Use b to select the type of contract credit card or cash card. In addition, in response to the message "Is the reader reading manual?" displayed on the display unit 13, if it is manual reading, press the YES key (equal key 12h).
Select it by inputting the
By pressing the T key (addition key 12C), in response to the guidance displayed on the display unit 13, ``Is the reading automatic conveyance type?'', by pressing the YES key (equal key 12h), select it. Furthermore, by manually specifying the first track using the "1" key in the numeric keypad 12b and the division key 12e, and by specifying the second track by inputting the "2" key in the numeric keypad 12b and the division key 12e, 1st
Select whether to output track data or second track data.

” 1), the CPU 28 reads the first track data and the second track data from the data memory 31 as data (72 characters) corresponding to the selected credit card or cash card.
It is output to the magnetism generating member control circuit 40. Also, CPU2
8 outputs a drive rate corresponding to the selection of manual type or automatic conveyance type to the magnetism generating member control circuit 40. Further, the CPU 28 outputs command data, a command write start signal, and a data write start signal to the magnetism generating member control circuit 40.

Next, when the start key (multiplication key 12f) is turned on, the CPU 28 outputs a start signal to the magnetism generating member control circuit 40. As a result, when the output of the data for the first track is selected, the magnetism generating member control circuit 40 causes the magnetic field generating member 148 to generate a magnetic field corresponding to the data for the first track of the credit. A side magnetic head (not shown) is supplied with the same signal as when reading the conventional magnetic stripe of the first track. Moreover, the magnetism generating member control circuit 40
When the output of data for the second track is selected, a magnetic field corresponding to the data for the second track of the credit is generated from the magnetism generating member 14b, so that the magnetic head (not shown) on the reader side is The same signal is provided when reading the magnetic stripe of the second track of .

As a result, in shopping mode, it can be used as a conventional credit card.

The designation of the track is maintained until the end key (decimal point key 12g) instructing the end of the transaction in the mode is pressed or the other track is designated.

In addition, the output of the above magnetic data usually ends once, or if the start key (multiplication key 12f) continues to be pressed, the data is output continuously, that is, the data for each track is repeatedly output. do.

In this case, there is no change to the specified track.

Next, the online function used by inserting the IC card 10 into the terminal 16 will be explained. That is,
Insert the IC card 10 into the insertion slot 17 of the terminal 16.

Then, the IC card 1o is accepted, and the connection part inside the terminal 16 and the contact part 11 of the IC card 10 are connected. As a result, when an external power supply voltage is supplied via the contact portion 11, the power supply control circuit 23 switches from being driven by the internal battery 25 to being driven by an external power supply voltage. In addition, the reset control circuit 2
2 generates a reset signal and starts the CPU 28. After this activation, if the CPU 28 confirms that it is operating online, it performs online processing based on the contents of the program ROM 29. This online processing involves exchanging data by updating data between the terminal 16 and the IC cart 10, and
New data is written into the cart 10.

As mentioned above, while the start key is pressed, data for each track is repeatedly output, so
The magnetic head and the magnetism generating member are precisely aligned, that is, when the magnetism generating member passes the magnetic head, the magnetic data can be reliably read by the magnetic head. Therefore, the operation is simple, that is, the operability is good, and the operation can be performed accurately in a short time. This is particularly effective when the reader is a manual type.

In the above embodiment, the magnetic data is repeatedly output by continuing to press the start key, but the invention is not limited to this, and the display unit may be used to select whether to repeat or once,
It may also be specified using a separate key for continuous output.

In addition, although an IC card is used, it is not limited to this, as long as it has a data memory and a control element, and selectively inputs and outputs from the outside. It may be a shape.

[Effects of the Invention] As described in detail above, according to the present invention, it is possible to create a portable medium that does not require detailed alignment between the reading position of the reader and the magnetic generation element, and that can improve operability. Can be provided.

[Brief explanation of the drawing]

The drawings are for explaining one embodiment of the present invention, and FIG. 1 is a flowchart for explaining the operation in the shopping mode, FIG. 2 is a diagram showing the schematic configuration of the electric circuit of the IC card, and FIG. 4 is a plan view showing the configuration of an IC card.
Figure 5 shows a terminal that handles IC cards, Figure 5 shows an example of the configuration of a power supply control circuit, Figure 6 is a timing chart for explaining the operation of the main parts in Figure 5, and Figure 7 shows A diagram showing the configuration of the clock control circuit, FIG. 8 is a schematic configuration block diagram of the calendar circuit, FIG. 9 is a diagram showing the output timing of the signal from the frequency dividing circuit, and FIG. 10 is a configuration example of the magnetic generation member control circuit. 11 and 12 are timing charts for explaining the operation of the main parts in FIG. 10. 10... IC card (portable medium), 11... Contact section, 12... Keyboard section, 12a... Mode key, 12b... Numeric keypad, 12C... Addition key (NEXT key), 12d --- Subtraction key, 12 e,
,. Division key, 12f... Multiplication key (start key), 12
g... Decimal point key (No key, end key), 12h.
...Equal key (YES key), 13...Display section,
14a, 14b... Magnetism generating member, 16... Terminal, 23... Power supply control circuit, 25... Internal battery,
28... CPU (control element), 31... data memory (storage means), 40... magnetism generating member control circuit (
drive means). Applicant's agent Patent attorney Takehiko Suzue Figure 3 Figure 4

Claims (3)

[Claims] (1) In a portable medium having an input means and a control element for controlling each part including the input means, a storage means for storing information specifying transaction details, a magnetism generating member for generating magnetic data, and the magnetism. an instruction means for instructing the generation member to generate magnetic data; and a driving means for driving the magnetism generation member according to the memory content stored in the storage means while the instruction means is giving an instruction; A portable medium comprising: (2) While the instruction means is giving an instruction, the magnetism generating member repeatedly generates magnetic data corresponding to the stored content of the storage means, as set forth in claim 1. portable media. (3) The portable medium according to claim 1, wherein the instruction means is performed by the input means.