JPS6323413A - Decision circuit - Google Patents

Abstract

PURPOSE:To eliminate a DC offset accurately by providing a switch circuit giving an output signal of a sample means to one of two output terminals in response to a control signal and using an intermediate value of the output of a voltage memory circuit connected respectively to the two output terminals as a reference signal. CONSTITUTION:A switch circuit 5 inputted a part of a sample and hold signal switches and outputs an input signal to two output terminals in response to a control signal CONT being an output of a binarization circuit 8. Then the two outputs are inputted to a voltage memory circuit comprising capacitors 6a, 6b and resistors 7a, 7b and a voltage R being a connecting point between the resistors 7a and 7b is an intermediate value of the voltage stored in the capacitors 6a, 6b and an optimum reference voltage is obtained. Then the binarization circuit 8 outputs a binary logic signal representing whether the sampled voltage by the sampled-and-hold circuit 3 is higher or lower than the reference voltage R. The binary logic signal is outputted from an output terminal 9 as a decision signal and inputted to the switch circuit 5 as a control signal CONT.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a digital signal determination circuit including a DC offset control circuit, and in particular, it provides effects by removing DC offset included in an input digital signal. The present invention relates to a judgment circuit that makes a certain judgment.

[Conventional technology]

When receiving a digital signal, it is necessary to determine which of the digital logic values the received signal is closest to. At this time, if the received digital signal contains a DC offset, the probability of making an error in determination increases. Therefore, removing the DC offset is an important issue in order to prevent the reception error rate characteristics from deteriorating.

The circuit that controls this DC offset is
Conventionally, circuits having low-frequency cutoff characteristics and circuits that detect maximum and minimum peak values and calculate their average value are known.

[The interlayer point that the invention attempts to solve]

Among the above-mentioned conventional DC offset control circuits, among these circuits, those with low-frequency cutoff characteristics are effective for signals that do not contain DC components, such as analog audio signals; When applied to a normal digital signal containing a DC signal, there is a problem that code amount interference occurs due to the loss of a DC signal component, and reception error rate characteristics deteriorate.

In addition, the latter circuit that detects the maximum and minimum peak values and calculates their average value has difficulty finding an accurate average value because the peak value changes depending on the digital signal sequence. However, there was a problem in that it was difficult to accurately remove the DC offset.

[Means for solving problems]

The judgment circuit of the present invention is a judgment circuit that takes a digital signal as input and makes a judgment by removing a DC offset included in the input digital signal, and includes sampling means for sampling the input digital signal at a predetermined sampling timing. , a switch circuit that receives the output signal of this sample means as input and selects and outputs one of two output terminals according to a control signal, and a first and second output terminal that are respectively connected to the two output terminals of this switch circuit. 2 voltage memory circuits, and the output signal of the sample means 2, using the intermediate value of the outputs of the first and second voltage memory circuits as a reference signal.
Determine and output as one of the logical signals of the value 2
The device comprises a digitizing circuit and means for inputting an output signal of the binarizing circuit as a control signal to the switch circuit.

[For production]

In the present invention, since the digital signal at the sample time takes a constant voltage without changing depending on the code sequence, the DC offset can be effectively controlled without depending on the digital signal sequence, and the DC offset contained in the input digital signal Remove offset.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In the figure, 1 is an input terminal to which a digital signal is applied, 2 is a clock regeneration circuit that receives the input digital signal from input terminal 1 and generates a sample timing signal in synchronization with the digital signal, and 3 is an input terminal 1. The sample and hold circuit 3 samples and holds the input digital signal from the clock regeneration circuit 2 using the sample timing signal obtained from the clock regeneration circuit 2, and the sample and hold circuit 3 constitutes means for sampling the input digital signal t at a predetermined sample timing. are doing. Reference numeral 4 denotes a reference signal generating circuit, and this reference signal generating circuit 4 receives the output signal of the sampling means as input, and a switch circuit 5 selects and outputs one of the two output terminals according to the control signal CON'r. , capacitors 6a, 6b and resistors 7a, γ
b, and two voltage memory circuits respectively connected to the two output terminals of the switch circuit 5. Reference numeral 8 denotes a binarization circuit that uses the intermediate value of the outputs of these two voltage memory circuits as a reference signal to determine and output the output signal of the sample means as one of the binary logic signals, and 9 indicates this binarization circuit. This is an output terminal from which the output of the circuit 8 is obtained. The output of this binarization circuit is inputted as the control signal C0NT of the switch circuit 5.

In preparation for explaining the operation of the embodiment shown in FIG. 1, FIG. 2 shows a schematic representation of the waveform of a digital signal. When there is no noise, sample time nT (n: positive integer, T: digital signal rate a)
If there is noise, the received signal is determined to be a binary logic signal depending on which of these values it is closer to. This determination is made based on whether the sampled signal voltage is higher or lower than the reference voltage C.

In an ideal case where there is no DC offset in the input digital signal, the probability of erroneous determination is low. On the other hand, for example, as shown in FIG. 2, the DC offset Δ
If V is present, the determination is made based on the reference voltage d, so the probability of an erroneous determination increases.

Next, the operation of the embodiment shown in FIG. 1 will be explained with reference to FIG. 2.

First, a digital signal containing a DC offset is input from an input terminal 1 to a clock recovery circuit 2 and a sample-and-hold circuit 2. This clock regeneration circuit 2 is
It receives an input digital signal and generates a sample timing signal in synchronization with the digital signal.
Since this is a generally well-known technique, detailed explanation will be omitted here. Further, the sample and hold circuit 3 uses the sample timing signal obtained from the clock recovery circuit 2 to sample and hold the input digital signal.

Next, a part of the sampled and held signal is input to the switch circuit 5, and this switch circuit 5 is connected to the binarization circuit 8.
The input signal is switched between two output terminals according to the control signal C0NT which is the output of the output terminal. The two outputs of this switch circuit 5 are capacitors 6a and 6, respectively.
Ki
4 input voltages are stored. Here, since the constants of these capacitors 6a, 6b and resistors 7a, 7b are set equal, the voltage R at the point where resistor 7a and resistor arb are connected is an intermediate voltage between the voltages stored in capacitors 6a and 6b. value. Since this voltage R takes an intermediate value between voltage values a and b (see FIG. 2), it becomes an optimal reference voltage (hereinafter, this voltage R will be referred to as reference voltage R).

Then, the binarization circuit 8 outputs a -r binary logic signal indicating whether the voltage value sampled by the sample hold circuit 3 is higher or lower than the reference voltage R. This binary logic signal is output from the output terminal 9 as a determination signal and at the same time is input to the switch circuit 5 as a control signal C0NT. In this way, the switch circuit 5 selects and selectively outputs the output terminal of the switch circuit depending on whether the voltage of the sampled signal is higher or lower than the reference voltage R. Therefore, the voltage values a and s shown in FIG. 2 are stored in the capacitors 6a and 6b.

In this way, the reference voltage R changes according to the DC offset voltage, so excluding the influence of the DC offset voltage,
Optimal judgment can be made.

〔Effect of the invention〕

As explained above, according to the present invention, the digital signal at the sample time takes a constant voltage (a, b) without changing depending on the code sequence, so the DC offset can be adjusted independently of the digital signal sequence. control effectively,
This has the effect of making it possible to perform optimal signal determination.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a schematic waveform diagram of a digital signal used to explain the operation of FIG. 1. 3... Sample hold circuit, 51-... Switch circuit, 6a, 6b... Capacitor, 7a, 7b...
・Conflict/Resistance, 8・Φ...Binarization circuit.

Claims (1)

[Claims] A determination circuit that receives a digital signal and makes a determination by removing a DC offset contained in the input digital signal, the circuit comprising: sampling means for sampling the input digital signal at a predetermined sampling timing; and an output signal of the sampling means. a switch circuit that receives as input and selects and outputs one of two output terminals according to a control signal, and first and second voltage memory circuits respectively connected to the two output terminals of this switch circuit; a binarization circuit that determines and outputs the output signal of the sampling means as one of binary logic signals using an intermediate value of the outputs of the first and second voltage memory circuits as a reference signal; and means for inputting an output signal of the switching circuit as a control signal of the switching circuit.