JPS63211991A - Digital convergence circuit - Google Patents

Abstract

PURPOSE:To maintain the vertical symmetry of a correction data by reading out the correction data by means of designating an address by a clock, obtained from a horizontal periodic signal, for a correction data storage circuit, and on the other hand, switching a read start address, for the change of the number of scanning lines, and obtaining always the same correction data at the center of a picture frame. CONSTITUTION:The correction data is read out from the correction data storage circuit 12, by designating the address according to the clock, obtained by frequency- multiplying the horizontal periodic signal by an address generation circuit 13. A phase locked loop circuit 21, which generates an address forming frequency-multiply signal, phase-locked to the horizontal periodic signal, and a timing generation circuit 22, which generates a load pulse to determine the read timing according to the vertical periodic signal and the horizontal periodic signal, are previously connected to the address generation circuit 13 in addition to an input.output circuit 15. The input.output circuit 15 loads the read start address, set by a central processing unit 14, to the address generation circuit 13 at the point of time when the load pulse is supplied to the address generation circuit 13. The central processing unit 14 switches and sets the read start address in accordance with the number of the scanning lines.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital convergence circuit that can defocus a scanning line that scans a screen.

[Prior Art] A projection television receiver that combines images projected from three monochrome projection tubes corresponding to three primary colors on a screen is
Compared to a direct-view television receiver, which looks directly at the screen on the picture tube, it is more susceptible to the effects of the earth's magnetic field, and misfocusing of the scanning line that occurs when changing the direction or adjusting the posture of the projection tube.
It is necessary to correct it by convergence adjustment. Digital convergence circuit not shown in Figure 3! is RGB
This is applied to a projection type television receiver 4 that projects an image from each of the monochrome projection tubes 2r, 2g, and 2b onto a screen 3 in front of it, and each of the projection tubes 2r, 2g.

Horizontal and vertical convergence coils installed every 2b (
(not shown) is built into the defocus correction circuit 5. A memory circuit 6 is connected to the focus shift correction circuit 5 and stores correction data necessary for focus shift correction, which is collected in advance for each sample point divided into a matrix on the screen 3. The correction data read from
It is configured to be supplied to the defocus correction circuit 5.

[Problems to be Solved by the Invention] When the above-mentioned conventional digital convergence circuit l successively generates correction data necessary for correcting defocusing, it uses a clock obtained by doubling the frequency of a horizontal synchronizing signal in synchronization with this. Accordingly, the read control circuit 7 generates an address signal, and the correction data stored at the address specified by this address signal is read out from the storage circuit 6.
Like a multi-scan projector, 15-41k
In a projector in which the deflection mode is automatically switched in accordance with the horizontal deflection frequency of Hz, for example, when the scanning line density is switched from high density to low density, the readout control circuit 7 is configured as before. If the correction data is read out according to the specified address, correction data will be left unread at the end of the screen scan, and the correction data that originally had vertical symmetry with respect to the center of the screen may have a center of symmetry other than the center of the screen. However, there are problems in that convergence correction itself may have the opposite effect.

[Means for Solving the Problems] This invention solves the above problems, and correction data for correcting the focusing deviation of the scanning line that scans the screen is stored at an address corresponding to the screen. a correction data storage circuit, an address generation circuit for specifying an address of the correction data to be read from the correction data storage circuit according to a clock obtained by multiplying the frequency of the horizontal synchronization signal i) in synchronization with this; A readout device that is connected to the generation circuit and maintains the vertical symmetry of the correction data by switching the readout start address according to the number of scanning lines so that the same correction data is always obtained at the center of the screen regardless of the number of scanning lines. The present invention is characterized in that it is configured by providing an address control means.

[Function] The present invention synchronously doubles the frequency of a horizontal synchronizing signal to a correction data storage circuit in which correction data for correcting the focusing deviation of a scanning line that scans a screen is stored at an address corresponding to the screen. The correction data is read out by specifying the address according to the clock obtained from the screen, and when the number of scanning lines changes, the readout address control means switches the readout start address so that the same correction data is always obtained at the center of the screen. , maintaining the vertical symmetry of the correction data.

[Example] Hereinafter, an example of the present invention will be described with reference to FIG. 1.2. FIG. 1 is a circuit configuration diagram showing an embodiment of a digital convergence circuit of the present invention, and FIG. 2 is a diagram for explaining the control operation by the read address control means shown in FIG. 1.

In FIG. 1, the digital convergence circuit 11 includes a correction data storage circuit 12 in which correction data for correcting convergence deviation on the screen is stored at an address corresponding to the screen.
And this correction data storage circuit! The correction data to be read from 2 is connected to the address generation circuit 13 of the clock obtained by multiplying the frequency of the horizontal synchronizing signal in synchronization with the horizontal synchronizing signal.
In order to always obtain the same correction data at the center of the screen regardless of the number of scanning lines, a readout address control means is provided that switches the readout start address according to the number of scanning lines and maintains the vertical symmetry of the correction data. It is composed of

The read address control means includes a central processing unit 14 located at the center of the digital convergence circuit 11, and a controller provided between the central processing unit 14 and the address generation circuit.
It consists of an output circuit 15. In addition to the correction data storage circuit 12, the central processing unit 14 is connected to a coefficient storage circuit 6 for storing each coefficient of the basic correction wave obtained during convergence adjustment, and a ROM 17 for storing software. .

In this embodiment, correction data determined based on the coefficients stored in the coefficient storage circuit 16 is written into the correction data storage circuit 12. The correction data read out from the correction data storage circuit 12 is latched by the latch circuit 18, and is provided to the DA converter 19, and then sent to the low frequency frequency circuit 2 for removing distortion.
0 to the defocus correction circuit 5.

Here, the address generation circuit 13 includes a human output circuit! 5
In addition, a phase-locked loop circuit 2 that generates a frequency-doubled signal for address formation that is phase-locked to the horizontal synchronization signal;
A timing generation circuit 22 is connected to generate a load pulse that determines read timing according to a vertical synchronization signal and a horizontal synchronization signal. The input/output circuit 15, at the time when the load pulse is supplied to the address generation circuit 13,
The read start address set by the central processing unit 14 is loaded. This readout start address is determined by the central processing unit 14, which always feeds back the output of the address generation circuit I3 to the input/output circuit I5 so that the same correction data is always obtained at the center of the screen regardless of the number of scanning lines. The vertical symmetry of the correction data is maintained by the central processing unit 14 switching the readout start address in accordance with the number of scanning lines.

Here, the reason why we insist on vertical symmetry of the correction data is not only because the correction data has symmetry at the top and bottom of the screen unless there are special circumstances, but also because of the basics used when combining the correction data. This is because the correction wave employs, for example, a parabolic waveform wave with a vertical scanning period and its modulation wave, which is characterized by vertical symmetry. That is,
In this embodiment, the convergence correction amount Y at the distance X from the scanning start end of the I-line scanning line is determined by Y=ΣKj
fj(x) = +f + (x) *r t(x)・ ・+Knf
n(x), and successively change the coefficient Kj from the basic correction wave f+(x), which has the most influence on the correction of defocusing, while visually observing the defocusing on the screen and improving the adjustment range. This basic correction wave includes the above-mentioned parabolic waveform wave of the vertical scanning period and its modulation wave. In the convergence adjustment, the central processing unit 14 calculates correction data at each point of the screen divided into a matrix for the temporarily set coefficient Kj, and stores this in the correction data storage circuit 12. Then, the correction data storage circuit 12 reads out the stored correction data in synchronization with horizontal deflection scanning, and sequentially supplies it to the defocus correction circuit 5. The coefficients =Kn are all stored in the coefficient storage circuit 12 upon completion of the adjustment.

When the convergence adjustment is completed in this way, from the next time onwards, a predetermined defocus correction will be performed for each scanning point on the screen using the correction data read out from the correction data storage circuit 12. Now, if the scanning line density were changed from high density to low density, if the address was specified from address 0 according to the frequency division signal of the horizontal synchronization signal as before, it would be corrected at the end of screen scanning. This will result in data being left unread. Taking as an example the correction data defined by a parabolic waveform with a vertical scanning period, as shown by the dotted line in Figure 2,
The correction data at the center of the screen does not match the previous correction data, and the vertical symmetry of the correction data is lost. However, as already mentioned, the central processing unit was monitoring the output of the address generation circuit 13 for the number of scanning lines! 4 is the person/output circuit! As a result of 5, the correction data at the beginning of scanning that inhibits vertical symmetry is skipped, and as shown by the solid line in Figure 2,
Symmetrical convergence correction can be performed at the top F of the screen.

In this way, the above digital convergence circuit! (3) is a phase-locked loop circuit 2 that stores correction data for correcting the focusing deviation of the scanning line that scans the screen at an address corresponding to the screen.
The address generation circuit 13 specifies the readout address according to the clock generated by synchronously doubling the horizontal synchronization signal V1, while the number of scanning lines is changed by the central processing unit 14 and the human/output circuit I5. Since the read address control means switches the read start address and is configured so that the same correction data is always obtained at the center of the screen, the clock used for address specification by the address generation circuit 13 is
It is possible to use one with a fixed period that is phase-locked to the horizontal synchronization signal. Also, without changing the clock frequency, r
By simply changing the readout start address to 9j, the horizontal deflection frequency can be handled by simply changing the horizontal deflection frequency. It can be said that this system is particularly suitable for convergence correction in multi-scan television receivers and the like that automatically follow the .

Although the above embodiments have been explained using a projection type television receiver as an example, convergence correction can also be applied to other types of television receivers, such as direct-view type television receivers that directly view images projected on a picture tube. good.

[Effects of the Invention] As explained above, the present invention transmits a horizontal synchronizing signal to a correction data storage circuit in which correction data for correcting a focusing shift on a screen is stored at an address corresponding to the screen. The correction data is read out by specifying the address according to the clock obtained by synchronous frequency doubling, and when the number of scanning lines changes, the readout address control means switches the readout start address so that the same correction data is always displayed at the center of the screen. Therefore, the clock used for address specification by the address generation circuit can be a clock with a fixed period that is phase-locked to the horizontal synchronization signal, and the read start address can be simply changed without changing the clock frequency. It is possible to handle different horizontal deflection frequencies by simply adding a special delay circuit, etc., and it can be handled using only software processing. Therefore, multi-scan televisions that automatically follow two or more horizontal deflection frequencies can be used. It has excellent effects, such as being suitable for convergence correction in John's receivers and the like.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram showing an embodiment of the digital convergence circuit of the present invention, FIG. 2 is a diagram for explaining the control operation by the read address control means shown in FIG. 1, and FIG. , is a circuit configuration diagram showing an example of a conventional digital convergence circuit. 500. Focus shift correction circuit, 11. ,,Digital convergence circuit,12. , , correction data storage circuit, ta
, , address generation circuit, 14. . , central processing unit, 15. ,,input/output circuit, 21°99
Phase-locked loop circuit, 22. ,,timing generation circuit.

Claims (1)

[Claims] Correction data for correcting the focusing deviation of the scanning line that scans the screen is stored in a correction data storage circuit at an address corresponding to the screen, and the correction data to be read from this correction data storage circuit is stored in a horizontal synchronizing signal. An address generation circuit that specifies addresses according to the clock obtained by multiplying the frequency of A digital convergence circuit is provided with a read address control means for switching a read start address according to the number of scanning lines and maintaining vertical symmetry of correction data.