JPS63209334A - Quantizer - Google Patents

Abstract

PURPOSE:To decrease the bit number of an output without deteriorating the S/N by applying subsequent connection to delta sigma quantizer of multiple integration (more than double integration) as unit stage. CONSTITUTION:A double integration delta sigma quantizer 61 uses the 1st integration device 25 so as to integrate an input signal 13 and uses the 2nd integration device 26 for further integration. It is discriminated by a comparator 35, and the binary signal output is fed back negative to the input of the integration devices 25, 26 to provide the double integration noise suppression characteristic. Thus, the triple integration noise suppression characteristic is provided together with the 1st and 2nd stage integrations. Then as to the output level number, the 1st stage output Y1 and the 2nd stage output Y2 take binary values of +1, -1. Moreover, the delay output Y2' of the Y1 takes tow-value of +1, -2, the differentiation output Y2' takes tristate values of +2, 0, -2, and its summing output Y4 takes 4-value of 3, 1, -1, -3. Thus, the output level number is halved.

Description

[Detailed description of the invention] [Technical field to which the invention pertains] The present invention relates to a multi-stage noise suppression quantizer, which is a type of oversampling quantizer that converts a digital signal with a long word length into a digital signal with a short word length sampled at high speed. The present invention relates to a quantizer, and particularly to a quantizer that can shorten the output word length (number of output levels) without deteriorating S/N characteristics.

[Conventional technology]

Conventional quantizers include, for example, the International Conference on Acoustic Speech and Signal Processing (International Conference on Acoustic Speech and Signal Processing).
Conference Acoustic 5pe
echand Signa], Processing
1986), pages 1545 to 1548 of the 1986 Proceedings of the International Society for Acoustic and Speech Signal Processing, or published patent application No. 1921.27 of 1986.

FIG. 5 is a block diagram of an example of a conventional quantizer described in the above-mentioned document, in which (A) shows a two-stage cascade connection and (B) a three-stage cascade connection.

This quantizer is a multi-stage cascade connection of single-integral type delta-sigma quantizers having a single-integral noise suppression characteristic. The higher the order, the higher the S/N characteristic of the quantizer.

In FIG. 5, 11 is the input of the first stage, ]2 is the output of the first stage, and 13 is the quantization noise output of the first stage, which is also the input of the second stage. 14 is a two-stage output. 15 is the quantization noise output of the second stage, and simultaneously serves as the input of the third stage. Also, 16
is the third stage output, and on 12.14.16, two values of +1 and -1 are output.

Also, 20.21.22 is an integrator, 30.31.32 is a comparator that judges the value of the integrator output and outputs +1 or -1, 40.4], 42 is a delay circuit that delays one timing, 50.51.52 is a differentiator.

Further, 70, 71, and 72 are negative feedback circuits, 80, 81 are difference signal circuits, and 90 are adder circuits.

Also, the output value of 12 is Yl, the output value of 14 is Y2.16
The output value of is Y3, and the outputs of the delay circuit and differentiator are Y,', Y,', Y2', Y2'',
Let Y1' and Y3'' be the addition output of Y1' and Y2', or the addition output of Y,', Y2#, and Y3#.
, and so on.

The above-mentioned single integral type delta sigma quantizer includes an integrator 20 that integrates a human input signal, and
Comparator 30 outputs a binary signal according to the output level of
and a negative feedback circuit 70 that feeds the output of the comparator 30 back to the integrator 20. In addition, in order to connect such single integral type delta sigma quantizers in series, the quantization noise of the first stage quantizer, that is, the difference between the output of the integrator 20 and the output of the comparator 30 must be reduced. The output of the delay circuit 40 which supplies the difference signal (output of the difference signal circuit 80) as an input to the second stage quantizer and delays the output of the first stage comparator 30 by one timing; The output of the differentiator 50 that differentiates the output of the comparator 31 is added to the adder 9.
The value added by 0 is used as an output signal.

As mentioned above, two or more single-integral delta-sigma quantizers are connected in series as a unit stage, and the quantization noise of the first stage is input to the second stage, and the quantizer of the second stage is By quantizing, differentiating the output, and adding it to the output of the first stage, it is possible to cancel the quantization noise of the first stage.

In this way, by sequentially inputting the quantization noise of the previous stage and canceling the quantization noise of the previous stage by adding the differential signal, it is possible to obtain the integral noise suppression characteristic for the number of stages connected in series. I can do it.

Next, the number of output levels in the above device will be explained.

First, in the case of FIG. 5(A), the values of Y2 and Y2 are 10],
-1, 2nd shift. Since Y1' only delays Yl, it has two values of +1 and -1.

However, since Y2' is the differential value of Y2, in the Z function, Y2
'=Y2-Y2·z-1, which is the difference between the current Y2 and the previous Y2. Therefore, there are four outputs as the value of Y2': +1+1, +1-1, -1+1, and -1-1, and the value of Y2' ultimately becomes three values, 2.0 and -2.

Furthermore, since Y4 is the addition of Y,' and Y2', its output takes four values: 3.1, -1, and -3. That is, the number of output levels is 4 (2 bits).

Note that this circuit has double integral noise suppression characteristics.

Next, in the case of FIG. 5(B), when the output power is determined in the same manner as in FIG. 5(A), Y3, Y2, and Y3 are binary values of +1 and -1. Also, 5Y1' is a two-timing delay of Y,
The output value remains the same as +1 and -1.

Also, since Y2' and Y3' are the differential values of Y2 and Y3, (
Similar to A), it takes three values: 2.0 and -2.

Since Y2' is this one timing delay, it is 2.0, -
It has three values of 2.

Also, Y3' is the differential of Y3', and therefore 4.
2. Takes five values: 01-2, -4.

Furthermore, Y4 is Y1' + Y2' + Y3
', and 7.5.3.1, -1, -3. -5,
Takes the 8 value of -7. That is, the number of output levels is 8 (4 bits).

Note that this circuit has triple integral noise suppression characteristics.

[Problem that the invention seeks to solve]

As mentioned above, in the prior art method of multi-stageing a single-integral delta-sigma quantizer with a 1-bit output (the number of output levels is two), a quantizer with a double-integral noise suppression characteristic has a 2-bit ( 4 values).

A quantizer with triple integral noise suppression characteristics uses 3 bits (8 values)
The output will appear. Therefore, a problem arises in the operating speed of subsequent circuits.

For example, FIG. 4(A) shows a pulse number modulation method D/
This is an output waveform diagram when an A converter (PNM circuit) 110 is added; in this case, the PNM circuit 110 must operate at a speed eight times faster than the digital output frequency of the quantizer 100.

Therefore, there is a problem in that a high-speed D/A converter and a high-frequency oscillator are required.

The present invention solves the problem of the prior art as described above, that is, high-speed operation is required when a pulse number modulation type or pulse width modulation type D/A converter is connected after the quantizer. Therefore, it is an object of the present invention to provide a quantizer that can reduce the number of output bits without deteriorating the S/N characteristic.

[Means to solve the problem]

In order to achieve the object described in item 1, in the present invention, a single integral delta sigma quantizer is used as a unit stage, and the quantization noise of the 8-stage quantizer in the previous stage is given as input to the quantizer in the next stage. , and the above unit stage is designed to cancel the quantization noise of the previous stage by setting the value obtained by adding the output obtained by differentiating the output of the next stage comparator to the output obtained by delaying the output of the previous stage comparator as an output signal. In a multi-stage integral noise suppression quantizer in which multiple integrators are connected in series, the output level of the last integrator is A multiple integral delta sigma quantizer (for example, a double integral delta sigma quantizer) comprising a comparator that outputs a corresponding signal, and a circuit that negatively feeds the output of the comparator to the input of the plurality of integrators. ) is configured to be provided at least one stage as a unit stage of the multi-stage integral noise suppression quantizer.

In other words, when achieving triple or more integral noise suppression characteristics, conventionally a multi-stage cascading connection of single integral delta sigma quantizers was used; however, in the present invention, multiple integral (double integral) The most important feature is that the delta-sigma quantizers (above) are connected in series as a unit stage.

By using the above configuration, the present invention reduces the number of output bits by 1 bit or more (reducing the number of output levels to 1/2 or less) with the integral noise suppression characteristic of the same order compared to the conventional technology. be able to.

〔Example〕

FIG. 1 is a block diagram of a first embodiment of the invention.

In Figure 1, 1] is the input, 12 is the first stage output, and 13
is the first stage quantization noise output and the second stage input, 14 is 2
It is stage output. Also, 20.25.26 is an integrator, 30
．． 35 is a comparator, 40 is a 1-timing delay circuit,
54 is a differentiator, 70.75 is a negative feedback circuit, 80 is a difference signal circuit, and 92 is an adder circuit. Also, Y□ is the first stage output, Y2 is the second stage output, Y,' is the delay output of Yl, Y
2' is Y2. The differential output, Y4, is the addition output of Y1' and Y2'.

Further, a portion 60 surrounded by a broken line indicates a single-integration type delta-sigma quantizer, and a portion 61 indicates a double-integration type delta-sigma quantizer.

In the above embodiment, the same single integral type delta sigma quantizer 60 as the conventional one is used as the first stage quantizer, but the double integral type delta sigma quantizer 60 is used in the second stage.
1 is used.

As shown in the figure, this double integral type delta sigma quantizer 61 integrates the input signal (previous stage quantization noise) 13 by the first integrator 25 and further integrates it by the second integrator 26. The comparator 35 determines this and outputs a binary signal, which is negatively fed back to the inputs of the first and second integrators, and has double integral noise suppression characteristics. Therefore, the circuit shown in FIG. 1 has triple integral noise suppression characteristics as a whole of the first stage and the second stage. Next, the number of output levels in the circuit of FIG. 1 will be explained.

In the circuit shown in FIG. 1, Yl and Y2 take binary values of +1 and -1. Moreover, Y1' is +1. -1 binary value, Y2' is +
It takes three values of 2.0 and -2, and its addition output Y4 takes 44 values of 3.1, -1 and -3.

As mentioned above, in the embodiment shown in FIG. 1, the number of output levels is 4 (2 bits) while having the triple integral noise suppression characteristic, and the conventional method has the same triple integral noise suppression characteristic. The number of output levels is 1/2 compared to FIG. 5(B).

Therefore, while the conventional triple integral noise suppression characteristic quantizer required a 3-bit resolution D/A converter, the present invention requires a 2-bit resolution D/A converter. It will be over.

FIG. 4(B) shows a pulse number modulation D/A converter (PN) in the triple integral noise suppression characteristic quantizer 101 of FIG.
This is an output waveform diagram when a PNM circuit (M circuit) 111 is added; in this case, the PNM circuit 111 only needs to operate at a speed four times the digital output frequency of the quantizer 101. Therefore, the operating speed can be increased to 172 Hz compared to when the conventional quantizer shown in FIG. 4(A) is used. For this reason, D
When the speed of the /A converter is the same, oversampling can be twice as much as that of the conventional method.
Quantization noise within a necessary band can be reduced, and a high S/N ratio can be achieved.

Note that the same applies even if a pulse width modulation type D/A converter is used.

Next, FIG. 2 is a block diagram of a second embodiment of the present invention.

In Figure 2, 11 is the input, 25.26 is the integrator, 3
5 is a comparator, 46.47 is a 1-timing delay circuit, 56.57 is a differentiator, 75.76 is a negative feedback circuit, 82
is the difference signal circuit, 93 is the adder circuit, Y□ is the first stage output, Y
2 is the second stage output, Y,' is the delay output of Yl, Y□'
is the delay output of Y,', Y2' is the differential output of Y2, Y
2' is the differential output of Y2', and Y4 is the addition output of Y, # and Y2#.

Further, portions 62 and 63 surrounded by broken lines both indicate a double integral type delta-sigma quantizer.

In the above embodiment, double integral delta-sigma quantizers are used as both the first-stage and second-stage quantizers. Therefore, the circuit of FIG. 2 has quadruple integral noise suppression characteristics.

In the circuit shown in Figure 2, Y, 2 between +1- and -1.
Y2# takes five values: 4.2.01-2, -4. Therefore, Y4 is +5, +3, +1, -1, -
3. It takes 6 values of -5.

As mentioned above, the circuit shown in FIG. 2 has quadruple integral noise suppression characteristics, and has higher performance than the conventional circuit shown in FIG. 5(B) with triple integral noise suppression characteristics. , the number of output levels is as small as 6 (3 bits), and furthermore,
The number of output levels is 172 or less compared to 16 (described in Table 1 below) of a conventional quadruple integral noise suppression characteristic quantizer having equivalent noise suppression characteristics.

Next, FIG. 3 is a block diagram of a third embodiment of the present invention.

In Figure 3, 11 is input, 23.24.25.26
is an integrator, 33.34.35 is a comparator, 43.44.4
5 is a one-timing delay circuit, 53.54.55 is a differentiator, 73.74.75.76 is a negative feedback circuit, 82.
83 is a difference signal circuit, and 9] is an adder circuit.

In this embodiment, the same single-integral delta-sigma quantizers as in the past are used as the first and second-stage quantizers, and a double-integral delta-sigma quantizer is used only in the third stage. ing.

Therefore, the circuit of this embodiment has quadruple integral noise suppression characteristics, and the number of output levels is eight.

Next, the number of output levels at various integral orders will be compared between the conventional method using only a single integral delta sigma quantizer and the present invention which combines at least one stage of double integral delta sigma quantizers. A comparison is shown in Table 1 below. Table 1 illustrates the relationship between the overall integration order, the integration order of each stage of quantizer, and the number of output levels when the comparator has 1 bit (outputs +1 and -1). .

As can be seen from Table 1 above, when the present invention is used, the number of output levels is smaller than the conventional one for the same integral order, especially when double integral type delta-sigma quantizers are used in all stages. The effect becomes noticeable.

In the embodiments described above, a double integral type delta sigma quantizer is used, but it is of course possible to use a triple or more multiple integral type delta sigma quantizer. [Effect] As explained above, in the present invention, the number of output values of the quantizer can be reduced to about 1/2 or less of that of the conventional method, and therefore, the D/
The resolution of the A converter can be lowered. Therefore, when mounting a D/A converter and a quantizer on an LSI etc.,
This has the effect that the circuit scale of the D/A converter can be reduced. Furthermore, if a pulse number modulation method or a pulse width modulation method D/A converter is used as a D/A converter, the operating speed can be reduced to 1/2 or less, and vice versa. In addition, if the D/A converter has the same operating speed, oversampling can be twice as much as that of the conventional method, so quantization noise within the required band can be reduced, resulting in a high S/N ratio. Excellent effects such as being able to achieve this can be obtained.

[Brief explanation of the drawing]

Figures 1 to 3 are examples of the present invention, respectively, and Figure 4 is a case where a pulse number modulation type D/A converter is connected to a triple integral noise suppression characteristic quantizer of the conventional method and the present invention. FIG. 5 is an example of a conventional device. <Explanation of symbols> 11...1st stage input

Claims (3)

[Claims] (1) Single integration type consisting of an integrator that integrates an input signal, a comparator that outputs a signal according to the output level of the integrator, and a circuit that negatively feeds the output of the comparator to the integrator. The unit stage is a delta-sigma quantizer, and the quantization noise of the quantizer in the previous stage, that is, the difference signal between the output of the integrator and the output of the comparator, is given as input to the quantizer in the next stage, and A plurality of the above unit stages are used to cancel out the quantization noise of the previous stage by making the output signal the value obtained by adding the output obtained by delaying the output of the previous stage comparator to the output obtained by differentiating the output of the next stage comparator. In a multi-stage integral noise suppression quantizer connected in series, a plurality of integrators connected in series sequentially integrate the output of the previous integrator, and a signal corresponding to the output level of the final integrator among the integrators. A multi-integral delta-sigma quantizer comprising a comparator that outputs , and a circuit that negatively feeds the output of the comparator to the input of the plurality of integrators, as a unit of the multi-stage integral noise suppression quantizer. A quantizer characterized in that at least one stage is provided. (2) Comparison of a first integrator that integrates an input signal, a second integrator that integrates the output of the first integrator, and outputs a signal according to the output level of the second integrator and a circuit for negative feedback of the output of the comparator to the inputs of the first and second integrators.
a delay circuit used in the first stage, connected in a subordinate manner to the single integral type delta sigma quantizer in the first stage, and delaying the output of the single integral type delta sigma quantizer by one timing; It is equipped with a differentiator that differentiates the output of the integral type delta-sigma quantizer, and an adder circuit that adds the output of the delay circuit and the output of the differentiator, and has triple integral noise suppression characteristics while achieving an output word length. 2. The quantizer according to claim 1, wherein the quantizer is 2 bits. (3) Comparison of a first integrator that integrates an input signal, a second integrator that integrates the output of the first integrator, and outputs a signal according to the output level of the second integrator and a circuit for negative feedback of the output of the comparator to the inputs of the first and second integrators.
Used in the second stage and second stage to connect them in a subordinate manner, and
A delay circuit that delays the output of the first stage double integral type delta sigma quantizer by two timings, a differentiator that differentiates the output of the second stage double integral type delta sigma quantizer twice, and the above delay circuit. Claim 1, characterized in that it comprises an adder circuit that adds the output of the circuit and the output of the differentiator, and has an output word length of 3 bits while having quadruple integral noise suppression characteristics. Quantizer.