JP2000232361A - D/a converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To fix an output pulse train at the time of inputting data with continues '0' at a mute pattern or a zero level without generating changeover noise at all in a simple structure. SOLUTION: This D/A converter is provided with a ΔΣmodulator 38 provided with a local feedback route 55 from a fourth stage integrator 63 to a third stage integrator 62 together with integrators 62-63 of fourth order. When detecting that input digital data are data for which zero data continue for a fixed period, the output of the ΔΣ modulator 38 is turned to a mute pattern and noise in an audible band is theoretically turned to zero by adding an extremely small DC component for removing the fractions of the integrators 60 and 61 of a first and second stages to the integrated values of the integrators 60 and 61 of the first and second stages.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a D / A for generating an analog signal from a digital signal such as a voice signal.
About converter.

[0002]

2. Description of the Related Art Conventionally, a D / A converter for converting a digital signal such as a voice signal into an analog signal has been known as an oversampling digital filter and a so-called ΔΣ.
By combining with a kind of bit compression technique by modulation, a 1-bit D / A converter having a small number of bits (about 1 to 4 bits) can obtain a resolution and precision equivalent to, for example, 16 to 18 bits. / A converter exists.

The above-mentioned 1-bit D / A converter outputs a pulse train consisting of "1 (high level)" and "0 (low level)" according to the input data by requantizing the input data. It is. For this reason, when the input data is, for example, data indicating a large positive value, the output of the 1-bit D / A converter has a high occurrence frequency of the sign of “1”, while the input data has a large negative value, for example. , The 1-bit D /
In the output of the A-converter, the frequency of occurrence of the code "0" is high (in other words, the frequency of occurrence of the code "1" is low).
When the input data is continuous data of "0", the D / A converter outputs a pulse train in which the frequency of occurrence of the codes of "1" and "0" is totally half in total. . Note that "1" and "0" in the output of the 1-bit D / A converter are digital signal expressions, and that "0" is actually "-1" whose level is negative. Means. This D /
The output pulse train from the A-converter is thereafter subjected to, for example, waveform shaping, and further converted to an analog waveform signal via a low-pass filter or the like.

[0004]

Here, in a case where a signal of a certain pulse train is waveform-shaped and an analog sound signal is generated through a low-pass filter or the like, for example, a complete silent sound signal is converted from the pulse train. In order to generate the pulse train, for example, “101010...
"Or" 110011001100 "as shown in FIG.
.. "Or a pulse train in which the code generation frequencies of" 1 "and" 0 "are equal per unit number and the same pattern is repeated.

As shown in FIG. 6, a signal composed of a pulse train in which the code generation frequencies of "1" and "0" are equal and the same pattern is repeated per unit number is, for example, 1 band in a band of several hundred KHz or more. Only two spectra stand, and the level is theoretically lower in the lower band-
信号 (−infinity) dB. Hereinafter, such a signal is referred to as a mute pattern.

When the input data is continuous data of "0", the output pulse train of a normal 1-bit D / A converter has a total code generation frequency of "1" and "0" as described above. Although it is evenly divided, due to the nature of the ΔΣ modulation, each output pulse does not have a fixed pattern, but becomes a nearly random pulse train as shown in FIG. A signal of a pulse sequence close to random as shown in FIG. 7 has much noise in a high frequency band and has a spectrum as shown in FIG. For this reason, even if the input data is, for example, silent voice data (voice data in which “0” continues, hereinafter, referred to as silent data), 1
The audio signal generated from the output pulse train of the bit D / A converter does not theoretically have no audible noise level. That is, the S / N of the audio signal is reduced due to the interaction between the theoretical noise and the high-frequency noise or jitter.

[0007] For this reason, some conventional D / A converters have the object of avoiding the above-mentioned reduction in S / N and reducing the noise level when the input data is unvoiced data. For example, it is detected that data of "0" continues for a certain period of time as input data (hereinafter, this is referred to as zero detection), and the output pulse train is forcibly switched to the mute pattern according to the zero detection.
An A converter is present.

However, such a D / A that switches the output pulse train to a mute pattern in response to the detection of zero.
In the case of the converter, the output pulse train that is originally continuous (even if it is a pulse train generated from silent data is continuous) is immediately converted to the original pulse train as shown in FIG. Since the mute pattern is switched to an unrelated mute pattern, a discontinuous point occurs in the switching unit. For this reason, the output pulse train as shown in FIG. 9A is subjected to waveform shaping, and the analog audio signal generated through the low-pass filter is shown in FIG. 9B due to the discontinuity. Such noise (for example, noise of a sound such as “petit”) occurs.

As a technique for reducing the switching noise caused by the discontinuous point, for example, Japanese Patent Laid-Open No. 8-186497
Japanese Patent Application Laid-Open Publication No. H11-163873 discloses a technique in which the integrated value of an output pulse is monitored, the timing is adjusted, and switching is performed at a place where the influence is small. However, also in this case, it is difficult to eliminate the switching noise, and there is a problem that the operation is complicated and the scale becomes large.

In the above description, a case where the ΔΣ modulation output is represented by binary values of “1” and “0”, that is, one bit is taken as an example. PWM (pulse width modulation) of requantized output
There is also a D / A converter that is represented by using a voltage value by a resistor or a resistor adder. That is, for example, the output of the ΔΣ modulator is, for example, 3 bits and ± 3 bits obtained from these 3 bits
There are D / A converters that output PWM waveforms or voltages having widths corresponding to seven values of 3, ± 2, ± 1, and 0. As described above, when the requantization is performed in a plurality of bits, there is a zero-level value unlike the above-described case where the Δ１ modulation output is one bit. However, for example, input data is continuous data of “0”. Even if the output is not fixed to the zero level, the signal becomes a random signal having much noise in a high frequency band, as in the case where the ΔΣ modulation output is 1 bit.

Therefore, the present invention has been made in view of such circumstances, and has a simple structure without any switching noise and an output pulse train when data of continuous "0" is input. It is an object of the present invention to provide a D / A converter capable of fixing a signal to a mute pattern or a zero level.

[0012]

According to the present invention, there is provided a D / A converter comprising a ΔΣ modulation means having an even-order integrator, and a last stage integrator in the ΔΣ modulation means which is located immediately before the last stage. A feedback path to the integrator, zero detection means for detecting that the input digital data is data for which zero data continues for a certain period, and ΔΣ when detecting that the input digital data is data for which zero data continues for a certain period. By adding predetermined data to a predetermined integrator in the modulation means, the output of the ΔΣ modulation means can be converted into a pulse train having the same code generation frequency of “1” and “0” per unit and repeating the same pattern. The above-mentioned problem is solved by having the output adjusting means.

Further, the D / A converter of the present invention provides a ΔΣ modulation means having an even-order integrator and a signal from the last integrator in the ΔΣ modulation means to the integrator immediately before the last stage. A feedback path, zero detection means for detecting that the input digital data is data for which zero data continues for a certain period of time, and, when detecting that the input digital data is data for which zero data continues for a certain period of time, the ΔΣ modulation means The above-mentioned problem is solved by adding output data to a predetermined integrator so as to provide an output of the ΔΣ modulation unit with a fixed voltage output or a fixed pulse width modulation output waveform by adding predetermined data.

That is, according to the D / A converter of the present invention, when the zero detection means detects that the input digital data is data that has zero data for a certain period of time,
By adding predetermined data to a predetermined integrator in the ΔΣ modulation means, the output bit sequence of the ΔΣ modulation means is theoretically zero in the audible band.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a D / A according to an embodiment of the present invention.
2 shows a configuration of a converter 30.

The D / A converter 30 according to the embodiment of the present invention
As shown in FIG. 1, an input unit 29 to which digital data such as voice is input, and an input data interface (I / I) for converting the input digital data into data that can be handled in the D / A converter 30. F) Part 31
And a digital interpolation filter 3 for performing interpolation between data, etc.
2. a zero detector 33 for detecting the continuation of "0" from the input data; a mute signal input unit 35 for receiving a mute signal for gradually converting the input data to "0"data;
A ΔΣ modulator 38 for converting multi-bit data into 1-bit data, a waveform shaper 40 for shaping a data waveform,
And an output section 42 of the D / A converter 30.

In FIG. 1, for example, voice digital data is input to an input unit 29. The input digital data is input to the digital interpolation filter 32 and the zero detector 33 via the input data interface unit 31.

When the zero detector 33 detects that data of "0" continues as input digital data for a certain period of time or more, it regards the input digital data as silent data and sets the detection signal 34 to "1" ( On the other hand, if the input digital data is no longer "0", the detection signal 34 is immediately set.
To “0”. The detection signal 3 from the zero detector 33
4 is input to the OR gate 39.

The digital interpolation filter 32 appropriately interpolates between the data of the supplied input digital data and changes the sampling frequency to, for example, 64 of the input data.
Convert to double the rate. When the mute signal from the mute signal input unit 28 becomes “1”, the digital interpolation filter 32 multiplies the input digital data (audio data) by a coefficient whose value gradually decreases, and To the data of "0" smoothly. The output data 37 from the digital interpolation filter 32 is Δ
入 力 Input to the modulator 38.

The OR gate 39 takes the logical sum of the mute signal and the detection signal 34 and supplies the output signal to the ΔΣ modulator 38 as a fraction removal signal 36. In other words, the OR gate 39 outputs a signal of “1” as the fraction removal signal 36 while either the detection signal 34 or the mute signal is “1”.

The ΔΣ modulator 38 operates at a frequency of the same rate as that of the oversampling by the digital interpolation filter 32 (a rate 64 times the input data), and converts the multi-bit interpolated data into one bit. (Ie, perform requantization). At this time, the re-quantization noise generated when converting to the one bit is concentrated on a high frequency to secure a certain level of S / N in the audible band. The specific configuration and operation of the ΔΣ modulator 38 will be described later. 1-bit data 53 from the ΔΣ modulator 38
Is input to the waveform shaper 40.

The waveform shaper 40 transforms the 1-bit data 53 from the ΔΣ modulator 38 into a so-called return zero waveform or the like. For example, a clock generated by a separate power supply or a clock with less jitter improves the analog characteristics. The waveform is shaped as follows. The output signal 41 of the waveform shaper 40 is
This is the output signal of the D / A converter of FIG. The output signal of the D / A converter of FIG. 1 is thereafter made to have a smooth analog waveform by passing through an analog low-pass filter (not shown).

FIG. 2 shows the configuration of the ΔΣ modulator 38. As shown in FIG. 2, the ΔΣ modulator 38 has an even number of integrators each having the same configuration (in this embodiment, four integrators 60 to 63 from the first stage to the fourth stage).
And each of the integrators 60, 61,
Shifters 64 and 6 for shifting the respective outputs of
5, 66, a quantizer 52 for requantizing data after integration by the integrators 60 to 63, a delay circuit 59 for feeding back output data of the quantizer 52 to each of the integrators 60 to 63, and a feedback path 54. A local feedback path 55 for locally feedback (negative feedback) data between an integrator 63 of the fourth stage and an integrator 62 of the third stage, an arithmetic unit 69, and a shifter 70; Fraction remover 5 for removing the fraction generated by the integrator 60 of the second stage and the integrator 61 of the second stage.
7 and 58 and arithmetic units 67 and 68.

In FIG. 2, an output terminal 37 from the digital interpolation filter 32 shown in FIG.
Is input to the terminal 44, and the fraction removal signal 36 from the AND gate 39 in FIG.

The data 37 from the input terminal 43 is sent to a first-stage integrator 60. This first stage integrator 60
And the integrators 61, 62, and 63 at the next and subsequent stages are integrators having the same configuration including an arithmetic unit 71, a delay unit 72, and an arithmetic unit 73, respectively.

The data integrated by the first-stage integrator 60 is shifted to 1/8 by the shifter 64 and then input to the second-stage integrator 61. Hereinafter, similarly, the second
The data integrated by the integrator 61 at the first stage is shifted to シ フ ト by the shifter 65 and then input to the integrator 62 at the third stage, where it is integrated by the integrator 62 at the third stage. The shifted data is shifted by に て by the shifter 66 and then input to the integrator 63 at the fourth stage. The output of the integrator 63 of the fourth stage is requantized by the quantizer 52 and supplied as 1-bit data 53 from the ΔΣ modulator 38 to the waveform shaper 40 of FIG. And the delay unit 5
9 from the feedback path 54 via the integrator 6 of each stage.
This is fed back to 0-63.

The feedback data to the first stage integrator 60 is input to a computing unit 67 as a subtraction signal, and is sent from the computing unit 67 to a computing unit 73 of the first stage integrator 60. The feedback data to the second-stage integrator 61 is input to the calculator 68 as a subtraction signal, and is sent from the calculator 68 to the calculator 73 of the second-stage integrator 61. The feedback data to the integrator 62 at the third stage is input to the arithmetic unit 69 as a subtraction signal, and
9 to the arithmetic unit 73 of the integrator 62 at the third stage.
The feedback data to the fourth-stage integrator 63 is input to the calculator 73 of the third-stage integrator 62 as a subtraction signal.

The signal from the fraction remover 57 is supplied to the arithmetic unit 67 as an addition signal, and the signal from the fraction remover 58 is supplied to the arithmetic unit 68 as an addition signal.

The fraction remover 57 includes a first-stage integrator 6
The data from the 0 delay unit 72 is input, and in accordance with the fraction removal signal 36 from the OR gate 39 in FIG. It is generated and sent to the arithmetic unit 67 as an addition signal. The data from the delay unit 72 of the second-stage integrator 61 is input to the fraction remover 58, and the fraction remover 58 responds to the fraction remove signal 36 from the OR gate 39 in FIG. During the integration processing of, an extremely small DC component whose fraction gradually disappears is generated and sent to the arithmetic unit 68 as an addition signal.

The signal from the local feedback path 55 via the shifter 70 is supplied to the arithmetic unit 69 as a subtraction signal.
That is, the data from the integrator 63 of the fourth stage is shifted to 1/256 by the shifter 70, and
5 and the arithmetic unit 68 is negatively fed back to the arithmetic unit 73 of the integrator 62 at the third stage. The operation by the local feedback path 55 is generally called zero shift, and without this, the frequency characteristic of the quantization noise generated by the quantizer 52 simply rises as shown by a curve 90 in FIG. 3) when there is a local return path 55.
The characteristic is such that the quantization noise is reduced at a certain frequency as shown by a curve 91 in the middle. Normally, this can reduce the quantization noise level in the audible band by several dB.

Next, the D / A of the above-described embodiment of the present invention will be described.
The operation when silence data of continuous "0" is input to the input unit 29 of the converter 30 will be described below.

"0" as input data for a certain time or more
Is input, the zero detector 33 regards data in which the input data “0” is continuous as silent data, and sets the detection signal 34 at that time to “1” (the detection flag is “1”). "). When the input data is no longer “0” data, the zero detector 33 immediately returns the detection signal 34 to “0”.

The OR gate 39 outputs the detection signal 3
The logical sum of “1” of No. 4 and the mute signal is calculated. As a result, the fraction removal signal 36 becomes “1”.

Here, in the case where the input data is continuous data of "0" for a certain period of time or more, the data output from the digital interpolation filter 32 and input to the .DELTA..SIGMA. Modulator 38 becomes "0". The first stage integrator 60 receives feedback data (a signal having a value of ± 1.0) from the feedback path 54.
Is input only to the upper bits of Therefore, the integrator 60
Nothing is added to the lower bits (bits with a weight smaller than 1.0) of, and the same value remains forever. The value of the lower bits that do not move is called a fraction. This fraction is integrated by the integrator in the subsequent stage, and affects how the bit string of the ΔΣ modulation output is output.

From the above, in the present embodiment,
When the fraction removal signal 36 is "1", the fraction remover 57 detects the fraction of the first-stage integrator 60, and sets a very small D so that the fraction gradually disappears.
The C component is added to the integrator 60. As described above, when a small DC component is repeatedly integrated, carryover occurs, and the fraction eventually becomes “0”. When the fraction becomes “0”, the fraction removing circuit 57 stops adding a minute DC component.

Next, the feedback data from the feedback path 54 is provided to the integrator 61 at the second stage.
The integrated value of the first-stage integrator 60 is calculated by the shifter 64 as 1 /
Since the signal shifted to 8 is input, the minimum step of the fluctuation width of the input signal to the second integrator 61 is 1/8. Therefore, a bit having a weight smaller than the 1/8 step does not move and becomes a fraction. In the second-stage integrator 61, when the fraction removal of the first-stage integrator 60 is completed, the fraction is similarly removed.

Next, a signal obtained by shifting the integrated value of the second-stage integrator 61 to 1/4 by the shifter 65 in the same manner as described above and the feedback path 5
4 and the local feedback path 5
5 is input. That is, the second
When the fraction of the integrator 61 in the third stage is removed, only the feedback signal from the local feedback path 55 is input to the lower bits of the integrator 62 in the third stage. Since the feedback signal from the local feedback path 55 is a negative feedback signal from the fourth-stage integrator 63 to the third-stage integrator 62, these changes are reduced to act in a stable direction. .

As described above, according to the embodiment of the present invention, D /
In the A converter 30, when data (silent data) in which “0” continues for a certain period of time or longer as input data (even when the mute signal is “1”), the even-order ΔΣ modulator 38 Fractions are eliminated in the integrator preceding the local feedback path 55, and the local feedback path 55 acts to stabilize the ΔΣ modulator 38 in a monotonous operation. Thereafter, the same operation is repeated. At this time, the output data 53 of the ΔΣ modulator 38 is, for example, “1001011
.., "01001110...", A pulse train in which the code generation frequencies of "1" and "0" are equal per unit number and the same pattern is repeated, that is, a mute pattern pulse train. Therefore, by passing the output data 53 of the ΔΣ modulator 38 through the waveform shaping 40 and the low-pass filter, it is possible to obtain an audio signal that is silent in the audible band.

In summary, according to the D / A converter 30 of the embodiment of the present invention, the first and second integrators 6 of the ΔΣ modulator 38 at the time of inputting silent data.
A minute DC component is added to 0,61 to remove the fraction,
Further, by the action of the local feedback path 55, each of the integrators 60 to
63 repeats the same operation, so that the ΔΣ modulator 38
Is output as a mute pattern pulse train. This series of operations is continuous as shown in FIG. 4A because there is no operation of forcibly switching a nearly random pulse train to another mute pattern as described in the above-described conventional example. No discontinuous point occurs in the pulse train. Therefore, in the present embodiment, even if silence data is input and output data 53 of ΔΣ modulator 38 changes to a mute pattern pulse train, the pulse train is shaped as shown in FIG. 4B. The analog audio signal that has been passed through the low-pass filter does not generate noise (for example, noise of a “petit” sound) due to the discontinuous point as described above.

In this embodiment, an example using the fourth-order ΔΣ modulator 38 has been described. However, the ΔΣ modulator is not limited to the fourth order, and a higher even-order ΔΣ modulator can also be used. .
That is, for example, in the case of a sixth-order ΔΣ modulator, it is possible to cope with other orders by changing such that the fraction removal is performed from the first stage to the fourth stage integrator.

In this embodiment, 1 is used as quantization.
Although the binary one is used, the quantizer 52 is replaced with a plurality of bits, so that the multi-bit quantization ΔΣ
It can also be applied to modulators. In this case, since there is a zero-level value in the quantized value in a plurality of bits, if the same method as described above is used, a signal fixed to “0” (fixed to zero level) is output instead of the mute pattern as the output of the ΔΣ modulator. Signal). Thus, also in this example, a fixed voltage output corresponding to the “0” output or a fixed PWM waveform having a duty ratio of 50% can be output without generating switching noise.

As described above, according to the embodiment of the present invention, the output pulse of the D / A converter at the time of silence data input is converted into a pulse train of a mute pattern or a silent circuit without generating any switching noise. The signal can be fixed to “0”. This makes it possible to improve the S / N of the finally obtained analog signal,
In addition, since it is not necessary to increase the theoretical S / N of the Δ 大 き く modulation, the sampling frequency can be set low, which contributes to low power consumption.

[0044]

As is apparent from the above description, in the D / A converter of the present invention, when the zero detecting means detects that the input digital data is data that continues for zero time from the input digital data, the ΔΣ modulation is performed. By adding predetermined data to a predetermined integrator in the means, the output of the ΔΣ modulation means is a pulse train in which the code generation frequencies of “1” and “0” are equal per unit number and the same pattern is repeated. Or, by changing the output of the ΔΣ modulation means into a fixed voltage output or a fixed pulse width modulation output waveform, data having continuous “0” was input with a simple structure and without any switching noise. The output pulse train at the time can be fixed to a mute pattern or zero level, and the noise of the finally obtained analog waveform signal is theoretically reduced to zero in the audible band. Possible it is.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram illustrating an overall configuration example of a D / A converter according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific configuration example of a ΔΣ modulator provided in the D / A converter according to the embodiment of the present invention.

FIG. 3 is a diagram illustrating frequency characteristics of quantization noise generated by a quantizer when zero shift is not performed by a local feedback path, and frequency characteristics of quantization noise generated by the quantizer when zero shift is performed; is there.

FIG. 4 is a waveform chart showing an output pulse train of the D / A converter according to the embodiment of the present invention and an example of an analog waveform signal after passing through a low-pass filter.

FIG. 5 is a diagram illustrating an example of a mute pattern.

FIG. 6 is a diagram illustrating an example of a spectrum of a mute pattern.

FIG. 7 is a diagram illustrating an example of an output pulse train of a normal 1-bit D / A converter.

FIG. 8 is a diagram illustrating frequency characteristics of quantization noise generated by requantization of a normal 1-bit D / A converter.

FIG. 9 is a waveform diagram illustrating an example of an analog waveform signal after passing through a pulse train and a low-pass filter when an output pulse train of a normal 1-bit D / A converter is forcibly switched to a mute pattern during silence.

[Explanation of symbols]

30 D / A converter, 31 input data interface unit, 32 digital interpolation filter, 33
Zero detector, 38 ΔΣ modulator, 39 OR gate, 52 quantizer, 57, 58 fraction remover,
59,72 delay unit, 60-63 integrator, 64,6
5, 66, 70 shifter, 67 to 69, 71, 73
Arithmetic unit

Claims (2)

[Claims] 1. A 1-bit D / A converter using oversampling and ΔΣ modulation, comprising: ΔΣ modulation means having an even-order integrator; and a last stage integrator in the ΔΣ modulation means. A feedback path to the integrator immediately before the last stage; zero detection means for detecting that the input digital data is data continuing zero data for a certain period; By adding predetermined data to a predetermined integrator in the ΔΣ modulation means when detecting that the zero data is continuous data, the output of the ΔΣ modulation means is set to “1” per unit number. A D / A converter comprising: a pulse train in which the code generation frequency of “0” is equal and the same pattern is repeated. 2. A multi-bit D / A converter using oversampling and ΔΣ modulation, wherein ΔΣ modulation means provided with an even-order integrator, and a last stage integrator in the ΔΣ modulation means. A feedback path to the integrator immediately before the last stage; zero detection means for detecting that the input digital data is data continuing zero data for a certain period; By adding predetermined data to a predetermined integrator in the ΔΣ modulation means when detecting that the zero data is continuous data, the output of the ΔΣ modulation means is fixed voltage output or fixed pulse width modulation. A D / A converter, comprising: output adjusting means for outputting an output waveform.