JPS63203077A - Circuit for preventing character quivering in video circuit - Google Patents

Abstract

PURPOSE:To always display a character such as a track number at the same location without longitudinal quivering by providing a monostable multivibrator circuit and counting a horizontal synchronizing signal in a composite synchronizing signal based on the time point of the end of its operation. CONSTITUTION:When an integration circuit 10 detects a vertical synchronizing signal V.Sync based on a composite synchronizing signal C.Sync in a 0.5H delay period, the signal is taken in a character generation IC9. On the other hand, the monostable multivibrator 13 is triggered on the leading edge of the timing t1 to turn on a transistor (TR) 14. Then even when the signal H.Sync is to be taken in the IC9 by inverting the signal C.Sync by the TR 11, the signal is given to the ground side by the TR 14 and only a pulse of nearly 8H is given. Then the monostable multivibrator 13 is turned off and the TR 14 is turned off, then the signal H.Sync is outputted sequentially to the IC 9. Then the signal H.Sync is counted, based on the operating end timing t2 of the monostable multivibrator 13 to decide the character display position, then the counting of a noise pulse A as 1H is avoided.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a character blur prevention circuit in a video circuit such as a still image reproduction device.

BACKGROUND OF THE INVENTION In recent years, still image playback devices have been commercially available that magnetically record photographic images taken with a camera on a still image floppy disk and play the recorded images on a regular television. Here, the video signal is recorded on a plurality of tracks on the disk in a relationship of one track per screen, that is, one rotation minus one field. Then, such a video signal is read from the disk by a head, demodulated, and output.

By the way, in the normal television standard system, a 1/2 interlaced scanning (so-called interlaced scanning) system is adopted. For example, in the NTSC system like Japan, the number of horizontal scanning lines in one field is 262.5H, and the number of striped scanning lines for one screen in two fields, that is, one frame, is 52.
It is set to be 5H. When a still image disc or the like on which one field (ie, 262.degree. 5H horizontal scanning line) of video signals is recorded on one track is played back by such a television, the recording seam becomes a problem. In other words, the video signal on the same track (always the same video signal for each field) is read while the still image disc is continuously rotated, but at the recording joint (i.e., end point = start point) .5H1, that is, a shift of 1/2 of the horizontal synchronization period for each field. Therefore, if the image is reproduced as is on a normal television receiver, the screen will be distorted, making it impossible to display a normal still image.

Therefore, by alternately passing the 1-field repeated playback signal from the recording joint on the track through 0 and 5H delay circuits that correspond to 1/2 horizontal horizontal period for each field, and by synthesizing these signals, continuous horizontal synchronization can be achieved. It is necessary to create a playback signal.

For this reason, a block configuration as shown in FIG. 3 is generally adopted. First, after a video playback signal on a certain track read by the playback head 1 is amplified by the head amplifier 2, one side becomes a non-delayed through signal, and the other side becomes a through signal.
/2 horizontal period through 0.5H delay circuit 3.
The signal is input to the demodulation circuit (FM) 4 as a 5H delay signal. Here, in the demodulation circuit, these through signals and 0.
5H delay signal and switching pulse signal 5WP (
Y) (Y means a luminance signal) is alternately switched for each field. The demodulated signal is then separated by a synchronization signal separation circuit 5 as a composite synchronization signal (C-8ynC), which is then passed through a synchronization signal generation circuit 6 to generate a synchronization signal, which is then combined with the signal demodulated by the demodulation circuit 4. The waveform synthesis circuit 7 synthesizes the signals and outputs them to the receiver as a frame signal (video signal).

Here, the switching pulse signal 5WP(Y) selects the through signal and the 0°5H delay signal by switching between the H level and the L level for each field as shown in FIG.゜5H delay period is generated, but the switching pulse signal s
Among these, wp(y) has a vertical through period (low level) during the 0°5H delay period, and is set in the through signal selection state only during the vertical synchronization period.

In the timing chart shown in FIG. 4, the video signal is placed between the horizontal synchronizing signals in the IH row. Also, near vertical synchronization, there are multiple equivalent pulses arranged in 0.5H,
Six of these equivalent pulses, ie, 3H, are used as the vertical synchronizing signal V. Above this, before and after the vertical synchronizing signal (2), there are also six equivalent pulses, that is, 0.5H arranged V detection portions each having 3H. Switching pulse signal 5WP
(Y) has a vertical through period of about 18 equivalent pulses within the 0.5H delay period,
Among them, the actual vertical synchronization signal (2) is detected and output as is as a through signal.

This is the basic method for preventing image blur in each field.

By the way, when playing such a still image, the characters of the track number in which the still image is recorded may be displayed on the screen together with the still image.

Such character information such as a track number is not recorded on the disc, but is processed by a circuit as shown in FIG. 5, for example. First, the microcomputer 8 writes data for determining the character display position to the character generation IC 9, and when the character generation IC 9 reaches the display position, the character data is outputted and displayed. At this time, the track number is displayed, for example, at the upper right position of the screen, but in any case, it is preferable to specify the position where the character is displayed and always display it at the same position. Therefore, the character generating IC 9 receives the vertical synchronizing signal 5ync through the integrating circuit 10 based on the composite synchronizing signal C-3ync, and passes the horizontal synchronizing signal H- Then, as shown in FIG. 6, from the point in time (rising edge) when the vertical synchronizing signal SYNC is detected through the integrating circuit 10, the number of horizontal synchronizing signals H-8ynCO is counted, and a predetermined value determined by the program is counted. The track number characters are displayed at n positions, that is, at n H positions.The problem that the invention attempts to solve is that when the switching pulse signal swp(y) falls, the broken line in FIG. Whisker-like switching noise, as shown by pulse A in Sync, may appear on the composite synchronization signal C-8sync.Here, in order to determine the track number character display position, the vertical synchronization signal The synchronization signal H Sync is counted sequentially, but this noise pulse A is also counted as an IH minute, and compared to the through period, it is about an IH minute earlier, and nX
Since it is a count value of H, the display position will be for IH. Since such IH-shifted character display is repeated alternately, the track number display becomes a blurred display state in which the characters flicker vertically.

Means for Solving the Problem Disable the output of the composite synchronization signal to the character generation IC from the rise of the vertical synchronization signal to at least the fall of the vertical through period, and set the operation end point to the composite synchronization signal. A monostable circuit is provided to use as a reference time for counting horizontal synchronization signals.

The falling edge at the end of the active vertical slew period may cause the composite sync signal to contain whisker-like noise pulses equivalent to the horizontal sync signal, but during this period the monostable circuit does not Since the output of the horizontal synchronizing signal is disabled and masked, and the horizontal synchronizing signal is counted based on the point in time when the operation of the monostable circuit ends, noise pulses will not be counted. Therefore, the characters of the track number, etc. are always output to the same horizontal synchronizing signal portion, and no vertical blurring or the like occurs.

Embodiment An embodiment of the present invention will be explained based on FIGS. 1 and 2. Components that are the same as those shown in FIGS. 3 to 6 are indicated using the same reference numerals. In this embodiment, a monostable circuit 1 operates based on the output of the integrating circuit 10 to mask the input of the horizontal synchronizing signal H-3ync for the character generation C9 for a certain period of time.
2. That is, this monostable circuit 12 receives the vertical synchronization signal ■・S detected by the integrating circuit 10.
It has a monostable multivibrator 13 that is triggered by the rise of ync, and a transistor 14 that is turned on by the output of this monostable multivibrator 13 is connected in parallel to the transistor 11. Here, the number of monostable multivibrators 13 is m, for example, 8H, counting from the rising timing t of the vertical synchronization signal SYNC.
The setting is such that the output can be generated over a length of approximately 300 degrees. That is, it is set so that it can be output at least until timing t2, which is later than the falling edge of the vertical through period of the switching pulse signal swp(y).

lO- According to such a configuration, when the integration circuit 10 detects the vertical synchronization signal V-5ync based on the composite synchronization signal C-3ync during the 0.5H delay period, that signal is taken into the character generation IC 9. On the other hand, the monostable multivibrator 13 is triggered at the rising edge of timing t1, turning on the transistor 14. Therefore,
Composite synchronization signal C-5ync is transferred to transistor 11
horizontal synchronizing signal H-5yn to the character generation IC9.
Transistor 14 that is on even when trying to take in c
The signal is canceled to the ground side, and only one pulse lasting about 8H is given. Then, when the monostable multivibrator 13 is turned off and the transistor 14 is turned off, the fifth
Similar to the case shown in the figure, the horizontal synchronizing signal H-5sync is sequentially output to the character generation IC 9. Therefore, if the character display position is determined by counting the horizontal synchronizing signal H-3 sync based on the operation end timing t2 of the monostable multivibrator 13 (the counted value is, for example, nm H's). , the noise pulse A is no longer counted as IH. In other words, instead of counting directly from the rising edge of the vertical synchronizing signal V・Sync, the horizontal synchronizing signal H
This is the reference time point for counting -3 sync. As a result, the track number can always be displayed on the same horizontal synchronization line without repeating the 18-minute vertical shift.

Effects of the Invention As described above, the present invention provides a monostable circuit that operates for a certain period of time from the vertical synchronization detection point in the 0.5H delay period, and counts the horizontal synchronization signal in the composite synchronization signal based on the point in time when the operation ends. Therefore, even if whisker-like noise pulses occur in the composite synchronization signal due to the fall of the vertical through period, the monostable circuit masks them and makes them invalid, so the noise pulses will not be counted. Therefore, it is possible to always display track numbers and the like in the same position without any vertical shift.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing an embodiment of the present invention, Fig. 2 is a timing chart showing its operation, Fig. 3 is a circuit diagram showing general video signal processing, and Fig. 4 is a timing chart showing its operation. 5 is a circuit diagram showing a conventional example, and FIG. 6 is a timing chart showing its operation.

Claims (1)

[Claims] A composite synchronization signal in which a horizontal synchronization signal and a vertical synchronization signal are mixed is used, and a through period in which the video signal is output as a through signal, and the through signal is set to 0.5.
Output as a 0.5H delay signal delayed by H0
．． Vertical synchronization is achieved by using a switching control signal that has a vertical through period that switches the 5H delay period for each field, and outputs the vertical synchronization signal in a through signal state without delay during vertical synchronization during the 0.5H delay period. In a character blur prevention circuit in a video circuit equipped with a character generation IC that determines the output position of a displayed character by counting the number of pulses of a horizontal synchronization signal in the composite synchronization signal based on signal detection, The output of the composite sync signal to the character generation IC from the rising edge to at least after the falling edge of the vertical through period is disabled, and the operation end point is set as a reference time for counting horizontal sync signals in the composite sync signal. What is claimed is: 1. A circuit for preventing character blurring in a video circuit, characterized in that a monostable circuit is provided.