JPS63193783A - N-fold scan television receiver - Google Patents

Abstract

PURPOSE:To improve a phase error answer when a normal horizontal synchronizing signal is inputted by constituting a two-fold horizontal synchronism generation circuit and a two-fold horizontal deflection circuit in one phase locked loop circuit. CONSTITUTION:A phase locked loop circuit 9 consists of a phase comparator 13, a low pass filter 14, a voltage controlled oscillator 15 and a 1/2 frequency divider 19. A 1/910 frequency divider 18 is provided before the phase synchronous circuit 9, and it always operates the phase comparator 13 with a normal horizontal synchronizing frequency. If the normal horizontal synchronizing signal is selected as an input signal, the normal horizontal synchronizing signal is inputted to the phase comparator 13. If an n-fold horizontal synchronizing signal is selected, the horizontal synchronizing signal whose frequency has become the same as the normal horizontal synchronizing signal by the 1/910-frequency divider is inputted to the phase comparator 13. For switching a standard signal and the two-fold signal as the input signal, the phase synchronous circuit of horizontal synchronism can be constituted in one stage, whereby the same phase error answer can be obtained. If the normal signal is inputted, the phase error answer can considerably be improved.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a television receiver that uses a digital circuit to double-speed convert a video signal and perform double-density scanning. The present invention relates to a television receiver suitable for inputting two systems of double-speed signals.

[Conventional technology]

Japan's standard television broadcasting system uses an interlaced scanning system. This is a method in which one screen (frame) is made up of two coarse screens (fields), and since the entire screen is repeated every 1/60 seconds, large-area flickers are not very noticeable. However, in areas where the scanning line structure is noticeable or where the brightness changes significantly in the vertical direction, line flickers occur every 1/30 seconds, which causes image quality deterioration. Therefore, there is a known method for reducing the image quality deterioration caused by these disturbances, and a device that displays a screen by increasing the number of scanning lines in one field to four times the normal number is known. Generally, ru is 2, so the following description will be made assuming ru = 2.

Conventionally, the sixth synchronization generating circuit used in this device was
A circuit as shown in the figure is known. In Figure 6, 4
2 is a normal horizontal synchronization signal input terminal, 43 is a double-speed horizontal synchronization generation circuit, 44 is a double-speed horizontal synchronization signal input terminal, 45 is a double-speed horizontal deflection circuit, and 46 is a double-speed horizontal output.

Next, the operation will be explained. First, when normal horizontal synchronization is input, the double-speed horizontal synchronization generation circuit 43 generates double-speed horizontal synchronization having a period 1/2 of the normal horizontal synchronization. The generated double-speed horizontal synchronization is input to a double-speed horizontal deflection circuit 45, which outputs a five-times-speed horizontal synchronization signal 46 to perform horizontal scanning at double speed. Considering a double-speed RGB signal as an input signal, a double-speed horizontal synchronization signal is input together with this signal, but when this double-speed horizontal synchronization signal 44 is input, it is directly input to the double-speed horizontal deflection circuit 45 by switching a switch. Then, a double-speed horizontal output signal 46 is output.

Here, the double-speed horizontal synchronization generation circuit 43 and the double-speed horizontal deflection circuit 45 will be explained. In FIG. 7, (α) shows the double-speed horizontal synchronization generation circuit 43, and (b) shows the double-speed horizontal deflection circuit 4.
5, 47 is a phase comparator, 48 is a low pass filter (LPF), 49 is a voltage controlled oscillator (rCO),
50 is a frequency divider by 2, and 51 is a flyback transformer.

As shown in the figure, the double-speed horizontal synchronization generation circuit 43 is a phase synchronization circuit that inputs the normal horizontal synchronization 42 and outputs the double-speed horizontal synchronization signal 44, and the double-speed horizontal deflection circuit 45 inputs the double-speed horizontal synchronization 44 and is a phase synchronization circuit that outputs the double-speed horizontal synchronization signal 44. This is a phase synchronized circuit that outputs a horizontal output 46.

Therefore, when double-speed horizontal sync is input as an input signal, double-speed horizontal sync is directly input to the deflection circuit and horizontal scanning is performed as in a normal television receiver, but normal horizontal sync is input as an input signal. In this case, horizontal scanning is performed by cascading two stages of phase synchronization circuits: a double-speed horizontal synchronization generation circuit and a double-speed horizontal deflection circuit. In addition, related devices of this type include Japanese Patent Application Laid-open No. 57-1522.
No. 79 is mentioned.

[Problem that the invention seeks to solve]

In the above conventional technology, when the input signal is double-speed horizontal synchronization,
A normal television receiver has a horizontal scanning frequency of 2
There is no particular problem since the circuit configuration remains the same, just doubling the size. However, when normal horizontal synchronization is input, a double-speed horizontal synchronization generation circuit and a phase synchronization circuit are added to the circuit configuration when double-speed horizontal synchronization is input, so it looks like a normal TV signal. This is good when the synchronization is stable, but when a signal containing noise or a signal containing skinny signals such as those from a VTR is input, there is a problem in that the phase error response deteriorates.

Here, the above phase error response will be explained.

In FIG. 8, (al indicates the screen of a normal television receiver, and <h> indicates the screen of a double-density scanning television receiver having the same circuit configuration as the conventional example. Skinny et al. This does not appear on the screen because it occurs during vertical blanking, but if the response is poor, it may appear at the top of the screen, or it may not appear on the screen during special playback on a VTR or the like.

Now, to make it easier to understand, the screen is showing the screen when a signal in which the horizontal synchronization phase suddenly changes near the center of the screen is input. In (z), the phase error response in the horizontal deflection circuit appears on the screen as is, but in (h), as shown by the broken line, the phase error response in the double-speed horizontal synchronization generation circuit is added to the screen. appear. In other words (b
In 1, the phase-locked circuits are connected in cascade in two stages, so the output when the first-stage phase-locked circuit follows the input and the second-stage phase-locked circuit follows its output. will appear on the screen. Therefore (A)
In this case, the phase error response becomes worse with respect to (α). Furthermore, since there were two stages of phase-locked circuits, twice as many circuits and adjustments were required.

The purpose of the present invention is to have the same followability when normal horizontal synchronization is input as an input signal and when double-speed horizontal synchronization is input, and to have a phase error when normal horizontal synchronization is input. The goal is to improve response. Furthermore, the present invention aims to simplify circuits, adjustments, and the like.

[Means for solving problems]

The above object is achieved by configuring the double-speed horizontal synchronization generation circuit and the double-speed horizontal deflection circuit in one phase synchronization circuit. In other words, the phase-locked circuit consists of a phase comparator, a low-pass filter, a voltage-controlled oscillator, and an M frequency divider.The first method is to provide an M frequency divider before the phase-locked circuit and perform a phase comparison. On the other hand, as a second method, the division ratio of the M frequency divider is switched according to the input synchronization, and the phase comparator is always operated at the input horizontal synchronization frequency. There is a way to make it work.

The above object is achieved by the means described above.

[Effect]

In the first means, when the normal horizontal synchronization signal is selected as the input signal, the normal horizontal synchronization signal is input to the phase comparator, whereas when the 9x horizontal synchronization is selected, the normal horizontal synchronization signal is input to the phase comparator. , M frequency divider makes the horizontal synchronization frequency the same as the normal horizontal synchronization frequency, and the horizontal synchronization signal is input to the phase comparator.

Further, in the second means, when the normal horizontal synchronizing signal is selected, the normal horizontal synchronizing signal is input to the phase comparator, and the phase is compared with the signal passed through the M frequency divider. On the other hand, when the nine-times horizontal synchronization signal is selected, the nine-times horizontal synchronization signal is input as is to the phase comparator, and the phase is compared with the signal with the frequency division ratio M switched.

As described above, the double-speed synchronization generation circuit and the double-speed horizontal deflection circuit can be configured by a single-stage phase synchronization circuit.

〔Example〕

A first embodiment of the present invention will be described below with reference to FIG.

In FIG. 1, 1 is a normal video signal input terminal, 2 is a normal RGB signal input terminal, 3 is a double-speed ROB signal input terminal, and 4 is a normal video signal input terminal.
5 is a demodulation circuit, 5 is a synchronous separation circuit, 6 is a horizontal synchronous divide-by-2 circuit, 7 is a double speed conversion circuit, 8 is a video output circuit, 9 is a double speed horizontal AFC circuit, 10 is a vertical deflection circuit, and 11 is a plow/tube. be.

Next, the overall operation will be explained. The input normal video signal 1 is demodulated by the demodulation circuit 4 and switched to the normal RGE signal 2. The switched signal is input to the double speed conversion circuit 7 and is converted into a double speed signal with a normal horizontal scanning period of 172. Here, the double speed converted signal and the double speed RG
The B signal 3 is switched and inputted to the video output circuit 8 to drive the cathode ray tube 11. On the other hand, the synchronization signal is obtained by switching between the separated synchronization and the normal RGB signal 2 in the synchronization separation circuit 5, and then the double-speed RGB signal 3 whose frequency is the same as the normal horizontal synchronization frequency by the horizontal synchronization 2 divider circuit 6.
The horizontal synchronization is input to the double-speed horizontal AFC circuit 9, the vertical synchronization is input to the vertical deflection circuit 10, and the deflection signal is supplied to the deflection yoke. In addition, double-speed horizontal AFC
The circuit 9 generates a clock synchronized with the input horizontal synchronization and outputs it to the double speed conversion circuit 7 and the like.

The operations of the double-speed horizontal AFC circuit 9 and the double-speed conversion circuit 7 will be described in detail below.

First, regarding the double-speed horizontal AFC circuit 9 and its peripheral components,
Figure 2 shows its detailed configuration. In Figure 2, 30
is a normal horizontal synchronization signal input terminal, 31 is a double-speed horizontal synchronization signal input terminal, 32 is a switch, 13 is a phase comparator, 14 is a VCo for the LPF 115, 1f is an 8fsc clock, 1
7 is a 4fzc clock, 18 is a 910 frequency divider circuit, 19 is a 2 frequency divider circuit, 20 is a waveform shaping circuit, 21 is a double-speed horizontal drive circuit, 22 is a double-speed horizontal output circuit, 23 is a horizontal deflection yoke, and 24 is a flyback transformer. , 25 is a high voltage limiting circuit. First, the operation when a normal video signal is input will be explained. A voltage corresponding to the phase difference between the normal horizontal synchronization signal 12 inputted to the phase comparator 13 and the output from the divide-by-2 circuit 19 is inputted to the VCO 15 through the LPF 14. Here, the VCO 15 is the color subcarrier frequency Cfzc)
The 8bc clock 16, which is a clock with a frequency eight times as high as 8bc, is generated. By dividing this clock by two, a 4hc clock is obtained.

The Naori lock will be described later, but A of the double speed conversion circuit
Used as a sampling clock for the /D converter and a writing/reading clock for the write/memory.

Also, the relationship between the horizontal synchronization frequency e (fH) and fsc is rf
From H= fsc, double-speed horizontal synchronization is 2fH=-! -81. c, double-speed horizontal synchronization can be obtained by dividing the clock 16 by 910. Further divide-by-2 circuit 19
Normal horizontal synchronization is obtained by dividing the frequency by two, and by inputting it to the phase comparator 13, a phase synchronization circuit is constructed. The double-speed horizontal synchronization signal output from the 910 frequency divider circuit 18 is waveform-shaped by a waveform shaping circuit 20, inputted to a double-speed horizontal drive circuit 21, drives a double-speed horizontal output circuit 22, and is supplied to the horizontal deflection yoke 23. Further, the output of the double-speed horizontal output circuit 22 is input to a flyback transformer 24, where it is boosted and rectified to generate the power supply voltage necessary for each circuit.

The flyback pulse generated by the flyback transformer 24 is input to the high voltage limiting circuit 25, and if the flyback pulse becomes large due to a failure in the power supply circuit or the like and the high voltage rises abnormally, the oscillation is stopped and the horizontal It is designed not to deflect. Further, as the signal for phase comparison in the phase comparator 13, a signal obtained by inputting and frequency-dividing the output flyback pulse from the flyback transformer to the frequency divider circuit 19 may be used, as shown by the broken line in FIG.

Next, the operation when a double-speed video signal is input will be described. When inputting a double-speed video signal, switch 3.
2 closes on the opposite side to that shown in the figure, and sends the output of the double-speed horizontal synchronizing signal divided by two by the frequency dividing circuit 6 to the phase comparator 13. Since this output has exactly the same frequency as a normal video signal, the other parts of the operation are the same as described above.

The vertical deflection circuit 10 has the same vertical synchronization period of about 1/60 second for double-speed signals and normal signals, so it is the same circuit as the vertical deflection circuit of a normal television receiver.

Next, the double speed conversion circuit 7 will be explained. Here, the video input signals of the double speed conversion circuit 7 are normal luminance signals and color difference signals, and are outputted in the form of double speed brightness signals and color difference signals.

The specific structure of the double speed conversion circuit 7 is shown in FIGS. 3 and 4. In FIG. 3, 26 is a video signal input terminal for a luminance signal or a color difference signal, 27 is an A/D converter, 28 is a line memory, and 29 is a D/A converter. FIG. 4 is a diagram showing the operation in the line memory. The video signal 26 is input to the A/D converter 27 and is converted to 4 fsc.
The signal is sampled by the clock 17 and input to the line memory 28. The clock to write to line memory is also 4Lc.
Although it is a clock, data reading is performed using a double Bfyc clock 16. This data is converted to D/A converter 29.
By performing the /A conversion, a double-speed video signal with a cycle of 1/2 of the normal frequency can be obtained. FIG. 4 shows the operation of this line memory, and as shown in the figure, double-speed video signals are continuously obtained by alternately writing data into line memories 1 and 2 and switching reading.

In this way, the double-speed converted video signal is sent to the video amplification/output circuit 8, which has twice the bandwidth of a normal television receiver.
The signal is then output to the cathode ray tube 11 and scanned with a double-speed horizontal output signal produced by the double-speed AFC circuit 9.

Another embodiment of the double-speed AFC circuit 9 will now be described with reference to FIG. In FIG. 5, 30 is a normal horizontal synchronization input terminal, 31 is a double-speed horizontal synchronization input terminal, 32 is a synchronization changeover switch α, and 33 is a changeover switch b. The operation will be explained here. When a normal signal is selected as the input signal, the selector switch a32
As a result, normal horizontal synchronization is input to the phase comparator 13, and the same operation as in the embodiment described above is performed. Here, a case in which double-speed horizontal synchronization is input will be described. First, the double-speed horizontal synchronization selected by the changeover switch α32 is input to the phase comparator 13. Then, the changeover switch h33 compares the phase with the signal that does not pass through the frequency dividing circuit 19, and the voltage corresponding to the phase difference is passed through the LPF 14 to V
It is input to C015. When V is 015, an 8fzc clock is generated, which is frequency-divided by the 910 frequency divider circuit 18 to obtain double-speed horizontal synchronization, which is input to the phase comparator 13 through the waveform shaping circuit 20 to form a phase synchronization circuit. .

In this way, when the phase comparator 130 input is normal horizontal synchronization, the changeover switch b33 is switched to pass the frequency divider 19 through the divide-by-2 circuit 19, and when double-speed horizontal synchronization is input, the divide-by-2 circuit 19 is switched. By switching so that the signal does not pass through, double-speed horizontal scanning is always performed using one phase-locked circuit. Although not shown in the figure, a flyback pulse may be used instead of the signal from the waveform shaping circuit 20 in exactly the same manner as described above.

In the above embodiments, VC was described when Le=2, but the same applies to cases where Le is other values.

As described above, the present invention generates double-speed horizontal synchronization using one phase synchronization circuit regardless of whether normal horizontal synchronization or double-speed horizontal synchronization is input as an input signal, and performs double-speed horizontal scanning. Therefore, even if normal horizontal synchronization is input as an input signal, the phase error response is the same as when double-speed horizontal synchronization is input, and it is possible to significantly improve the response compared to the conventional method.

〔Effect of the invention〕

According to the present invention, even when switching between a standard signal and a double-speed signal as an input signal, the horizontal synchronization phase synchronization circuit can be configured in one stage, so the same phase error response can be obtained, and the normal signal is input When this is done, the effect is that the phase error response is significantly improved.

Furthermore, since there is only one phase-locked circuit, there is an effect that the circuit configuration, adjustment, etc. can be simplified.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram of a double-speed horizontal AFC circuit, FIG. 3 is a block diagram of a double-speed conversion circuit, and FIG. 4 is a line measurement operation in the double-speed conversion circuit. FIG. 5 is a block diagram of a double-speed horizontal AFC circuit as another embodiment, FIG. 6 is a block diagram showing a conventional example, FIG. 7 is a block diagram showing FIG. 6 in more detail, and FIG. FIG. 8 is an explanatory diagram showing a television screen in which phase error responses are compared. 1... Normal video signal input terminal, 2... Normal RGB signal input terminal, 3... Double speed RGB signal input terminal, 4... Demodulation circuit, 5... Synchronization separation circuit, 6
...Horizontal synchronization frequency divider circuit, 7...Double speed conversion circuit, 8...Video output circuit, 9
... Double speed AF, C circuit, 10... Vertical deflection circuit,
・13... Phase comparator, 14... LPF,
15, Vco, 16...8 fsc clock, 17...4 fzc clock, 18...9
10 frequency divider circuit, 19...2 frequency divider circuit, 20... Double speed horizontal-synchronization generation circuit, 21... Horizontal drive circuit, 22... Double speed horizontal output circuit, 23... Horizontal deflection yoke, 24...Flyback transformer, 25...High voltage limiting circuit. , - Representative Patent Attorney Katsuo Ogawa - / Figure 2 Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] 1. Using a memory circuit that stores a signal over one horizontal period of an input normal first video signal and reads it out at n times the speed at which it was stored (n is an integer of 2 or more). , a signal converting means for converting a first video signal into a video signal having a horizontal period of 1/n, and a second video signal having a horizontal period of 1/n with respect to the video signal converted by the signal converting means. means for receiving an input video signal and switching between the two, and displaying the video signal selected by the switching means;
a horizontal deflection circuit having an n-fold horizontal scanning frequency; a terminal for inputting a synchronization signal related to the first video signal; and a terminal for inputting a synchronization signal related to the second video signal; It consists of an input terminal, a switch for selecting one of these signals, and a phase synchronization circuit connected to the switch, and is characterized in that an n-times horizontal synchronization signal is obtained as the output of the phase synchronization circuit. An n-times scan television receiver. 2. When a normal signal synchronization signal is selected, the switch directs the synchronization signal to the phase synchronization circuit;
A patent claim characterized in that when a synchronizing signal of the second signal is selected, the synchronizing signal is supplied to a frequency dividing circuit that divides the frequency by n, and the output of the frequency dividing circuit is guided to the phase synchronized circuit. The n-times scan television receiver according to item 1. 3. The switch directs a synchronization signal related to the first and second video signals to a phase synchronization circuit, and the phase synchronization circuit includes a phase comparator and a low-pass filter connected to the phase comparator. , a voltage-controlled oscillator whose oscillation frequency is controlled by the output of the filter, and a frequency divider that divides the output of the oscillator and leads it to the phase comparator, and converts the output of the oscillator into a synchronizing signal selected by the switch. depending on,
2. The n-times scan television receiver according to claim 1, further comprising another switch for changing the frequency division ratio of the frequency divider. 4. The writing and reading clocks of the memory circuit used in the signal conversion means, and the n-times horizontal synchronization for control are generated within the phase synchronization circuit. and an n-times scan television receiver according to any one of Item 3.