JPS63186360A - Multi-cpu device - Google Patents

Abstract

PURPOSE:To improve the processing capacity of a multi-CPU device by securing such a mechanism where an information processing unit of a transmitter side gives an access to a proper input/output address area allocated to the information processing unit of a receiver side and delivers directly a communication request. CONSTITUTION:The information processing unit 1A of the transmitter side gives an access to a proper input/output address area allocated to an information unit 1B of the receiver side and delivers directly a data communication request. Then the unit 1A writes an address signal into a memory means 13 in the unit 1B to inform the communication request even when the unit 1B is set under an interruption inhibiting state in order to process its own task. In addition, plural address signals can be recorded and stored in such a state where these signals can be successively read out in their writing order since the means 13 has an FIFO form. Thus the communication requests can be properly accepted and the processing capacity of a multi-CPU device is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application This invention relates to a multi-CPU device that operates a plurality of CPUs in parallel.

Conventional technology In recent years, multi-CPU devices that operate multiple CPUs in parallel to enhance processing functions have been attracting attention. This multi-CPU device is a type of device that exchanges data such as commands between multiple CPUs. A conventional multi-CPU device of this type is one shown in Fig. 3, in which each CPU is operated in parallel while cooperating with each other by performing data communication. 60-231251) 0 First, the multi-CPU device shown in the same figure is
Multiple information processing units sharing bus 6) 5A, 5B,
Each of the information processing units 5A, 5B, . . .
In addition to the CPU 51, which is a general-purpose information processing device, there is also a local memory 52, a bus requester 53, and an interrupt! J7 ESTA and Nordora 54 are provided.

The CPU 51 is capable of operating independently within the unit while using the local memory 52. Bus requester 53 issues a signal requesting permission to use system bus 6 based on processing by CPU 51. The interrupt requester and handler 54 sends interrupt requests to others and receives interrupt requests to itself.

The system bus 6 includes address signal lines, data signal lines,
and control signal lines. Control signal lines include input/output control signal lines, interrupt signal lines, and bus arpitation signal lines (
In this case, the number of interrupt signal lines is large enough for at least one system of each information processing unit to be individually occupied by each information processing unit.

A bus management device 7 and a system memory 8 are connected to the system bus 6.

The bus management device 7 is equipped with a contention adjustment function called a bus arbiter, and adjusts the bus use permission requests issued from the plurality of information processing units 5A, 5B, . . . Permission to use the bus is granted to only one information processing unit.

The system memory 8 includes each information processing unit 5A, 5B.
,... has a storage area that can be shared.

Next, the operation will be explained.

For example, when an information processing unit 5A sends data such as a command to another information processing unit 5B, first, the unit 5A, which is the source of the data, issues a request for permission to use the bus. This bus use permission request is accepted by the bus management device 7. If the system bus 6 is free, the bus management device 7 sends the message to the sending unit 5.
Give permission to A to use the bus.

The source unit 5A, which has been granted permission to use the bus, uses the system bus 6 to transfer data to be transmitted to the destination unit 5B to the system memory 8 at high speed. As soon as these transmission procedures are completed, the source unit 5A hands over the system bus 6.

Thereafter, the destination unit 5A interrupts the destination unit 5B. This interrupt is performed via an interrupt signal line individually assigned to the unit 5B.

The destination unit 5B that has been interrupted analyzes the cause of the interrupt, and if it determines that the cause of the interrupt is a data communication request, it disables interrupts to ignore future interrupts. After processing, a bus use permission request is issued to the bus management device 7. Bus management device 7 that received this usage permission request
As described above, after confirming that the system bus 6 is free, it grants permission to the destination unit 1-5B to use the bus.

The destination unit 5B, which has been granted permission to use the bus, accesses the system memory 8 using the system bus 6t.
The transmission data transferred by the destination UNISO 5A is transferred to its own local memory 52 at high speed. When this transfer is completed, the destination unit 5B releases the system bus 6 and independently performs processing based on the data transferred to its local memory 52 from the unit 5A. When the processing is completed, the destination unit 5B releases the interrupt prohibition for its own CPU 51 and prepares to accept the next interrupt.

As described above, data such as commands can be transmitted relatively quickly between multiple CPUs that can each operate independently.
Processing functions are now being strengthened by operating PUs in parallel.

Problems to be Solved by the Invention However, according to such a configuration, a communication request to a data destination is made by an interrupt via an individual interrupt signal line provided for each CPU, so a multi-CPU device is not configured. The number of CPU0s is limited by the number of interrupt signal lines. For this reason, in this type of multi-CPU device, the CPU0 cannot be easily added, and there is a problem in that the degree of freedom in functional expansion is low.

Further, when each CPU 51 in a multi-CPU device independently processes a task given to it, it is often necessary to avoid interrupting the processing due to an interrupt. In such cases, it is necessary to disable interrupts in advance so that interrupt requests from others can be ignored. However, if the CPU is disabled,
The CPU that is in the interrupt-disabled state will no longer be able to accept data communication requests.
There are many cases where data communication requests are not accepted and are placed in a waiting state until interrupt permission is granted, and this is one of the factors that hinders the improvement of the processing power of multi-CPU devices. There was a problem.

The above problem arises for the following reasons. In other words, since the means for specifying the data transmission destination CPU is dependent on individual interrupt signal lines, the number of CPUs that can be operated in parallel while cooperating with each other as a multi-CPU device is limited by the number of CPUs that can be operated in parallel. It is limited to the number of signal lines. Additionally, since the configuration uses interrupts to request data communication to the destination CPU, if the destination CPU disables interrupts in order to process its own task, this interrupt prohibition is canceled. Until this happens, it is not possible to notify the destination CPU of the presence or absence of a communication request.

This invention was made in view of the above problems, and
Multi-CPU that increases the flexibility of functional expansion by adding more PUs, and enables data communication requests to be accepted at any time regardless of the operating status of the CPU, improving processing capacity.
The purpose is to provide equipment.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides a plurality of information processing units each having a CPU that can operate independently, and an information processing unit shared by the plurality of information processing units. a system bus shared by the plurality of information processing units via the system bus; A unique input/output address area is assigned to each information processing unit. Furthermore, each information processing unit has the above system/
Address detection means for determining whether or not the address signal output to the bus is a signal specifying a unique address area allocated to the bus; It is equipped with a FiFo format (first-in, first-out format) storage means for storing data in a state that can be read continuously, and an interrupt generation means for interrupting the CPU in the unit based on the address signal stored in this storage means. It is something that

Effect of the Invention With the above-described configuration, the present invention allows the source information processing unit to simply access the unique input/output address area assigned to the destination information processing unit.
Data communication requests can be made directly to the destination unit.

This makes it possible to arbitrarily specify the information processing unit as the data transmission destination without relying on individual interrupt signal lines.

Furthermore, even if the destination unit is in an interrupt-disabled state to process its own task, the source information processing unit does not wait for the interrupt-disabled state to be canceled.
An address signal indicating a communication request can be written into storage means within the destination unit. This avoids the waste of repeatedly issuing data communication requests, making it possible to further improve processing performance.

Furthermore, since the storage means is a FiFo type storage means, a plurality of address signals can be sequentially stored and accumulated in a state where they can be output one after another in the order in which they are written. Therefore, even when a plurality of communication requests are concentrated on one information processing unit, the plurality of communication requests can be accepted at any time and processed in order.

As described above, the degree of freedom in functional expansion by adding a CPU is increased, and data communication requests can be added at any time regardless of the operating status of the CPU, making it possible to improve processing capacity.

Embodiment FIGS. 1 and 2 show a schematic configuration of a multi-CPU device according to an embodiment of the present invention. In this case, FIG. 1 shows the main part, and FIG. 2 shows the overall outline.

First, as shown in the overall outline in FIG. 2, a multi-CPU device according to an embodiment of the present invention has a plurality of information processing units IA, IB, IC, . . . . These plural information processing units (IA, IB, IC9, etc.) share the same system bus 2.

System bus 2 includes address signal lines and control signal lines. The control signal lines include input/output control signal lines, bus arbitration signal lines, interrupt signal lines, and the like.

The system bus 2 includes an information processing unit LA,
In addition to the IB, IC, . . . , a bus management device 3 and a system memory 4 are connected.

The bus management device 3 is equipped with a bus arbitration function and a priority encoder (priority order setting means), and handles bus usage permission requests issued from each information processing unit IA, IB, IC, . The system makes adjustments and grants permission to use the bus to one designated information processing unit according to a priority order determined by a predetermined method.

The system memory 4 includes each information processing unit IA, IB
, IC, . . . have a storage area that can be shared.

Next, as partially shown in FIG. 2, each of the information processing units LA, IB, IC, . A format storage means 13, an interrupt generation means 14, a bus contention avoidance means 15, a bus requester 16, etc. are built in.

The CPU 11 is provided in each unit so as to be able to operate independently.

Address detection means 12 constantly detects whether the address signal on system bus 2 is a signal specifying a unique address area assigned to its own information processing unit. This address detection means 12 includes a digital comparator 1
2a and a digital setting switch 12b. The digital comparator 12a constantly compares whether a part of the address signal (data on the upper digit side) outputted to the system bus 2 matches the setting data of the digital setting switch 12b. The output when both data match becomes the detection output of the address detection means 12. The digital setting switch 12b is used to set a type of code data (+O, $1, . . . , +n) for identifying the information processing unit, and the setting is performed for each information processing unit.

The FiFo format storage means 13 is, for example, a multi-stage shift
It consists of a RAM that is indirectly addressed by a register or a stack pointer. This F
The iFo format storage means 13 is the address detection means 1
2 detects a specific address area set by the setting switch 12b, and when an input/output control signal is detected, the address signal at the time of this detection is taken from the system bus 2 and stored in a readable state in the writing order. ·accumulate. At this time, the storage means 13 stores part of the data of the address signal. Further, the address signal stored in the storage means 13 is read by the CPU II in the unit at any time.

The interrupt generating means 14 operates when an address signal is stored in the storage means 13, and interrupts the CPU in the unit based on the stored address signal.

The bus contention avoidance means 15 also has a kind of arbitration function, and performs monitoring and control operations to avoid contention on the system bus 2.

The bus requester 16 issues a bus usage permission request based on the processing of the CPU 11.

Next, the operation will be explained.

For example, when the information processing unit LA transmits data such as a command to another information processing unit IB, first, the unit IA, which is the data transmission source, issues a bus usage permission request. This bus use permission request is accepted by the bus management device 3. If the system bus 2 is free, the bus management device 3 transmits the message to the sending unit I.
Give permission to A to use the bus.

7) The sending unit LA, which has received permission to use the bus, uses the system bus 2 to send information to the destination information processing unit IB.
The data to be sent to the system memory 8 is transferred at high speed. At the same time, an address signal specifying a unique address area allocated to the destination unit IB,
The address signal output at this time is a code (+1) that specifies the unique address area assigned to the destination unit IB, and a code (+1) that specifies the unique address area assigned to the destination unit IB, and a code (+1) that specifies the unique address area assigned to the destination unit IB. It is made up of a code (+0) that specifies the assigned unique address area. As soon as these transmission procedures are completed, the source unit IA hands over the system bus 2.

On the other hand, when the destination information processing unit IB detects the input/output control signal and the address signal specifying the unique address area assigned to itself from the system bus 2, A part of the data is imported and stored in its own storage means 13. This storage operation is performed unconditionally regardless of whether or not the own CPU II is in an interrupt disabled state. Further, the storage operation is performed any number of times within the storage capacity of the storage means 13, and the information is stored and accumulated in a readable manner in the writing order.

In this way, when the address signal including the specific address area assigned to the self is stored, the interrupt generating means 14 in the Enin 1-IB is activated based on this storage.
Issue an interrupt request to PUII. As a result, the CPU 11 in the destination unit IB accepts interrupts from the interrupt generating means 14 when its own task processing is finished and interrupts are disabled. The CPU 1l in the destination unit IB stores the address signal that caused the interrupt in the storage means 13.
, and determines whether the cause of the interrupt is a communication request and whether the source of the data is unit IA. After that, after disabling the CPU II, a bus usage permission request is issued to the bus management device 3.Q The bus management device 3, which received this usage permission request, confirms that the system bus 2 is free, as described above. After confirming that
The destination unit IB that has been granted permission to use the bus uses the system bus 2.
The system, system memo IJ4t- is accessed using , and the transmission data transferred by the destination unit IA is transferred at high speed into its own unit. After this, the destination unit (IB)
The system bus 2 is released and processing based on the data transferred to the unit IA is independently executed. Then, when the process is finished, the CP
Release the UII interrupt prohibition. At this time, if an address signal indicating yet another communication request is stored in the storage means 13, the series of operations described above is resumed based on this stored address signal.

As described above, in the multi-CPU device of the embodiment described above, the information processing unit IA of the transmission source accesses the unique input/output address area assigned to the information processing unit IB of the transmission destination. Data communication requests can be made directly to the unit. This makes it possible to arbitrarily specify the information processing unit IB as the data transmission destination without relying on individual interrupt signal lines.

Furthermore, even if the transmission destination unit IB is in an interrupt-disabled state in order to process its own task, the transmission source information processing unit IA does not wait for the interrupt prohibition to be released. An address signal indicating a communication request can be written into the storage means 13 in the destination unit IB. This avoids the waste of repeatedly issuing data communication requests, making it possible to further improve processing performance.

Furthermore, since the storage means 13 is a FiFO type storage means, it is possible to sequentially store and accumulate a plurality of address signals in a state where they can be output one after another in the order in which they were written. Therefore, even when a plurality of communication requests are concentrated on one information processing unit, the plurality of communication requests can be accepted at any time and processed in order.

As described above, the degree of freedom in functional expansion is increased by adding a CPU, and data communication requests can be accepted at any time regardless of the operating status of the CPU, thereby improving processing capacity.

Effects of the Invention As is clear from the above explanation, this invention
The configuration allows data communication requests to be made using address signals output to the system bus, rather than relying on interrupts via individual interrupt signal lines, increasing the degree of freedom in functional expansion by adding CPUs. Communication request is from CPU
This has the effect that requests can be made at any time regardless of the operating status of the system, making it possible to further improve processing capacity.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a schematic configuration of main parts of a multi-CPU device according to an embodiment of the present invention, FIG. 2 is a block diagram showing a schematic structure of the entire main part including the above-mentioned main parts, and FIG. FIG. 2 is a block diagram showing a schematic configuration of a CPU device. IA, IB, IC... Information processing unit 2... System bus, 3... Bus tube WUi! , 4... System memory, 12... Address detection means, 13...
- FiFo format storage means, 14... interrupt generation means. Name of agent: Patent attorney Toshio Nakao and one other person Figure 1

Claims (1)

[Claims] It includes a plurality of information processing units each equipped with a CPU (central processing unit) that can operate independently, and address signal lines, data signal lines, and various control signal lines, which are shared by the plurality of information processing units. system·
A bus, a bus management device that adjusts contention on the system bus and grants one information processing unit permission to use the bus, and the plurality of information processing units that control the system bus.
and a system memory shared via a bus, and each information processing unit determines whether the address signal output to the system bus is a signal specifying a unique address area assigned to itself. an address detection means for always detecting the address signal; a first-in, first-out storage means for storing the address signals detected by the address detection means in a state where they can be output one after another in the order in which they are written; and an address signal stored in the storage means. A multi-CPU device having an interrupt generating means that interrupts a CPU in the unit based on.