KR100199033B1 - A multi-interrupt control device and method using compromised type on pci bus - Google Patents

Abstract

The present invention relates to a multi-interrupt control device and a method for a compromise PCI bus for handling interrupts between a system and a host system to be connected to the PCI bus, difficulty in interrupt processing in the prior art, and other systems In order to solve the problems such as the limitation of the use of interrupts and the inability to handle the highest priority interrupt resource through the PCI bus, the present invention provides a method for a host system to allocate a plurality of interrupt resources in a system connected to the PCI bus. It is proposed to handle interrupts in order of occurrence, priority, and user-set priority.

Description

Multiple Interrupt Control Units and Methods for an Affordable PCI Bus

The present invention relates to a multiple interrupt control apparatus and method for a compromise PCI bus for handling interrupts between a system and a host system to be used in connection with a PCI bus.

Conventionally, a single interrupt is satisfied in a system connected to a PCI bus, but due to the miniaturization of the chip and the multifunction of the system, there are many interrupt resources in the system connected to the host bus. (Starvation) occurs, it is difficult to accommodate the needs of the flexible priority interrupt processing, and the problem of placing a lot of restrictions on the performance and use of the system, such as causing an interrupt collision when used simultaneously with other systems. In addition, if any interrupt resources in the system need to be processed first, they cannot be processed through the PCI bus.

The present invention provides a system for processing a plurality of interrupt resources in a system connected to a PCI bus through an interrupt line of one of the PCI buses so that the host system can process the interrupts according to the order of occurrence, priority, and the highest priority designated by the host. It is to efficiently manage interrupts from local interrupt resources in the queue and flags so that interrupt processing of local interrupt resources in the system can be processed according to the order of occurrence, priority and priority without starvation.

1 is a block diagram showing the present invention and the peripheral relationship functional block.

2 is a block diagram of a multiple interrupt controller for a compromise PCI bus of the present invention.

3 is a control flowchart of an interrupt detector according to the present invention.

4 is a control flowchart of an interrupt queue controller according to the present invention.

5 is a control flowchart of an interrupt queue input / output controller according to the present invention.

6 is a high priority interrupt designation flow chart.

* Explanation of symbols for main parts of the drawings

410: highest priority interrupt register 420: interrupt detector

430: highest priority flag 440: interrupt flag

450: interrupt queue controller 451: queue counter

460: interrupt queue 470: interrupt queue input and output controller

480: Priority Encoder

Multi-interrupt control for a compromised PCI bus of the present invention for achieving the above object, interrupt from the interrupt detector to process a plurality of interrupt resources in the system from one host connected to the PCI bus through one interrupt line of the PCI bus Detecting and setting an interrupt flag, determining an interrupt priority from the flag state, requesting a queue input from the interrupt queue controller, and acknowledging the reset flag; Setting interrupt information in the interrupt queue, incrementing the queue counter, confirming the queue input upon receiving a queue input request, and shifting the interrupt queue to the right and decreasing the queue counter upon receiving a queue shift request; If the queue flag of the interrupt queue is set and checked, the host requests an interrupt and receives interrupt information from the host, transmits it, and requests a queue shift. Also, if the host is requested to designate the highest priority interrupt, this is the highest priority. And registering the information in the interrupt register and registering the information in the interrupt detector.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram showing the configuration of the present invention and the peripheral function block, and shows a system for a PCI bus that is to be connected to the host system 100 and the PCI bus 110.

The system for the PCI bus is an essential element, which is composed of a PCI bus master / slave controller 200 that is responsible for data transfer over the PCI bus, and a PCI bus configuration register 300 that stores the configuration of the PCI bus. And it shows the connection state with the multiple interrupt controller 400 for the PCI bus according to the present invention.

The multi-interrupt controller 400 for the PCI bus receives local interrupts from the plurality of local interrupt resources 500 and is responsible for processing to deliver the interrupts to the host system 100 connected through the PCI bus 110. An interrupt line through the PCI bus 110 is directly connected to the multiple interrupt controller 400 and the host system 100.

The queue output request from the host system 100 indicates that it will be delivered to the multiple interrupt controller 400 via the PCI bus master / slave controller 200 which is an integral part of the system for the PCI bus.

2 is an internal block diagram of the multi-interrupt controller 400 for the compromised PCI bus of the present invention, which is largely an interrupt detector 420, an interrupt flag 440, a priority determiner 480, and an interrupt queue controller 450. ), A queue counter 451, an interrupt queue 460, an interrupt queue input / output controller 470, a highest priority interrupt register 410, and a highest priority flag 430.

The highest priority interrupt is assigned to the highest priority interrupt register 410 from the host system 100, and the highest priority interrupt register 410 transmits the highest priority interrupt information to the interrupt detector 420.

The interrupt detector 420 detects interrupts from local interrupt resources (1, 2, 3, ..., n), and then compares the detected interrupts with the highest priority interrupt information. Set 425 the highest priority flag 430, otherwise set 425 the corresponding interrupt flag 440, and queue the interrupt queue controller 450 to write interrupt information to the interrupt queue 460. Make a request 426. At this time, if multiple interrupts are detected at the same time, the priority among the multiple detected interrupts is determined by the priority encoder 480, and the queue input request 426 to the interrupt queue controller 450 sequentially according to the priority. In response to the queue input confirmation signal 427 from the interrupt queue controller 450, the operation of resetting the flag 425 is repeated as many as the interrupt request detection number.

The interrupt queue controller 450 receives the queue input request 426 from the interrupt detector 420 and the queue shift request 471 from the interrupt queue input / output controller 470 to control the interrupt queue 460. A cue counter 451 is provided for addressing. When a queue input request 426 from the interrupt detector 420 arrives, it enters the interrupt queue 460 corresponding to the current queue counter 451 value, increments the queue counter, and then queues the interrupt detector 420. Sending the acknowledgment 427 completes the queue input 452. When a queue shift request 471 from the interrupt queue input / output controller 470 arrives, the interrupt queue 460 is shifted to the right and the queue counter 451 is moved. It performs the function of reducing.

In addition, the interrupt queue input / output controller 470 searches for the highest priority flag 430 and the interrupt queue flag 461 indicating whether the interrupt queue 460 is valid, and generates an interrupt signal to the host if it is set. When interrupt information is received from the host system 100 after an interrupt is generated, the first priority flag 430 is checked for validity, and if it is valid, the contents of the highest priority interrupt register 410 are selected and output to the host system 100. Otherwise, the 0th queue of the interrupt queue 460 is transmitted to the host system 100 through the PCI bus 110, and the queue shift request 471 is performed by the interrupt queue controller 450.

The control flow according to the present invention is divided into the control flow of the interrupt detector, the control flow of the interrupt queue controller, and the input / output control flow of the interrupt queue, and the description of each is as follows.

3 is a detection flowchart of an interrupt detector.

In the start state, it is repeatedly checked whether an interrupt is detected (S1), and if an interrupt is detected, the detected interrupt is compared with the highest priority interrupt (S2), and if it is the highest priority interrupt, the highest priority flag is set (S3). Branch to the state.

If it is not the highest priority interrupt, it is first checked whether there is more than one interrupt detected (S4), and if there is one detected interrupt, the corresponding flag is set (S6), the interrupt is encoded (S7), and the interrupt queue controller 450 is executed. In step S8, a queue input request is made. When the queue input confirmation signal 427 is received while checking the queue input confirmation from the interrupt queue controller 450 (S9), the corresponding flag is reset and branches to the start state (S10).

However, if one or more interrupts are detected (S4), the priority encoder 480 encodes the detected interrupts (S11), and then a queue input request (S12) is made to the interrupt queue controller 450, followed by an interrupt queue controller. Checking the cue input confirmation 427 from the 450 (S13) and receiving the cue input confirmation signal 427 resets the corresponding flag (S14), until all the detected interrupts are sequentially input to the interrupt queue. The process is repeatedly performed (S15).

4 is a flowchart for controlling an interrupt queue, and is a flowchart for managing an interrupt queue by receiving input from an interrupt detector and an interrupt queue input / output controller.

In the start state, it is checked whether there is a queue shift request 471 from the interrupt queue I / O controller 470 (S16). If there is a queue shift request, the interrupt queue is shifted to the right (S17), the queue counter is decremented by one (S18), and branched to the start state. If there is no queue shift request, the interrupt detector 420 checks whether there is a queue input request 426 (S19), and if not, branches to the initial state. If there is a queue shift request, it reads the count value from the queue counter 451 to check if the queue is empty and if the queue is empty, interrupts the queue 460 from the priority encoder 480 to the queue according to this value. Information is controlled to be written (S21), the queue counter 451 is incremented by one (S22), the cue input confirmation signal 427 is sent to the interrupt detector 420, and then branches to the initial state.

5 is a flowchart of input / output control of an interrupt queue.

In the start state, the interrupt queue I / O controller 470 first checks whether the highest priority flag 430 is set (S23), and if it is set, generates an interrupt signal to the host (S24) and receives an interrupt information request from the host (S25). Interrupt information is read from the highest priority interrupt register and transmitted to the host (S26), and the highest priority flag is reset (S27) and then branches to the start state.

On the other hand, if the highest priority flag is not set and is set by checking the interrupt queue flag 461 (S28), if an interrupt signal is generated to the host (S29) and an interrupt information request is received from the host (S30), the interrupt queue 460 The interrupt information is read and transmitted to the host (S31), and a queue shift request (S32) is made to the interrupt queue controller.

6 is a flow chart that designates the highest priority interrupt from the host.

If the host is requested to designate the highest priority interrupt (S33), it is registered in the highest priority interrupt register 410 (S34), and this information is registered in the interrupt detector 420 (S35).

As described above, the present invention processes a plurality of interrupt resources in a system connected to a PCI bus through one interrupt line of the PCI bus, thereby facilitating the use of a host system because other systems can use interrupt convenience and limited interrupt resources. Can be enhanced.

In addition, interrupts are processed in the order of interrupt occurrence and priority interrupts are processed first, so it is easy to process multimedia and efficient use of system resources. In particular, the highest priority interrupts can be assigned by the host. It is easy for multimedia processing, and the queue flag can be used to reduce the number of accesses with the host.

Claims (6)

A highest priority interrupt storage means for storing and delivering the highest priority interrupt information specified in the host system for processing a host system connected to the PCI bus and a plurality of local interrupt resources in the system as one interrupt line of the PCI bus; The flag is controlled by comparing the delivered highest priority interrupt information with the interrupt information detected from the plurality of local interrupt resources, requesting a queue input according to the interrupt priority, and receiving a queue input confirmation signal to receive the corresponding flag. Interrupt detecting means for controlling; An interrupt flag and a highest priority flag indicating a plurality of interrupt states according to flag control of the interrupt detection means; Priority determining means for determining the priority of the plurality of input interrupt information according to the enable signal of the interrupt detecting means; Interrupt queue control means for receiving an queue input request signal and a queue shift request signal to control an interrupt queue; An interrupt queue inputted according to the control of the interrupt queue control means and outputted according to a priority determined by the priority determining means; And checking an valid state of the interrupt queue, generating an interrupt signal to a host system, receiving an interrupt information request signal from the host system, and selecting the contents of the highest priority interrupt storage means to the host system when the priority flag is valid. And an interrupt queue input / output control means for outputting and sending interrupt information data to a host system through a PCI bus when not valid, and for performing a queue shift request. 2. The multiple interrupt control apparatus for a compromise PCI bus according to claim 1, wherein said priority determining means uses an encoder. The queue of claim 1, wherein the interrupt queue control means increases in response to a queue input request signal from the interrupt detection means to address the queue, and decreases in response to this queue shift request signal from the interrupt queue input / output control means. Multiple interrupt control device for a compromise PCI bus, characterized in that it comprises a counter. The apparatus of claim 1, wherein the interrupt queue has a queue flag indicating whether the interrupt queue is valid. Interrupt detector, interrupt queue controller, highest priority interrupt register, and interrupt queue I / O controller, from the interrupt detector to handle multiple interrupt resources in the host and system connected to the PCI bus through one interrupt line of the PCI bus. A first step of detecting an interrupt, setting an interrupt flag, determining an interrupt priority from the flag state, requesting a queue input from an interrupt queue controller, and acknowledging the interrupt flag to reset the interrupt flag; A second step of setting interrupt information in an interrupt queue, increasing a queue counter, confirming a queue input when receiving the queue input request, shifting the interrupt queue to the right and decreasing the queue counter upon receiving a queue shift request; And a third process of requesting an interrupt from the host when the queue flag of the interrupt queue is set and transmitting interrupt and requesting a queue shift when the interrupt information is requested from the host. 6. The method of claim 5, wherein the first process includes registering the highest priority interrupt designation in the highest priority interrupt register upon receiving a request from the host and registering the information in an interrupt detector. Multiple interrupt control methods for the PCI bus.