JPS6316931B2 - - Google Patents

Info

Publication number
JPS6316931B2
JPS6316931B2 JP13101379A JP13101379A JPS6316931B2 JP S6316931 B2 JPS6316931 B2 JP S6316931B2 JP 13101379 A JP13101379 A JP 13101379A JP 13101379 A JP13101379 A JP 13101379A JP S6316931 B2 JPS6316931 B2 JP S6316931B2
Authority
JP
Japan
Prior art keywords
signal
variable
equalizer
adjustment
obtaining
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP13101379A
Other languages
Japanese (ja)
Other versions
JPS5654131A (en
Inventor
Fumio Akashi
Tooru Koyama
Masaru Yamaguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP13101379A priority Critical patent/JPS5654131A/en
Publication of JPS5654131A publication Critical patent/JPS5654131A/en
Publication of JPS6316931B2 publication Critical patent/JPS6316931B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006Arrangements for removing intersymbol interference
    • H04L25/03012Arrangements for removing intersymbol interference operating in the time domain
    • H04L25/03019Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
    • H04L25/03057Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception with a recursive structure

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
  • Filters That Use Time-Delay Elements (AREA)

Description

【発明の詳細な説明】 本発明はデータ伝送における自動等化器に関
し、特に歪の大きな伝送路に対する自動等化器の
引き込みに関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an automatic equalizer in data transmission, and more particularly to the use of an automatic equalizer for a transmission line with large distortion.

自動等化器においては通常等化出力を用いた信
号識別の結果を用いて等化出力との識別誤差を求
めそれによつて可変ゲインを調整する。このよう
な方法を用いると伝送路において歪が大きい場合
可変ゲインの初期状態においては信号識別に誤ま
りを発生し誤まつた信号識別を用いて誤まつた可
変ゲインの調整が行なわれ安定に自動等化器を収
束させられない場合が生ずる欠点がある。
In an automatic equalizer, the result of signal discrimination using the equalized output is usually used to find the discrimination error with the equalized output, and the variable gain is adjusted accordingly. When such a method is used, if there is large distortion in the transmission path, an error will occur in signal identification in the initial state of the variable gain, and the incorrect signal identification will be used to adjust the incorrect variable gain automatically and stably. There is a drawback that the equalizer may not be able to converge.

本発明の目的は信号識別を用いない可変ゲイン
の調整方法を与えることにより安定な収束を得ら
れる自動等化器を提供することにある。
An object of the present invention is to provide an automatic equalizer that can obtain stable convergence by providing a variable gain adjustment method that does not use signal discrimination.

歪の大きい伝送路の一例として第1図に示すよ
うに信号が遅延され一定のゲインが加わり、もと
の信号に加え合わされる場合がある。例えばケー
ブル伝送路で途中で分岐したブリツジドタツプが
含まれている場合等がこの例にあたる。この様な
場合、ユニツトパルス応答は第2図の波形図に示
すような2つのピークをもつ応答となり、これを
トランスバーサル型の可変等化器で等化する場合
は、ユニツトパルス応答の中心から各タツプ間隔
分遅延された点でのサンプル値を符号反転してそ
の分だけ進んだ遅延関係にあるタツプに与えるこ
とによりかなり等化される。また判定帰還型の可
変等化器についても同様に帰還タツプの当該位置
にサンプル値を与えることによつて等化される。
このサンプル値の検出手段はその自己相関の当該
遅延時刻の値によつてえられる。すなわち第2図
で示されたユニツトパルス応答をもつ場合受信波
形Ynは Yn=o+Ni=n aiXo-i となる。ただし、aiは送信データ、Xo-iはユニツ
トパルス応答でX0=1とする。またNはユニツ
トパルス応答が影響を及ぼすタイムスロツト数と
する。従つてその自己相関関数Zjはデータajの無
相関性を仮定すると、 Zjoo+j=|j 2|(X-j+X-j+X-j+1+…) となる。XOに比較してX-j(j≠0)が小さいと
すれば、上式はおおよそ|j 2|X-jと表わされ
る。|j 2|は送信データの平均電力であり、あら
かじめ既知の値であるので、この操作によつて
X-jが得られたことになる。従つて−X-jを当該
タツプ、たとえば−X-1であれば、中心から1タ
イムスロツト分離された遅延をもつタツプに設定
することにより、初期状態より、より良い等化状
態が得られる。
As an example of a transmission line with large distortion, as shown in FIG. 1, a signal is delayed, a certain gain is added, and the signal is added to the original signal. For example, this may be the case when a cable transmission path includes a bridged tap that branches off in the middle. In such a case, the unit pulse response becomes a response with two peaks as shown in the waveform diagram in Figure 2. When equalizing this with a transversal type variable equalizer, the unit pulse response becomes a response with two peaks as shown in the waveform diagram in Figure 2. Significant equalization can be achieved by inverting the sign of the sample value at a point delayed by each tap interval and applying it to a tap delayed by that amount. Similarly, the decision feedback type variable equalizer is equalized by applying a sample value to the corresponding position of the feedback tap.
This sample value detection means is obtained by the value of the autocorrelation at the relevant delay time. That is, in the case of having the unit pulse response shown in FIG. 2, the received waveform Yn becomes Yn= o+Ni=n a i X oi . However, a i is the transmission data, X oi is the unit pulse response, and X 0 =1. Also, N is the number of time slots affected by the unit pulse response. Therefore, assuming that data a j is uncorrelated, the autocorrelation function Z j becomes Z j = oo+j = | j 2 | (X -j +X -j +X -j+1 +...) . If X −j (j≠0) is small compared to X O , the above equation can be approximately expressed as | j 2 |X −j . | j 2 | is the average power of the transmitted data and is a known value, so this operation
This means that we have obtained X -j . Therefore, by setting -X -j to the tap in question, for example -X -1 , a better equalization state than the initial state can be obtained by setting -X -j to a tap with a delay separated by one time slot from the center.

本発明は上記原理にもとずき、相関器を用いた
第一の等化手段で、あらかじめ可変等化器の可変
ゲインの大まかな制御を行ない、しかる後に閾値
回路による識別信号を用いた第2の等化手段によ
つてより精密な制御を行なう事を特徴としてい
る。
The present invention is based on the above principle, in which the first equalization means using a correlator roughly controls the variable gain of the variable equalizer in advance, and then the second equalization means uses a discrimination signal from a threshold circuit. It is characterized by more precise control using the second equalization means.

以下図面を用いて本発明の実施例をのべる。 Embodiments of the present invention will be described below using the drawings.

第3図は本発明の一実施例の全体を示すブロツ
ク図である。図において端子1より入来した受信
信号は2つに分岐し、1つは累算器2を介して閾
値回路3に入力し、閾値回路3で識別を受け端子
4に識別信号を出力する。端子4に出力された識
別信号は同時に一信号間隔分の遅延をもつ直列に
接続された2つの遅延素子5,6に入力される。
遅延素子5および6の出力は、それぞれ可変ゲイ
ン7および8を介して累算器2に加え合わされ
る。遅延素子5および6、可変ゲイン7および
8、および累算器2で判定帰還型の可変等化器を
構成している。一方受信信号から分岐されたもう
一方の信号は直列に接続された2つの遅延素子2
4,25に入力されその出力はその遅延素子の
各々の出力は掛算器9および10で掛算され、そ
の出力はそれぞれ積分器11および12に入力さ
れその出力に自己相関の値をうる。積分器11お
よび12の出力は切替え回路13および14へ入
力する。切替え回路13および14の他方への入
力は以下にのべる回路の出力にて与えられる。端
子4に出力された識別信号は同時に減算器15に
て累算器2の出力信号と差し引かれ誤差信号が作
られる。誤差信号は各遅延回路出力の信号とそれ
ぞれ掛算器16および17で掛け合わされ、固定
ゲイン18および19を介して加算器20および
21で可変ゲイン保持回路22および23の出力
と加え合わされ切替え回路13および14に入力
される。切替え回路13および14は初期状態す
なわち、受信信号が到達した時積分器11および
12の出力が選択され、その後予め設定された時
間後、あるいは等化器出力の状態を判定し、等化
の状態が良と判定された後に加算器20および2
1が選択されるように切替えられる。切替え回路
13および14の出力はタツプゲイン保持回路2
2および23を介して調整されたタツプゲインを
可変等化器に供給する。ここで減算器15、掛算
器16および17、固定ゲイン18および19、
加算器20および21で第二の調整手段を構成
し、遅延素子24,25、掛算器9,10および
積分器11,12で相関器である第一の調整手段
を構成している。本実施例においては2タツプの
帰還タツプからなる判定帰還型の可変等化器を構
成しているが、トランスバーサル型の可変等化器
を用いても同様の構成で実現できる。どちらの場
合もタツプ数はより多くとる事が可能である。ま
た第一の調整手段としてここではミーンスクウエ
ア型の修正によつているが、ゼロフオーシング型
の修正あるいはハイブリツド型の修正にても構成
が可能である。
FIG. 3 is a block diagram showing the entire embodiment of the present invention. In the figure, a received signal input from terminal 1 is branched into two, one is input to threshold circuit 3 via accumulator 2, is discriminated by threshold circuit 3, and outputs an identification signal to terminal 4. The identification signal outputted to the terminal 4 is simultaneously inputted to two delay elements 5 and 6 connected in series with a delay of one signal interval.
The outputs of delay elements 5 and 6 are added to accumulator 2 via variable gains 7 and 8, respectively. Delay elements 5 and 6, variable gains 7 and 8, and accumulator 2 constitute a decision feedback type variable equalizer. The other signal branched from the received signal is transmitted through two delay elements 2 connected in series.
The outputs of each of the delay elements are multiplied by multipliers 9 and 10, and the outputs are input to integrators 11 and 12, respectively, to obtain the autocorrelation value at the output. The outputs of integrators 11 and 12 are input to switching circuits 13 and 14. The input to the other of switching circuits 13 and 14 is provided by the output of the circuit described below. The identification signal outputted to the terminal 4 is simultaneously subtracted from the output signal of the accumulator 2 by a subtracter 15 to generate an error signal. The error signal is multiplied by the output signal of each delay circuit in multipliers 16 and 17, respectively, and added to the outputs of variable gain holding circuits 22 and 23 via fixed gains 18 and 19 in adders 20 and 21, and then added to the outputs of variable gain holding circuits 22 and 23, and then added to the outputs of variable gain holding circuits 22 and 23 through fixed gains 18 and 19. 14. The switching circuits 13 and 14 are in an initial state, that is, when the received signal arrives, the outputs of the integrators 11 and 12 are selected, and then after a preset time or by determining the state of the equalizer output and changing the equalization state. adders 20 and 2 after it is determined to be good.
1 is selected. The outputs of the switching circuits 13 and 14 are connected to the tap gain holding circuit 2.
2 and 23 to supply the adjusted tap gain to the variable equalizer. Here, subtractor 15, multipliers 16 and 17, fixed gains 18 and 19,
Adders 20 and 21 constitute a second adjusting means, and delay elements 24, 25, multipliers 9, 10, and integrators 11, 12 constitute a first adjusting means, which is a correlator. In this embodiment, a decision feedback type variable equalizer consisting of two feedback taps is constructed, but a transversal type variable equalizer can also be used with a similar configuration. In either case, it is possible to have a larger number of taps. Furthermore, although mean square type correction is used as the first adjustment means here, it is also possible to use zero focusing type correction or hybrid type correction.

以上のべたごとく本発明は受信信号を用いた第
一の調整手段と、識別信号を用いた第二の調整手
段とを組合わせる事によつて、引込み範囲が広く
かつ高精度な等化を可能とする。特にブリツジド
タツプのついたケーブルの特性のように異なつた
遅延の信号が混在するような伝送路に対して広い
引込み範囲が得られる。
As described above, the present invention enables high-precision equalization with a wide pull-in range by combining the first adjustment means using a received signal and the second adjustment means using an identification signal. shall be. In particular, a wide pull-in range can be obtained for transmission paths where signals with different delays coexist, such as the characteristics of cables with bridged taps.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は伝送路のモデル、第2図はユニツトパ
ルス応答を示す波形図、第3図は本発明の一実施
例を示すブロツク図である。 図において2は累算器、3は識別回路、5,
6,24,25は遅延素子、7,8は可変ゲイ
ン、9,10,16,17は掛算器、11,12
は積分器、13,14は切替え回路、15は減算
器、18,19は固定ゲイン回路、20,21は
加算器、22,23はタツプゲイン保持回路であ
る。
FIG. 1 is a model of a transmission line, FIG. 2 is a waveform diagram showing a unit pulse response, and FIG. 3 is a block diagram showing an embodiment of the present invention. In the figure, 2 is an accumulator, 3 is an identification circuit, 5,
6, 24, 25 are delay elements, 7, 8 are variable gains, 9, 10, 16, 17 are multipliers, 11, 12
1 is an integrator, 13 and 14 are switching circuits, 15 is a subtracter, 18 and 19 are fixed gain circuits, 20 and 21 are adders, and 22 and 23 are tap gain holding circuits.

Claims (1)

【特許請求の範囲】[Claims] 1 データ伝送の受信器において、受信信号が与
えられた伝送路で生じた歪みを補償する判定帰還
型可変等化器と、前記可変等化器出力に接続され
受信信号を識別する閾値回路と、前記受信信号が
与えられ受信信号の自己相関を得る1個以上の相
関器を用いて調整信号を得る第一の調整手段と、
前記閾値回路の入力および出力を用いて前記可変
等化器の可変ゲインを自動的に調整するための調
整信号を得る第二調整手段と、等化の初期段階に
おいて第一の調整手段出力信号を用いて前記可変
等化器の可変ゲインを設定し、しかる後に第二の
調整出力信号に切替え前記可変等化器の可変ゲイ
ンの調整信号を得る切替え回路とを有し伝送路で
生じた歪を補償する自動等化器。
1. In a data transmission receiver, a decision feedback variable equalizer that compensates for distortion occurring in a transmission path to which a received signal is applied; a threshold circuit that is connected to the output of the variable equalizer and identifies a received signal; first adjusting means for obtaining an adjusted signal using one or more correlators to which the received signal is applied and for obtaining an autocorrelation of the received signal;
a second adjustment means for obtaining an adjustment signal for automatically adjusting the variable gain of the variable equalizer using the input and output of the threshold circuit; and a second adjustment means for obtaining an adjustment signal for automatically adjusting the variable gain of the variable equalizer; a switching circuit that uses the variable equalizer to set the variable gain of the variable equalizer, and then switches to a second adjustment output signal to obtain the adjustment signal of the variable gain of the variable equalizer, and eliminates distortion generated in the transmission line. Automatic equalizer to compensate.
JP13101379A 1979-10-11 1979-10-11 Automatic equalizer Granted JPS5654131A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13101379A JPS5654131A (en) 1979-10-11 1979-10-11 Automatic equalizer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13101379A JPS5654131A (en) 1979-10-11 1979-10-11 Automatic equalizer

Publications (2)

Publication Number Publication Date
JPS5654131A JPS5654131A (en) 1981-05-14
JPS6316931B2 true JPS6316931B2 (en) 1988-04-12

Family

ID=15047936

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13101379A Granted JPS5654131A (en) 1979-10-11 1979-10-11 Automatic equalizer

Country Status (1)

Country Link
JP (1) JPS5654131A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2422989A (en) * 2005-02-03 2006-08-09 Agilent Technologies Inc Correlating a received data signal with a time delayed version of the signal to obtain a measurement of inter-symbol interference

Also Published As

Publication number Publication date
JPS5654131A (en) 1981-05-14

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