JPS63182919A - Line equalizing circuit - Google Patents

Abstract

PURPOSE:To attain high speed convergence with high accuracy and a small circuit scale by using an IIR filter circuit whose stability is guaranteed, removing roughly waveform distortion and using an adaptive FIR filter so as to equalize the residual equalization with high accuracy. CONSTITUTION:A signal incoming from the subscriber line is inputted to an input terminal 1 and converted into a digital signal by an A/D conversion circuit 2. This signal selects the filtering coefficient of a coefficient control circuit 3 for the IIR filtering circuit in response to the level of the input signal to decide the equalizing characteristic of the IIR filter circuit 4. Then the inputted signal is subjected to rough equalization in the IIR filtering circuit 4. Then the signal is equalized with high accuracy by the FIR filtering circuit coefficient control circuit 5 and the adaptive FIR filtering circuit 6 to remove the attenuation distortion and phase distortion, and the result is outputted from an output terminal 7. Thus, the equalization is subjected to stable high speed conversion with high accuracy by a few number of times of operation processings.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a pulse transmission line for suppressing transmission distortion in subscriber lines of different line types and subscriber lines in which bridge taps are present. Regarding equalization circuits.

[Prior art]

In pulse transmission, in order to compensate for waveform distortion due to loss in the transmission line, equipment installed at the middle or end of the transmission line uses line equalization to amplify the distortion caused by the transmission line into the desired waveform for pulse identification. circuit is required.

As such a circuit, an f equalization circuit made of an RC active filter or an SCF filter has been used.
In recent years, advances in digital technology have made digital processing possible.

When this line equalization circuit is constructed using digital processing technology, due to its characteristics, IIR (Infinite
e Impulse Re5ponse) filter circuit and FIR (Finite Impulse Re5ponse) filter circuit
nse) filter circuit is used.

By the way, since the IIR filter circuit has a pole in the transfer function, the impulse response becomes infinitely long, and it is possible to achieve the same equalization ability with a smaller number of taps compared to the FIR filter circuit. This makes adaptive control of filter coefficients difficult.

Furthermore, it is difficult to ensure tap stability under various line conditions using only this IIR filter circuit, and it is unclear whether equalization is possible or not. Furthermore, using only an IIR filter whose filter coefficients are stored in a ROM or the like, it is difficult to deal with various line conditions, and highly accurate equalization cannot be performed.

On the other hand, since the FIR filter circuit has a finite impulse response, stable control is possible, but there is a problem in that the equalization ability is reduced. That is, for example, adaptive FIR
When a filter circuit is used, a very large number of taps are required to remove waveform distortion of the line, resulting in an increase in circuit scale and problems in that it takes time for the taps to converge. Furthermore, the equalization ability is also reduced due to control errors of each tap.

An example of the equalization ability of both of the above filter circuits is shown in FIG. In this way, line equalization circuits using conventional IIR filter circuits demonstrate superior equalization ability with fewer calculations compared to line equalization circuits using FIR filter circuits. In order to use the filter as an equalizer circuit, it is difficult to adaptively control the filter coefficients as described above.

[Purpose of the invention]

An object of the present invention is to use both an IIR filter circuit and an adaptive FIR filter circuit to perform highly accurate line equalization with a small amount of calculations in a stable manner and with high-speed convergence. be.

[Structure of the invention]

For this purpose, the line equalization circuit of the present invention includes a circuit for A/D converting the received signal, and a circuit for A/D converting the received signal in the pulse transmission line.
an IIR filter circuit that receives the output of the D conversion circuit;
An IIR having a memory circuit for storing filter coefficients for the IR circuit and a control circuit for addressing the memory circuit according to the level of a received signal, and controlling the IIR filter circuit.
The present invention is configured to include a filter circuit coefficient control circuit and an adaptive FIR filter circuit that receives the output of the IIR filter circuit.

〔Example〕

Examples of the present invention will be described below. In this example, waveform distortion is roughly removed using an IIR filter circuit whose stability is guaranteed, and the equalization residual is further removed using an adaptive FIR filter circuit.
A filter circuit is used to achieve highly accurate equalization.

In FIG. 1, a signal arriving from a subscriber line is input to an input terminal 1, and is converted into a digital signal by an A/D conversion circuit 2. In FIG. This signal is set to II depending on the level of the input signal.
The filter coefficients of the R filter circuit coefficient control circuit 3 are selected to determine the equalization characteristics of the IIR filter circuit 4. Then, the input signal is roughly equalized in this TIR filter circuit 4. Thereafter, the signal is highly accurately equalized by the FIR filter coefficient control circuit 5 and the adaptive FIR filter circuit 6 to remove attenuation distortion and phase distortion, and is output from the output terminal 7.

FIG. 2 is a detailed circuit diagram of the main part of the circuit shown in FIG. 1. IIR filter circuit 4 is delay circuit 40.41
, addition circuits 42-45, and multiplication circuits 46-49. Also, the coefficient control circuit 3 for the IIR filter circuit is R
It is composed of an OM control circuit 30 and a ROM circuit 31.

Further, the adaptive FTP filter circuit 6 includes delay circuits 60 to 62.
, addition circuits 64 and 65, and multiplication circuits 66 to 68.

In the subscriber line transmission system to which the equalization circuit of this embodiment is assumed to be applied, since it is used at a relatively high bit rate, the circuit configuration of the multiplier circuit is the most difficult, and it is difficult to reduce the number of multiplier circuits. required.

Regarding this point, in the circuit shown in FIG. 2, the IIR filter circuit 4 with a small number of multiplications is
It is stably controlled by the coefficient control circuit 3 for the IR filter circuit, and the equalization residue is highly accurately equalized by the adaptive FIR filter circuit 6.

In this way, in this embodiment, the IIR filter circuit, which has a problem with circuit stability in adaptive control, is controlled by a coefficient control circuit having a ROM in which stable coefficients have been written in advance, and the equalization residual is controlled by the adaptive FIR type. Since the configuration is equalized by a filter circuit, the wide variable gain width peculiar to subscriber lines is
The gain is controlled by the IR filter circuit, and the average distortion due to the difference in waveform distortion due to different line types is removed by the rlR filter, and furthermore, it is highly accurately equalized by the adaptive FIR filter, so the circuit size is small. High precision and high speed convergence is possible.

〔Effect of the invention〕

As described above, the present invention is characterized in that highly accurate equalization can be stably converged at high speed with fewer calculations than conventional circuits.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a line equalization circuit according to an embodiment of the present invention, Fig. 2 is a circuit diagram embodying the main parts of Fig. 1, and Fig. 3 is a line etc. using an IIR filter circuit, an FIR filter circuit, etc. FIG.

Claims (1)

[Claims] (1) In the pulse transmission line, a circuit that A/D converts the received signal and an IIR that receives the output of the A/D conversion circuit.
a coefficient control circuit for an IIR filter circuit that controls the IIR filter circuit and has a filter circuit, a storage circuit that stores filter coefficients for the IIR circuit, and a control circuit that addresses the storage circuit according to the level of a received signal;
A line equalization circuit comprising: an adaptive FIR filter circuit that receives an output from the IIR filter circuit.