JPS63169141A - Transmission error detection circuit - Google Patents

Abstract

PURPOSE:To directly detect transmission errors from ON/OFF digital signals by comparing an output signal from a delaying/inverting circuit with an original received digital signal at a comparator, and discriminating the periodicity of output signals from this comparator. CONSTITUTION:A received signal is inverted by an inverse logic circuit 1, slightly delayed by a delay circuit 2 in terms of time, and inputted to an AND circuit 3. To the other input terminal of the AND circuit 3, the reception signal is inputted as it is, and the AND condition of both input signals is detected, and an output signal from this AND circuit 3 is transmitted to a monitoring device 4 where its periodicity is discriminated. A digital signal is a signal constituted of a combination of turning on and off, therefore, even if the turning on/off is continued, they maintain the periodicity which is the multiple of integer of basic period. Hence, by monitoring the periodicity of the signals representing the timing of the leading and trailing of received digital signals, the absence of errors can be discriminated when the periodicity is detected and the presence of errors also can be discriminated when the periodicity is irregular.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a digital transmission device, and more particularly to a circuit that detects, on a receiving side, a transmission error in a digital signal sent via a transmission system.

[Conventional technology]

When transmitting digital signals via a transmission system, if the transmission system is long or if there are sources of electromagnetic noise nearby, transmission errors may occur due to waveform distortion or induced noise. So far, countermeasures have been taken using software, such as devising the code format of the signal to be transmitted, such as parity checking.

[Problems to be solved by the invention]

However, software-based countermeasures such as the parity check described above cannot be applied to uncoded signals and have limitations. An object of the present invention is to provide a transmission error detection circuit that can detect transmission errors directly from the on/off digital signal itself without using software, and is also effective for uncoded signals. .

[Means to solve the problem]

The transmission error detection circuit according to the present invention includes a delay/inversion circuit that generates a delayed inverse logic signal of a received digital signal, and a comparison circuit that compares the output signal of the delay/inversion circuit with the original received digital signal. and a circuit for determining periodicity of the output signal of the comparison circuit.

[For production]

By creating a delayed inverse logic signal of the received digital signal in a delay/inversion circuit and comparing this signal with the original received digital signal, a signal representing the rising or falling timing of the received digital signal can be obtained. On the other hand, a digital signal is a signal composed of a combination of on (H: High) and off (L: Low), and even if it continues to be on or off, the period is an integral multiple of the fundamental period. , periodicity is observed. Therefore, by monitoring the periodicity of the signal that represents the rising or falling timing of the received digital signal, it is possible to determine that there is no error if it is periodic, and that there is an error if the periodicity is disturbed. It is possible.

【Example】

In FIG. 1, a signal received through a transmission system or the like is inverted by an inverse logic circuit 1. In FIG. Thereafter, the signal is delayed somewhat by the delay circuit 2 and input to the AND circuit 3. The received signal is input as is to the other input terminal of the AND circuit 3, and the AND condition of these two human input signals is detected. The output signal of this AND circuit 3 is sent to a monitor device 4, and its periodicity is determined. Next, the operation will be explained with reference to the waveform diagram in FIG. First, let's assume that the received signal is as shown in Figure 2 A (note that this signal is a digital signal of H scarecrow, but as a result of being transmitted, it has a distorted waveform as shown in the figure). ). This is inverted by passing through the inverse logic circuit 1 and becomes as shown in FIG. 2B. The signal is then delayed by the delay circuit 2 and becomes as shown in FIG. 2C. The AND condition of the original received signal (Fig. 2A) and the inverted/delayed signal (Fig. 2C) is taken by the AND circuit 3, and when the AND condition is satisfied, the output signal is 2 It occurs as shown in the diagram. Therefore, the output pulse of the AND circuit 3 (FIG. 2D) is generated in response to the rising edge of the received signal, and represents the rising timing. Incidentally, the digital signal transmitted on the transmitting side is composed of repeated on/off cycles, and should basically be periodic even if the on/off cycle continues several times. Therefore, the output pulse from the AND circuit 3 is also periodic in the absence of noise, and is an integral multiple of the time T as shown in the figure. On the other hand, when a noise component is received as shown by the dotted line, an output pulse is generated from the AND circuit 3 in response to the rising edge of this noise component, and the periodicity of this output pulse is disturbed. Therefore, the periodicity of the output pulses of the AND circuit 3 is monitored by the monitor device 4, and when a pulse whose period is not an integral multiple of T appears, it can be determined that a transmission error has occurred. When it is determined that there is a transmission error in this way, the monitor device 4 generates an alarm signal. Note that here, AND circuit 3 is used to detect transmission errors.
The output pulse of this AND circuit 3 can also be used as a timing signal.

【Effect of the invention】

The transmission error detection circuit of the present invention can directly and immediately detect transmission errors from the on/off digital signal itself, regardless of software I/ware. Since transmission errors are detected using a hardware configuration, it is also effective for uncoded signals.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a signal waveform diagram of each part of FIG. 1. 1... Inverse logic circuit, 2... Delay circuit, 3... AN
D circuit, 4...monitor device.

Claims (1)

[Claims] (1) A delay/inversion circuit that generates a delayed inverse logic signal of a received digital signal, and an output signal of the delay/inversion circuit;
a comparison circuit that compares the original received digital signal;
a transmission error detection circuit comprising: a circuit for determining periodicity of an output signal of the comparison circuit;