JPH01149546A - System for correcting data transferring error - Google Patents

Abstract

PURPOSE:To correct a data error at a low cost without reducing transferring rate by immediately comparing data fetched at a receiving side and the data of a transmitting side and re-fetching the data at the receiving side when the error exists. CONSTITUTION:A transmitting side data signal 12 and a register output data signal 13 are compared by a comparing circuit 5 by means of a comparison enable signal 14 in which a data strobe signal 11 is delayed by a delaying circuit 4. When they coincide, a buffer 3 is opened by an EQU signal 15, and the use of the signal 13 is permitted. At the time of a non-coincidence, an error counter 6 is counted up by an ERROR signal 16, and register trigger pulse signal 17 is generated from a pulse generating circuit 9. The signal 12 is re-latched to a register 2 by the signal 17, and the signal 12 is compared with the signal 13 by the circuit 5. At the time of the non-coincidence, the register latch of the signal 12 is repeated until the signal 11 is turned off, and when the signal 11 is turned off, error counting data 13 are reported to the transmitting side.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a data transfer error correction scheme.

[Conventional technology]

Conventionally, errors have been detected or corrected using a parity-1 code correction method.

In addition, related methods of this sustenance include, for example,
There is Japanese Patent Application Laid-Open No. 55-034744.

[Problem that the invention seeks to solve]

In the conventional example described above, the parity method cannot correct errors, and the parity method cannot be used in devices with limited data lines.

In addition, in code correction methods such as Hamming codes, the amount of data transferred increases because the code is sent separately from the data line, a code conversion function and a correction function after error detection are required, which increases costs and reduces the transfer rate required for 1W transmission and reception. There was a problem with the increase in

The present invention provides a low-cost method for correcting data errors in data transfer'f! - aim.

[Means for solving problems]

The purpose of the above is to immediately compare the data captured on the receiving side and the data on the transmitting side, and if there is an error, the data is re-captured on the receiving side. This allows for low cost processing without reducing the transfer rate. Solvable.

[Effect]

In data transfer, by adopting this method, the data signal on the transmitting side and the register signal on the receiving side are compared with each other with a time difference, making it possible to detect data errors caused by noise on the transmitting side data line.

Upon error detection, the data is read in again, making it possible to receive normal data.

However, even if the data is imported again, if the error continues and the sending side has finished the data transfer, the sending side, the cable or Since it is possible to detect a failure somewhere in the receiving register, the location of the failure becomes clear, the failure search becomes easier during troubleshooting, and the reliability of data transfer is significantly improved.

〔Example〕

Hereinafter, one embodiment of the present invention will be explained with reference to the drawings.

The transmitting side data signal 12 is latched into the register 2 with the data strobe signal 11 as a trigger signal.

This transmitting side data signal 12 and register output data signal 1
Comparison circuit 5 performs the comparison of 3.

As the comparison enable signal 14 at this time, a signal obtained by delaying the data strobe signal 11 by the delay circuit 4 is used.

If the transmitting data signal 12 and the register output data signal 13 match, the EQLI signal 15 opens the buffer 2 and allows the register output data signal 13 to be used.

If the transmitting data signal 12 and the register output data signal 13 do not match, the error counter 5 counts up by the LROR signal 16, and the register trigger pulse signal 1 is output from the ROR multiplier 16 and the pulse generator 9.
7 occurs.

This register trigger pulse signal 17 causes the transmitting side data signal 12 to be latched in the register 2 again and compared with the register output data signal 13 in the comparator circuit 5.

At this time, the comparison enable signal 14 uses a ratio signal obtained by delaying the register trigger pulse signal 17 in the delay circuit 4.

If they do not match, the register latching of the transmitting side data signal 12 is repeated until the data strobe signal 11 is turned off.

If the data strobe signal 11 is turned off in a mismatched state, error count data 13 is reported to the transmitting side.

〔Effect of the invention〕

According to the present invention, error detection and correction can be easily performed at low cost in data transmission, and the reliability of data transfer is significantly improved.

[Brief explanation of the drawing]

The figure is a block diagram showing an embodiment of the present invention. ...
Error counter, 7...AND circuit, 8...Inversion circuit, 9...Pulse generation circuit, 10...AND circuit.

Claims (1)

[Claims] 1. During data transfer, during the period when the strobe signal indicating data transmission from the transmitting side is being sent, the receiving side takes it into the register and compares the register output and the transmitting side data with a time difference, resulting in errors. A data transfer error correction method that detects and corrects errors during data transfer by re-capturing the data into the register on the receiving side if there is an error.