JPS63153634A - Data processor - Google Patents

Abstract

PURPOSE:To easily speed up the processing of a processor without argely altering its design large even if some of its internal circuits is slow in operation speed by extending an internal clock signal when a specific instruction is execut ed. CONSTITUTION:When the specific instruction for which the slowest circuit in the processor needs to operate is fetched in an instruction register 1 and a microinstruction for it is read out of a microprogram control part 2, control signals phi1WE and phi2WE are sent from a decoder 3 for control which decodes the microinstruction to a clock generator 5. Therefore, internal clock signals phi1 and phi2 are extended only when the specific instruction is executed, and three cycles of a clock CLK whose one cycle normally corresponds to one machine cycle are regarded as one machine cycle, so that the instruction is executed. Consequently, the frequency of a reference clock can be increased as much as possible according to the speed of circuits except the slowest circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing technology and a technology that is particularly effective when applied to a synchronization method inside a data processing device, such as formation of an internal clock in a microprocessor. Concerning effective techniques that can be used in this method.

[Prior Art] A microprocessor has an internal oscillation circuit or receives a clock signal from the outside, divides the clock signal appropriately to form an internal clock signal, and synchronizes with this internal clock signal. The internal circuit is operated by Therefore, the higher the frequency of the internal clock signal, the faster the microprocessor operates.

[Problems to be solved by the invention] However, the frequency of the internal clock signal of a microprocessor is regulated by the slowest circuit inside the processor, that is, by the hardware. In some cases, the advantage of high speed could not be fully utilized.

Furthermore, when developing a microprocessor, the maximum operating frequency is first determined, and each circuit may be designed and processes selected to operate at that frequency. In that case, each circuit is designed to all operate in one clock cycle. Therefore, when developing a new product with higher functionality or faster speed of such a microprocessor,
So that each circuit operates in one clock cycle,
The disadvantage was that all the circuits inside the processor had to be redesigned.

Furthermore, as a conventional technique similar to the present invention, when a certain microprocessor accesses a peripheral device that operates slower than the microprocessor, the clock cycle, that is, the machine cycle, is extended, thereby making it possible to configure a system using low-speed devices. There is a technology that does this (for example, the 8-bit microprocessor HD6809 manufactured by Hitachi, Ltd.).

However, the traditional clock stretching method.

A dedicated external terminal (MRDY on HD6809)
When a signal indicating that it was a low-speed device was input from a peripheral device to a terminal), the microprocessor recognized it and stretched the clock ([Hitachi, Ltd., September 1982, rsEMIcOND
(See UcTERDATA BOOK, 8/16-bit Microcomputer, pp. 484-485). In other words, the conventional clock stretching method is: 1. It is not designed in consideration of the difference in operating speed between each circuit inside the processor.

An object of the present invention is to provide an internal synchronization method that can easily increase the speed of a microprocessor without making major design changes, even if some of the internal circuits of the microprocessor include slow operating speed circuits. There is a particular thing.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

In other words, focusing on the fact that the slowest circuit inside a processor often operates when a specific instruction is executed, for example, based on the signal output from the instruction decoder, The clock generator is configured to stretch the internal clock signal only when the

[Operation] According to the above-mentioned means, when the slowest circuit inside the processor is operated, other circuits that operate faster than this operate slowly in accordance with the slower circuit, so that the circuit is not restricted to the slow circuit. It has become possible to select and operate at a high frequency without any problems, and even if some of the internal circuits have slow operating speeds, the above purpose of speeding up the processor without major design changes has been achieved. can be achieved.

[Embodiment] FIG. 1 shows an embodiment in which the present invention is applied to a microprocessor.

The microprocessor of this embodiment includes an instruction register 1.0 that holds instructions read from external program memory. A microprogram control unit 2 in which a microprogram consisting of a group of microinstructions corresponding to the instructions held in the instruction register 1 is stored. a control decoder 3 that decodes microinstructions read from the control unit to form control signals inside the processor; an execution unit 4 that includes an ALU (arithmetic logic unit) and various register groups;
The processor internal clock signals φ0 . It is comprised of a clock generator 5 that forms the signal φ2, an interrupt control circuit 6 that controls interrupts, a path control circuit 7 that forms bus control signals, and the like.

In this embodiment, when a specific instruction that is necessary to operate the slowest circuit inside the processor is fetched into the instruction register 1, and the corresponding microinstruction is read out from the microprogram control unit 2, The control decoder 3 for decoding microinstructions is configured to send control signals φ, WE, φ, WE to the clock generator 5.

As a result, the microprocessor of this embodiment uses the internal clock signal φ only when executing a specific instruction.
□, φ2 is stretched and 1 Normally, 1 cycle corresponds to 1 machine cycle, but 3 cycles of clock CLK becomes 1
The instruction is executed as a machine cycle.

FIG. 2 shows a reference clock CLK and control signals φ, WE, φ, WE, which are input to the lock generator 5 as shown in FIG. 1, and internal clock signals φ1 . The timing relationship of φ2 is shown. In the figure, the symbols FF, FF are set/reset type flip-flops.

That is, the clock generator 5 of this embodiment generates an internal clock signal φ when a certain specific instruction is executed.
The control signal φ from the control decoder 3 is synchronized with the rising edge of 2.
, WE are changed to high level. Then, the output signals φ and W of the flip-flop FF are changed to high level, and this state is maintained until the next rise of the reference clock CLK.

As a result, the high level of internal clock signal φ1 becomes
It is extended by one cycle of clock CLK. Also,
At this time, while φ1 is at high level, NAND gate G2
Since the output of φ is fixed at low level, the low level period of clock φ2 is extended by one cycle of clock CLK, and φ.

The clock φ2 is changed to high level in synchronization with the falling edge of the clock φ2.

On the other hand, in response to the control signals φ and WE, the control decoder 3 supplies the clock generator 5 with control signals φ and WE that are changed to high level with a delay of half a cycle. The control signals φ and WE are maintained at a high level until the next rising edge of the reference clock CLK.

Therefore, the output signals φ and W of the flip-flop FF are
It is changed to a high level in synchronization with the rising edge of clock φ8 delayed by one cycle. Then, the clock φ2 set to high level is stretched by one cycle of clock CLK, and then changed to low level in synchronization with the rise of clock CLK. Also, at this time, since the output of the NAND gate G□ is fixed at a low level while the clock φ2 is at a high level, the low level period of the clock φ1 is extended by one cycle of the clock CLK, and synchronized with the falling edge of φ2. Thus, in the above embodiment, the machine cycle is extended to three times the normal machine cycle only when a certain specific instruction is executed. Therefore, even if the frequency of the reference clock CLK is made as high as possible in accordance with the speed of the circuits inside the processor except for the slowest circuit, three cycles are sufficient to execute an instruction for operating the slow circuit. Moreover, the instructions that operate such slow circuits are often special instructions that are executed infrequently, so by increasing the frequency of the reference clock CLK,
The overall operating speed of the processor will be significantly faster.

Note that in the above embodiment, when a certain specific instruction is issued, the internal clock signal φ1. The control signals φ1WE and φ2WE supplied to the clock generator 5 in order to extend φ are both outputted from the control decoder 3.
Of these, the control signal φ2WE is the control signal φ2WE.
, WE and the clock φ2 may be generated within the clock generator 5.

Further, in the above embodiment, the machine cycle is extended to three times the normal cycle when a specific instruction is executed, but it may be extended to twice or four times or more.

As explained above, in the above embodiment, the clock generator is configured to stretch the internal clock signal only when a certain specific instruction is executed, so when the slowest circuit inside the processor is operated, other The faster circuits are now operated more slowly to match the slower circuits, allowing the processor to operate at a higher frequency without being restricted by the slower circuits. Even if some of the processors have slow-operating circuits, the processor can be easily made faster without major design changes.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the above example,
Internal clock signals φ0. However, the processor itself may have an oscillation circuit, and the internal clocks φ□ and φ2 may be formed based on a reference clock obtained by frequency-dividing the oscillation signal. Formed clock φ
1. φ is not only supplied to the internal circuit, but also
It may also be output externally.

Furthermore, the control unit 2 in the embodiment may be a random logic type control unit.

In the above explanation, the invention made by the present inventor was mainly applied to microprocessors, which is the background application field, but the invention is not limited thereto, and the invention is not limited to single-chip microcomputers or other program-controlled devices. It can be used in general data processing devices of this type.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

In other words, even if some of the internal circuits of a microprocessor have slow operating speeds, when the slowest circuit within the processor is operated, other faster operating circuits will slow down to match the slower circuits. This allows the processor to operate at a higher frequency without being constrained by slower circuits, making it easier to speed up the processor without major design changes. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention applied to a microprocessor, and FIG. 2 is a timing chart showing an example of the timing of input/output signals of the clock generator. 2...Microprogram control unit, 3...Control decoder, 4...Execution unit, 5...Clock generator, CLK...Reference clock, φ1
．． φ2...Synchronization signal (internal clock signal). Figure 2 f2, ゛

Claims (1)

[Scope of Claims] 1. When a specific instruction is executed in a program control type data processing device that is equipped with a signal forming circuit that forms a synchronization signal inside the device and sequentially captures and executes instructions constituting a program. A data processing device characterized in that a period of a synchronization signal outputted from the signal forming circuit is longer than a normal period. 2. A microprogram control system control unit is provided, and a control signal that extends the cycle of the synchronization signal output from the signal forming circuit when a specific instruction is executed is a microprogram control unit that corresponds to the specific instruction. 2. The data processing device according to claim 1, wherein the data processing device is formed by a decoder that decodes instructions.