JPS63142445A - Memory device - Google Patents

Abstract

PURPOSE:To quickly access data by constituting a memory device so that data are successively and continuously accessed if the length of one data group, the length between data groups, the length of all of data, and the address of the first data are designated once. CONSTITUTION:The address is set to a memory address register 2 through a selector 5, and the data length is set to a data length register 8 through a selector 17, and the block length is set to a block length register 12 through a selector 11, and the increment address is set to an increment address register 15. Data of the length designated by the block length register 12 are continuously accessed when the block access mode is designated, and data of the length designated by the block length register 12 are continuously accessed again from the address position separated from the end address of said access by the value held in the increment address register 15 when said access is terminated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to data groups or blocks arranged in multiple rows at constant address intervals within a memory area.

The present invention relates to a memory device that can be accessed continuously.

[Conventional technology]

FIG. 6 is shown in 1, for example, Electronic Computers/Systems and Mechanisms (written by Eng. Flores, translated and supervised by Hideo Aiso, published by Shinyosha). FIG. 1 is a block diagram of a conventional memory device.

In the figure, (1) is a memory cell, 'il>D, (2) is a memory address register indicating which position of f-1 memory cell (1) is to be accessed, and 6D13) is a memory address register of memory cell (1). This is a memory data register that holds data sequentially output from the location specified in (2).

(4) is a memory control device that controls reading or writing to the memory cell (1), memory address register (2), and memory data register (3)K.

FIG. 5 shows a block diagram of the memory device shown in FIG. 6, which has an added function of continuously accessing a group of memory cells of a predetermined length. In the figure (5), use the selector to select the start address of the access or the output of the adder (6).

Generates input to the memory address register. (6) is an adder that adds 1 ft to the contents of the memory address register (2) to calculate the 9th memory address to be accessed. (7) selects the length of the data to be accessed using the selector or the output of the subtractor (9).

Generates input to data length register (8). ]8) is a data length register that holds the remaining data length after the currently accessed data. (9) checks that the subtraction value has become less than O, and notifies the memory control device (4) that access to all data has been completed.

Next, the operation of the memory device shown in FIG. 5 will be explained.

Here, an example of accessing data on the memory cell (1) shown in FIG. 4 will be described. Figure 4 shows four pieces of data starting from address A MOe Ml m M2 p M
The access (read) operation for these items, which indicate S, takes the following steps.

(Step 1) Set address A to memory address register (2) via selector (). Also, the data length (4 in this example) is set in the data length register (8) via the selector (7).

(Step 2) The memory cell specified by the memory address register (2) (
1), extract one piece of data and set it in the data register (3). The contents set in this register (3)K are transferred to the other 9, for example, the central processing unit.

(Step 3 Selector +5) selects the output of the addition Masuda and sets it in the memory address register (2). Here d, present/
% IJ 7 Add 1 to the contents of the dress register (2)jE
do.

Set the address for the next data in the memory address register (2). Also, via the selector (7), the subtractor (
91 is selected and set in the data length register (8). Here, from the contents of the current data length register (8), 1f
:Set the subtracted value to the data length register (8).

At this time, the comparator checks whether the contents of the data length register 18) are less than or equal to O.

If this value is 0 or less, it means that all data has been plotted. If it is larger than the reverse KO, there is still data to be accessed and the process returns to step 2 to read the primary data.

[Problem that the invention seeks to solve]

In the conventional memory device shown in FIG. 5, the data in the memory cell (1) as shown in FIG.
If you try to access in the order of 1 M2 e MS.

Address setting to memory address register (2).

A and M+4 are required twice, and data length register 1B
It is necessary to set the value to + twice, which poses a problem in that the memory access speed decreases.

This invention was made in order to solve the above-mentioned problems, and the memory device according to the invention uses a memory cell (1) as shown in FIG. , a block length register that holds the block length, an incremental address register that holds the address interval between each block, a data length register that holds the total data length to be accessed, etc. As shown in FIG. ．． Incremental address 3. Data length 6. By setting the value of the initial address A and the value of the initial address A once each), data can be accessed consecutively with MO* Ml e M2 e Ml .

[Effect]

In the memory device according to the present invention, when block access mode is specified, data of the length specified by the block length register is accessed continuously, and when this access is completed, the data is held in the incremental address register from the address at the end of the access. Data of the length specified by the block length register is accessed continuously from an address position separated by a value. This operation continues until the value of the data length register becomes 0 or less.

゛FIG. 1 is a block diagram of a memory device according to the present invention! ri, (f) ~ a@ is the 6th. This is similar to the conventional device shown in FIG. In the figure, the selector α11 selects 6D, a preset block length, or the output of the subtractor a3 to generate an input to the block length register r1z.

2 is a block length register that holds the length of the remaining data to be accessed among the data in the block.

A3 is a subtracter that subtracts 1 from the contents of block length register 0 to calculate the remaining data length to be accessed within the block. α4 is a comparator that checks if the contents of the block length register (Iz) is less than or equal to a, and detects that all data in one block has been accessed. Holds the address.116) is a selector while accessing data in the block.

+1 is selected, and when accessing one block of data is completed, the contents of the incremental address register μ9 are selected.

αD is a selector (a).+111: is selected while data in a block is being accessed, and when access to one block of data is completed, the contents of the incremental address register are selected. Here, the subtractor (9) is.

While accessing data in one block, 1 is subtracted from the contents of data length register 1B), and when access to data for one block is completed, data length register 18 is
) is subtracted from the value of the incremental address register tt51. Kasumi uses and gate, block access mode 7
When the lag α scratch is set.

, - the output of the comparator α is transmitted to each selector αDαeαη.

'-'its is block access mode flag 6#)
, Pro2] Specifies the access behavior for each block.

The operation of the memory device according to the present invention configured as shown in FIG. 1 will now be described. The memory continuation operation is performed according to the following steps.

(Step 1 Set block access mode flag 0 on IK to specify access in block units. Address A
memory address register (2) via selector (5)
, the data length is set to the data length register 8) via the selector αη, the block length is set to the block length register r12 via the selector αυ, and the increment address is set to the increment address register tI9.

(Step 2) Memory cell (
From the corresponding position in 1), one piece of data f is generated and set in the data register (3). The contents set in this register (3) are transferred to the other nine, for example, the central processing unit.

(Step 3) Select the output of the adder (6) via the selector (5).

Set to memory address register (2). That is, the output of the subtracter (9) is selected via the current selector (7).

Set to data length register (8). That is, the output (+1) of the selector αη is subtracted from the contents of the current data length register (8), and the length of the remaining data to be accessed is set in the data length register (18). At this time, the comparator α field is
Check whether the contents of the data length register (8) are less than or equal to 0. If this value is less than 0, it means that all data has been read and block data access is terminated. Next, select the location of the subtractor through the selector (111) and set the block length to the register z.In other words, subtract +1t from the contents of the block length register (12) and set the block length to register z. The length of the remaining data to be processed is set in the block length register σ2.

At this time, the comparator a41 checks whether the contents of the block length register α2 are less than or equal to 0. If this value is less than 0, it means that reading of the entire block of data has been completed, and the process goes to step 4 for nine people (if it is not less than 0, it returns to step 2).

(Step 4) When one block of data has been read eM.

The output of the comparator α4 becomes a selection signal to the selector all (lυaη) through the AND GO) 18. That is, the selector Ql
For l, select the block length, set the block length in the block length register (1z again, and select 2 selector αe.
For , select the incremental address register,
The value of the increment address register is added to the memory address register σ2. Further, the selector αη selects the output of the incremental address register 4, and subtracts the contents of the incremental address register μS from the data length register (8). Then jump to step 2.

Now, as an example of actual operation, the memory device shown in FIG.
FIG. 2 shows the states that change in each register when data on the memory cell (1) shown in FIG. 3 is accessed.

The operation in this case is as follows.

(Initial settings...time to) Value A is set to memory address register (2).

A value of 6 is set to the data length register (8), a value of 2 is set to the block length register (1z), and a value of 3 is set to the increment address register a9.

<Reading of data MQ...Time t1> Specified by content A of memory address register (2). Data MO is read from the corresponding position on the memory cell (1) and set in the data register (3). When this read is completed, the value obtained by subtracting 1 from the current block length data is not less than O (and the value obtained by subtracting the output of the 9 selector (Iη (+1 in this case)) from the current data length register 18 is also 0. Since it is not the following, the value A+1, which is the sum of the output (+1 in this case) of the selector (Iυ), is set to the value of the memory address register (2).The block length register 0 and the data length register 18+ are set.

Each current value) is set by subtracting 1 to 1 and 5.

<Reading of data M1...time t2)
Data M1 is read from the corresponding position on the memory cell (1) specified by the content A+1 of the memory address register (2) and set in the data register (3). After this reading is completed, the value obtained by subtracting 1 from the current block length register 03 will be less than 0, so the output of the comparator α will be
18 to the selector συC10αη as a selection signal. The selector α11 selects the block length, the value 2 is reset to the block length register 02, the 9 selector - selects the value 3 of the increment address register (1!9), and the value 3 is set to the memory address register (2). The value A+4, which is the sum of the increment address 3 and the value A+1 of the current memory address register (2), is set. Since this is detected, the secondary data is read.

Data M2 is read out from the corresponding position on the specified memory cell (1) at time t3>content A+4 of the memory address register (2), and data M2 is read out from the corresponding position on the specified memory cell (1), and the data M2 is read out from the data register (3). is set to When this reading is completed, the value obtained by subtracting 1 from the current block length register u2 is not less than 0, and the output of the 2 selector αη from the current data length register (8) (in this case, the value obtained by subtracting +12 from the current data length register (8) is also 0). Since it is not the following, the value A-)-5, which is the sum of the current memory address register (2) value and the output of selector H (+1 in this case), is set in memory address register (2). Also, block length register α2 and data length register 1
8) are set to values 1 and 1, respectively, which are obtained by subtracting 1 from the current value.

<Continuation of data M3...Time t4> Contents of memory address register (2) Data M3 is read from the corresponding position on memory cell (1) specified by A+5, and data M3 is read out from data register (3). is stored in When this reading is completed, the value obtained by subtracting 1 from the current block length register α2 becomes less than 0, so the value 1 of the comparator u41:
subtract; the target value -2 is set. At that point, comparator a detects that this value is less than 0, so it finishes reading out all block data.

In the above embodiment, the P& output operation for the memory device has been described, but the same applies to the write operation.

Furthermore, although a one-dimensional memory device in which one address is given has been described, a two-dimensional memory device in which access is given by one row and column address may also be used.

Furthermore, in the above embodiments, the case where data on a specific memory cell is accessed has been described.

The length of the block, the value of the increment address, the length of the total data, etc. may be set to other arbitrary values with the same effect.

〔Effect of the invention〕

As mentioned above, according to this older brother, when consecutive data groups of a certain number are arranged at a fixed distance apart in memory, the length of one data group is.

The configuration allows for sequential and continuous access by simply specifying the distance between each data group, the length of all data, and the address of the first data once, allowing high-speed data access to the memory device. See the effect.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a memory device according to an embodiment of the present invention, FIG. 2 shows an example of data on the memory cell of FIG. 3, and shows the values of each register when accessed by the memory device of FIG. 1. 3 and 4 are explanatory diagrams showing an example of data on a memory cell to be accessed, and FIGS. 5 and 6 are block diagrams showing an example of a conventional memory device. In the figure, (8) is the data length register, +111 is the selector,
r12 is a block length register, a is a subtractor, and I is a comparator. α9 is an incremental address register, (lGf′i selector, a
η is a selector, (I8 is an and-goo) e (11 is a block access mode flag. In the figure, the same symbol indicates the same or equivalent part. Patent applicant Kozo Iizuka, Director of the Agency of Industrial Science and Technology, Figure 2) 3rd flash Figure 4 Figure 5 Figure 6

Claims (1)

[Claims] Consisting of a memory cell that holds data, a memory address register corresponding to this memory cell, a data register, and a memory control device, it continuously stores data of a predetermined length by giving the start address and data length to be accessed. a block length register for holding the length of one data group; and means for subtracting the value of this register one by one and detecting when the value becomes 0 or less;
an incremental address register that holds an address interval between each data group; means for selecting the value or 1 of the incremental address register when generating a memory address and adding it to the memory address register; and all data to be accessed. a data length register that holds a length; and means for selecting and subtracting the value of the increment address register or 1 from the value of this register to calculate the remaining data length to be accessed;
The block length register includes means for detecting that the value of the data length register becomes 0 or less, and a flag for instructing a block access mode. A memory device characterized in that data having a length specified by a register is sequentially accessed in blocks until the value of the data length register becomes 0 or less.