JPS6286442A - Data processor - Google Patents

Abstract

PURPOSE:To minimize a hardware by recording the low-order 16-bit of an instruction head address just after branching to a trace memory and storing the high/low order 16-bit of the address of the instruction head into the trace memory in case of a 32-bit branch instruction. CONSTITUTION:A PC tracer consists of a jump flag 71, a 32-bit jump flag 72, a trace address counter 73, a memory 74, a 32-bit register 174 storing the content of a program counter, a selector 175 selecting whether low-order 16-bit or high- order 16-bit and a bit 176 reflecting a 32-bit jump flag 72. The level of the 32-bit jump flag reflection bit 176 is 0 at 16-bit jump and 1 at 32-bit jump. Since the storage capacity of a trace memory is decreased without losing effective trace information, the program counter trace device capable of wide range trace is formed without increasing the hardware.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a data processing device, and more particularly to a program counter tracing mechanism suitable for chip LSI implementation.

[Background of the invention]

(]) of the program when depacking the software. Monitoring execution status is often done.

This monitoring includes a method of sequentially storing the contents of the instruction word start address in memory and a method of storing the instruction start address of the branch destination. A known example of the former is HID
ICV90 series instruction language architecture manual 1
Pages 4-19 and 20, as a publicly known example of the latter, JP-A-60
-20251 publication is mentioned.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a data processing device having a program counter trace mechanism that minimizes the amount of hardware while storing effective program counter trace information.

[Summary of the invention]

The inventor discovered that there are two types of branch instructions: 16-bit branches and 32-bit branches. In the case of a 32-bit branch, the upper and lower 16 bits of the program counter are traced, and in the case of a 16-bit branch, the program counter is traced. We focused on the fact that the execution status of a program can be confirmed by tracing the contents of the lower 16 bits of the counter. According to the present invention, it is possible to reduce the trace memory capacity while storing effective trace information.

In the former case, it is possible to know all the execution status of the program, but since an illegal branch is taken, if an error occurs after executing more steps than the trace capacity, it is difficult to investigate the cause. Can not. For this reason,
The trace capacity needs to be increased, which requires a large amount of hardware.

In the latter case, the address where the branch occurred and the start address of the branch destination are recorded, but this is a tracer mechanism that is unrelated to the type of branch instruction, which results in wasted memory and a lot of waste in the hardware configuration. Ta.

When converting a data processing device into an LSI, it is necessary to reduce the number of gates for a secondary function such as a program counter tracer, which is not an original function, due to restrictions on the number of gates. In this case, both the former method and the latter method are inappropriate.

[Embodiments of the invention]

FIG. 1 shows the overall configuration of a data processing apparatus according to the present invention. Each data processing device includes an instruction fetch/decode unit 10 that reads and decodes instructions, an arithmetic control unit 20 that stores control information for each instruction and provides control information 205 to the arithmetic unit 30, and an arithmetic unit 30 that executes arithmetic operations. , a memory 40 for storing instructions and data, a memory interface section 90 for accessing the memory, and a clock generation section 80. The memory interface unit includes a program counter 50 that stores instruction addresses and a memory address register 60 that stores memory access addresses.
and a PC tracer 70 that traces the contents of the program counter, an adder 52 that increments the contents of the program counter, and a selector 51 that selects the jump destination address 504 given from the arithmetic unit 30 and the output 503 of the adder 52. Operand address 206 given from arithmetic unit 30 and output 50 of program counter 50
2 and a selector 61 for selecting.

FIG. 2 shows the configuration of the calculation control section 20. Arithmetic control unit 20
is a control memory 21, a microinstruction register 22, a control memory address register 23, an adder 24 for incrementing the control memory address, and an output 12 of the adder 24.
4 and a selector 25 for selecting the microinstruction start address 204 given from the instruction fetch decoding section 10. When executing a certain instruction, first the microprogram start address of the instruction is received from the instruction fetch decoding unit 10, and thereafter, the address is sequentially incremented and the control information 1 is retrieved from the control memory 21.
Read out 21. One bit of the control information 121 is E
The - bit is assigned to the ND signal 101, and the - bit is assigned to the JMP signal 1.
It is assigned to 02. The END signal signifies the final cycle of the instruction. As shown in Figure 1,
The JMP signal 102 is connected to the selector 51, and when this signal is on, the jump destination address 504 is selected and its contents are set in the program run 50.

FIG. 3 shows the configuration of the PC tracer 70.

The PC tracer 70 includes a jump flag 71, a 32-bit jump flag 72, a trace address counter 73, a memory 74, a 32-bit register 174 that holds the contents of the program counter, and a 32-bit register 174. The bit 176 reflects the 32-bit jump flag 72.

The jump flag 71 indicates that JMP32 is activated when the JMP signal is on.
It is set when the signal is off and the END signal is on, and cleared when the jump flag is on and the END signal is on.

The trace address counter 73 is an up/down counter, and when the JMP signal is on and the JMP32 signal is off,
EN when the END signal is on and the jump flag is on
TRCRD is counted up when the D signal is on, when the JMP32 signal is on and the END signal is on, when the 32-bit jump flag reflection bit 176 is on, and when the JMP32 signal and the END signal are on at the same time. When the signal is on, it will count down. The 32-bit jump flag 72 is set when the JMP32 signal and the END signal are on at the same time, and when the 32-bit jump flag is on, and is cleared when the JMP32 signal and the END signal are on at the same time. The register 174 that holds the contents of the program counter is a register that holds 32 bits of the contents of the program counter, and selects the lower 16 bits of the bit 174 reflected when the 32-bit jump flag is on. At the time of a 32-bit jump, the lower 16 bits of the register 174 are transferred to the memory 74 at the first clock when the 32-bit jump flag is set.
The upper 16 bits of the register 174 are output to the memory 74 at the next clock. The memory 74 is a 16-bit memory to which the output 575 from the selector 175 is connected and a 32-bit jump reflection flag 176 is input at the same time, and is written when the WE signal 780 is on. When the WE double signal, JMP signal is on, JMP32 signal is off and END signal is on, jump flag and END
When the signals are on at the same time, when the JMP32 signal and the END signal are on, the 32-bit jump jump flag reflection bit 176 is O for a 16-bit jump and 1 for a 32-bit jump. .

FIG. 4 shows the contents stored in the trace memory. When there is a 16-bit jump, it is stored as (1) and (3), and when there is a 32-bit jump, it is stored as (2).

〔Effect of the invention〕

According to the present invention, the storage capacity of the trace memory can be reduced without losing effective trace information, so it is possible to construct a program counter trace mechanism capable of tracing over a wide range without increasing the amount of hardware.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a data processing device having a program counter trace mechanism according to an embodiment of the present invention, Fig. 2 is a block diagram of an arithmetic control section, Fig. 3 is a block diagram of a program counter tracer, and Fig. FIG. 3 is a pattern diagram stored in a trace memory. DESCRIPTION OF SYMBOLS 10... Instruction fetch/decode unit, 20... Arithmetic control unit, 30... Arithmetic unit, 40... Memory unit, 50
...Program counter, 60...Memory address register, 70...Program counter tracer, 7
1... Jump flag, 72... 32 bit jump flag, 73... Trace address counter, 74
...Trace memory.

Claims (1)

[Scope of Claims] 1. In a data processing device having a trace memory that stores the contents of a program counter, means for identifying that the currently executed instruction has branched, means for identifying that the instruction that is currently being executed has not branched; By means of identification,
In the case of a 16-bit branch instruction, the lower 16 bits of the instruction start address immediately after the branch are recorded in the trace memory, and in the case of a 32-bit branch instruction, the instruction start immediately after the branch instruction is recorded in both the upper and lower 10 bits of the address. A data processing device characterized in that six bits are stored in a trace memory.