JPH07191879A - Microprocessor provided with executing function of instruction for debugging and debugging method - Google Patents

Abstract

PURPOSE:To easilky recognize the conditions of program execution by surely letting the influence of the execution of a program appear at any arbitrary check point of the program as memory reference outside a chip and observing that operation from the outside of the chip. CONSTITUTION:When an instruction decoded by an instruction decoder 106 is an instruction for debugging, an index number idi (=i) designated by this instruction for debugging is dispatched from the instruction decoder 106 to an instruction operation control part 110 for debugging, and the reading of the instruction is indicated. Based on this idi and the contents of a base register (BR) 109, the memory address of the moving destimation of the instruction, which is replaced by the instruction for debugging, to be originally executed, namely, the leading address of an i-th entry in a table area 201 of a main memory 20 is calculated by the instruction operation control part 110 for debugging, and the instruction to be truely executed from that address is read through a system bus 30, dispatched to the instruction decoder 106 and decoded.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor having a built-in cache memory for holding a part of stored information in a main memory provided outside a chip and having a function of executing a debugging instruction, and a debugging method. Regarding

[0002]

2. Description of the Related Art In recent years, microprocessors generally incorporate a cache memory on the same chip in order to improve the degree of integration with the remarkable progress of semiconductor technology. In such a microprocessor, a main memory (external main memory) provided outside the chip of the processor
If a part of the running program stored in is already loaded into the cache memory via the external bus (system bus) and the instruction to be executed is fetched directly from the cache memory, No operation such as instruction fetch occurs in the main memory).

In such a case, it is not possible to determine how the program is executed, even if the chip (the connection portion with the system bus) is externally observed with a logic analyzer or the like.

[0004]

As described above, in the microprocessor having the cache memory built in the chip, a part of the program being executed which is stored in the main memory provided outside the chip of the microprocessor. Has already been read into the cache memory and the instruction to be executed is directly fetched from the cache memory, no operation such as instruction fetch occurs outside (main memory of) the chip.

For this reason, conventionally, there has been a problem that even if the chip is observed from the outside by a logic analyzer or the like, the execution state of the program cannot be grasped, and it is difficult to debug the program.

The present invention has been made in consideration of the above circumstances, and it is an object of the present invention to make it possible that at any checkpoint of a program, the influence of the execution of the program always appears as a memory reference outside the chip. Accordingly, it is an object of the present invention to provide a microprocessor and a debugging method having a function of executing a debugging instruction, by which the state of program execution can be easily grasped by observing the operation from outside the chip.

[0007]

SUMMARY OF THE INVENTION According to the present invention, a main memory in which an instruction to be executed fetched from the cache memory is provided outside the chip in an instruction decoding means included in a microprocessor having a cache memory built in the chip. In the case of a debug instruction having address information for directly or indirectly designating the upper memory address, a function for instructing to read the instruction of the memory address on the main memory designated by the address information is added. In addition, in response to an instruction read instruction from the instruction decoding means, the instruction at the memory address on the main memory designated by the address information is read as an instruction to be truly executed, and this instruction is given to the decoding means. By providing the instruction operation control means in the microprocessor and executing the debugging instruction, Instruction to be executed true from the memory address of the main memory specified by decree is read into the microprocessor, it is characterized in that it has to be decrypted by the instruction decoding means.

[0008]

In the above structure, when a program is debugged, each instruction stored in the main memory at each check point in the program is replaced with a debugging instruction, and the replaced instruction is replaced with the replaced instruction. , Is moved to each memory address of the main memory which is directly or indirectly designated by the address information in the corresponding debug instruction.

The program in the main memory is executed by the microprocessor. Here, the instruction to be executed by the microprocessor is fetched from the cache memory (when there is a miss in the cache memory, one line of instruction group including the target instruction is transferred from the main memory to the cache memory). And decoded by the instruction decoding means.

Therefore, when the instruction to be executed has already been read into the cache memory, no operation such as instruction fetch occurs outside (on the main memory of) the chip. However, in the above configuration, when the instruction fetched from the cache memory and decoded by the instruction decoding means is a debugging instruction, the instruction decoding means sends the debugging instruction operation control means Since the instruction to read the instruction at the memory address on the main memory specified by the address information is instructed, the main instruction memory outside the chip is accessed by this instruction operation control unit for debugging, and the address information in the above instruction for debugging is directly used. Or, the instruction at the memory address in the main memory that is indirectly designated, that is, the instruction that is replaced with the debugging instruction and moved to the memory address designated by the address information of the debugging instruction is the instruction that should be truly executed. It is loaded into the microprocessor.

As described above, at an arbitrary checkpoint of the program replaced with the debugging instruction, the operation for reading the replaced original instruction from the main memory outside the chip is always performed.

Therefore, by observing the memory referencing operation (referenced memory address) from outside the chip with a logic analyzer or the like, the state of program execution can be easily grasped.

The instruction read in the microprocessor by the debug instruction operation control means is passed to the instruction decoding means, decoded and provided for execution in the same manner as the instruction fetched from the cache memory. .

[0014]

FIG. 1 is a block diagram showing the configuration of an information processing apparatus including a microprocessor according to an embodiment of the present invention, focusing on the internal configuration of the microprocessor. In the figure, 10 is a one-chip microprocessor, 20
Is a main memory provided outside the chip of the microprocessor 1, and 30 is the microprocessor 10 and the main memory 20.
Is the system bus to which is connected. This system bus 3
0 forms an external bus of the microprocessor 10.

The main memory 20 is for storing programs, data and the like. The main memory 20 includes a base register (B
R) 108 starting from a specific memory address (base address) specified by, for example, a table area 201 of 4n bytes
Are secured as needed.

The table area 201 is composed of n entries each of which stores, for example, a 4-byte instruction.
The entry (memory address) in this table area 201 is index number (entry number) id _i (id _i = 0
~ N-1) indirectly specified.

The microprocessor 10 includes a main memory 20.
An instruction cache memory 101 for holding a copy of a part of the program being executed stored in the main memory 2
A data cache memory 102 that holds a part of the data stored in 0, and a bus that controls transfer of instructions / data between the main memory 20 and the instruction cache memory 101 / data cache memory 102 via the system bus 30. Interface 103, bus interface 103, and debug instruction operation control unit 110 described later
Driver 1 provided between the bus and the system bus 30
04 and.

The microprocessor 10 also has an instruction buffer 105 for holding an instruction read from the instruction cache memory 101, and an operation code (OP code) of the instruction held in the instruction buffer 105.
It has an instruction decoder 106 that decodes the processing content designated by the instruction based on the above, and a register file 107 that holds operand data.

The instruction decoder 106 decodes instructions and
A necessary operand is read from the register file 107 (for example, in the case of a branch instruction, an operand necessary for calculating a branch address is read).

The instruction decoder 106 also includes a main memory 20.
When the debugging instruction having the index field in which the index number id _i for indirectly designating the entry (memory address) in the table area 201 is decoded, the debugging instruction operation control unit 110 is read. The 4-byte instruction at the memory address on the main memory 20 indirectly designated by the index number id _i is instructed to be read.

The microprocessor 10 further executes the instructed operation, load / store with the data cache memory 102, etc. according to the instruction decoding result of the instruction decoder 106, and stores the resulting operand data in the register file 10.
7 and so on, a base register (BR) 109 for holding the top memory address (with the base address) of the table area 201 on the main memory 20 used by the debug instruction, and designation of the debug instruction Instruction operation control section 11 for controlling the operation to be performed
It has 0 and.

The instruction operation control unit for debugging 110, in accordance with the instruction read instruction according to the result of decoding the instruction for debugging from the instruction decoder 105, includes the index number id _i in the instruction and the content (BR) of the base register 109.
System bus 3 using the memory address calculated based on
The main memory 20 is accessed via 0, and the instruction stored in the entry in the table area 201 starting from the memory address is read. The read instruction is passed to the instruction decoder 106.

Next, the operation of the configuration of FIG. 1 will be described. now,
It is assumed that a program 202 to be debugged is stored in the main memory 20 as shown in FIG. If an instruction 203 (such as a branch instruction) at the checkpoint location CP _{i in} the program 202 is to be fetched and executed, the instruction sequence including the instruction 203 has already been read into the instruction cache memory 101. If so, the instruction 203 is fetched at high speed from the instruction cache memory 101, not from the main memory 20, and sent to the instruction decoder 106 via the instruction buffer 105. Then, the instruction 203 is decoded by the instruction decoder 106, and is executed by the instruction execution unit 108 according to the decoded result.

When the instruction 203 at the location CP _i , which is the checkpoint for program debugging, is already read in the instruction cache memory 101 and the instruction 203 is executed, the instruction 203 is executed.
Are fetched from the instruction cache memory 101, and no instruction fetch operation (with respect to the main memory 20) appears outside the chip of the microprocessor 10, that is, on the system bus 30. In this case, even if the chip (and the connection portion with the system bus 30) is externally observed with a logic analyzer or the like,
The execution status of the program cannot be grasped.

Therefore, in the present embodiment, when the program 202 is to be debugged, the instruction 203 at the location CP _i which should be a checkpoint in the program 202 is set as shown in FIG.
As shown in (b), the index number id _i (= i)
Is replaced with the debug instruction 204 having an index field in which is set as the debug target program 212. Further, the table area 201 is secured in the main memory 20, and the index number id _i (= i) in the index field of the debug instruction 204 is secured.
In the i-th entry that is indirectly specified by
The replaced instruction 203 is transferred as shown in FIG.

Although only one instruction is the target of the operation in the figure, the same operation is actually performed for any n instructions. In addition, the base register (B
By executing a load instruction designating R) 109 as a destination register, the start address (BR) of the table area 201 is set in the base register (BR) 109.

After the above processing, the debug target program 212 stored in the main memory 20 as shown in FIG. 2B is executed. Now, in the execution state of this program 212, an instruction string including the newly set debugging instruction 204 (in place of the instruction 203) is already in the instruction cache memory 101 at the check point CP _i in the program 212. It is assumed to be loaded in.

In this state, when the instruction at the location CP _i (debugging instruction 204) is to be fetched and executed,
The instruction (debugging instruction 204) is fetched at high speed from the instruction cache memory 101, not from the main memory 20, and is sent to the instruction decoder 106 via the instruction buffer 105.

The instruction decoder 106 includes an instruction buffer 10.
Operation code (OP
Decode the processing content designated by the instruction based on the code). Then, the instruction decoder 106 determines that the instruction to be decoded is a debug instruction (here, the debug instruction 2
In the case of 04), the operation of the instruction execution unit 108 is interrupted,
An instruction read instruction (for reading the instruction 203 to be executed, which is replaced with the debugging instruction 204) is issued to the debugging instruction operation control unit 110. At this time, the instruction decoder 106 uses the index number (entry number) id _i set in the index field of the debug instruction 204 as the debug instruction operation control unit 1.
Pass to 10.

When the instruction operation control unit 110 for debugging receives an instruction read instruction from the instruction decoder 106, the index number (entry number) i passed together with the instruction read instruction.
Based on d _i and the contents (BR) of the base register 109, that is, the head memory address (base address) of the table area 201 on the main memory 20, the following expression PA = (BR) + id _i * 4 ... The operation (1) is performed to calculate the memory address (physical address) PA of the entry in the table area 201 on the main memory 20, which is indirectly designated by the index number id _i (= i). It should be noted that "4" in the above equation (1) indicates the byte length (entry size) of the instruction word.

Next, the debug instruction operation control unit 110
Based on the calculated memory address (physical address) PA, that is, (BR) + id _i * 4, via the bus driver 104 and the system bus 30 (microprocessor 10
The main memory 20 (provided outside the chip) is accessed, and an instruction having a length of 4 bytes starting from the memory address, that is, a checkpoint location CP _i , is stored in the main memory 20 with id _i (= i The instruction 203 transferred to the) th entry is fetched as an instruction to be truly executed.

As described above, the instruction 203 at the checkpoint location CP _i in the program 202 is replaced with the debugging instruction 204 (the program 212), and the replaced instruction 203 to be executed is replaced with the debugging instruction. By moving to the entry in the table area 201 specified by the index number id _i set in the index field of 204, that is, the id _i (= i) th entry, the debug instruction 204 is transferred from the instruction cache memory. Instruction decoder 1 taken out
When decoded in 06, the instruction 2 transferred to the id _i (= i) th entry in this table area 201
The operation for reading 03 from the main memory 20 is always performed by the debug instruction operation control unit 110.

Therefore, by observing the memory access operation (the memory address to be accessed) from outside the chip with a logic analyzer or the like, the state of program execution can be easily grasped.

Now, the debug instruction operation control unit 110
Is a debug instruction 2 in response to an instruction read instruction from the instruction decoder 106 according to the debug instruction 204.
When the instruction 203 replaced by 04 is fetched as an instruction to be truly executed, this instruction 203 is read by the instruction decoder 10
Send to 6.

Then, the instruction decoder 106 outputs the instruction 203 sent from the debugging instruction operation control unit 110,
Various control signals necessary for decoding and executing the processing specified by the instruction 203 are decoded in the same manner as when they are read from the instruction cache memory 101, that is, in the same manner as when an instruction is read in the normal procedure. It is output to the instruction execution unit 108 and the like. If the instruction 203 is a branch instruction, the instruction decoder 106 reads the operand required for calculating the branch address from the register file 107 and outputs it to the instruction execution unit 108.

The instruction execution unit 108 includes an instruction decoder 106.
In accordance with the control signal from, the process specified by the instruction 203 (if the instruction 203 is a branch instruction, the branch processing to the branch destination instruction according to the branch destination address) is executed.

In the above embodiment, the debug instruction 2
Although the destination of the instruction replaced with 04 is indirectly specified by the debug instruction 204, it may be directly specified. However, in the case of the direct designation method, since the position of the table area 201 is fixed, the degree of freedom becomes poor.

Further, in the above-mentioned embodiment, the case where the cache memory built in the microprocessor 10 is the two kinds of the instruction cache memory 101 for holding the instruction and the data cache memory 102 for holding the data is explained. It may be a cache memory that holds data.

[0039]

As described above in detail, according to the present invention,
The instruction decoding means of the microprocessor is a debugging instruction that has address information for directly or indirectly designating a memory address on the external main memory so that the instruction to be executed fetched from the cache memory built in the microprocessor. In some cases, in addition to the function of instructing the reading of the instruction at the memory address on the main memory designated by the address information, it is designated by the address information according to the instruction reading instruction from the instruction decoding means. The instruction address control means for debugging for reading the instruction at the memory address on the main memory as the instruction to be truly executed and giving it to the instruction decoding means for decoding is provided from the cache memory for debugging. If the instruction is read and decoded, be sure to specify it with the relevant debugging instruction. Since the operation of loading that instruction from the external main memory is carried out, how the program execution by observing its operation from outside the chip logic analyzer or the like can be easily grasped.

Further, the instruction at the place to be the checkpoint in the program is replaced with the debugging instruction, and the replaced instruction is moved to the memory address of the main memory directly or indirectly designated by the debugging instruction. As a result, the above checkpoint always causes an operation that refers to the main memory, and the instruction that should have been executed, which has been replaced by the instruction for debugging, is read into the microprocessor and decoded / executed. Trace can be done.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an information processing apparatus including a microprocessor according to an embodiment of the present invention, focusing on the internal configuration of the microprocessor.

FIG. 2 is a diagram for explaining a method of using a debugging instruction in the embodiment.

[Explanation of symbols]

10 ... Microprocessor, 20 ... Main memory, 30 ... System bus, 101 ... Instruction cache memory, 103 ...
Bus interface 106 ... Instruction decoder 108 ...
Instruction execution unit, 109 ... Base register (BR), 110
... debug instruction operation control unit, 201 ... table area,
202, 212 ... Program, 203 ... Instruction (instruction at place to be checkpoint), 204 ... Debugging instruction.

Claims (2)

[Claims] 1. A microprocessor having, on a chip, a cache memory that holds a copy of part of information stored in a main memory provided outside the chip, and executes an instruction to be executed fetched from the cache memory. The instruction decoding means for decoding, if the instruction is a debug instruction having address information for directly or indirectly designating the memory address of the instruction to be truly executed in the main memory, the address Instruction decoding means for instructing reading of an instruction at a memory address on the main memory specified by information; and the instruction information directly or indirectly specified by the address information according to the instruction reading instruction from the instruction decoding means. The instruction at the memory address on the main memory is read as the instruction to be truly executed, and is given to the instruction decoding means. By executing the debug instruction, the instruction to be truly executed is read from the memory address of the main memory specified by the instruction into the microprocessor. A microprocessor characterized by being decoded by the instruction decoding means. 2. An instruction at a place to be a checkpoint in a program stored in a main memory is replaced with a debugging instruction having address information for directly or indirectly designating a memory address on the main memory. A cache memory in which the replaced instruction is moved to a memory address specified by the address information of the debug instruction, the main memory is used as an external memory, and a part of the stored information in the memory is held. In a microprocessor with a built-in chip on the chip, when the instruction to be executed fetched from the cache memory is the debugging instruction, a memory address on the main memory specified by the address information in the debugging instruction. Read and decode the command as the command that should be truly executed
A debugging method characterized in that a program execution status can be observed from outside the chip by executing the program.