JPS6282724A - Redundancy suppression coding system - Google Patents

Abstract

PURPOSE:To suppress the redundancy of a binary signal with high efficiency by combining the rearrangement depending on bit interleave and the extended run length depending on the extraction of a changing point. CONSTITUTION:The pre-processing section 1 for a run length coding section 2 applying, e.g., the MH coding consists of a bit interleave reconstitution section 3 rearranging a binary picture data 4 by a prescribed period of bit interleave and obtaining a binary signal string 5 and a change point extracting section 6 converting the logical change and no-change of the binary signal string 5 rearranged further as a new binary value into a binary signal string 13. The run length coding section 2 uses a '0' run '1' run sharing section 7 so as to share the binary signal string 13 into '0' run and '1' run and run length coding sections 8, 9 apply run length coding to them respectively. Thus, the '1' run length is shortened and the '0' run length is lengthened to give expectation to high compression of the coding processing.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a redundancy suppression coding method for suppressing the redundancy of a binary signal such as a z-valued image signal [Prior art] ] In the redundancy suppression coding method for binary signals such as z-value image signals, it is necessary to obtain a signal sequence with greater bias in statistical properties than the original binary signal sequence, and to A major challenge is to obtain a high compression ratio by simply encoding the signal sequence. This is because in a signal sequence with large statistical bias, the length of consecutive sequences having the same logical value becomes longer, so if run-length encoding is performed, for example, so-called entropy is reduced and an extremely high compression ratio can be obtained.

However, encoding methods in the field of image communications, especially facsimile communications, such as MH (Modified Huffman) encoding, MR (Modified READ) encoding, and MMR (Modified, Modified READ) encoding recommended by CCITT, are Not only facsimile,
It is well known that these encoding methods are also used for electronic files, etc., but these encoding methods focus on the fact that there are many "white" runs in document information such as characters, and are used to encode such image signals. This is based on the premise of transmission. On the other hand, in addition to general document images, binary images such as halftone images such as photographs may be pseudo halftone images that are binarized using a dither method or the like. However, since the pseudo-halftone image produces gradation using the area gradation method, the printed dots ("black") will be dispersed due to its nature. In other words, the pseudo-intermediate-length image has an increased r-run length, which is shorter than the original halftone image.
This is inconvenient for encoding.

This situation is illustrated in Figure 2 (a), (b) and Figure 3 (a), (
This will be explained using b). The matrices of FIGS. 2(a) and 2(b) represent threshold matrices, particularly dot-concentrated dither matrices.

The solid line in FIG. 3 (5L) represents the threshold change in the first column in FIG. A pseudo-halftone image signal having a discrete distribution as shown in b) is obtained. If "white" and "black" become disjointed in this way, the compression rate will decrease in run-length encoding, so no explanation is needed. Not only is it not possible to achieve highly efficient suppression, but the amount of data may actually increase.

Conventionally, a bit interleaving method has been known as a means to solve the above problem. In the bit interleaving method, pixels corresponding to threshold values that are close to each other are grouped and converted into multiple series of bit patterns, or pixels with the same threshold are grouped and converted to multiple series of bit patterns, and each bit pattern is MH encoding has been applied to the data, but it has not been possible to expect a significant increase in efficiency.

[Object of the Invention] The present invention was made in view of the drawbacks of the above-mentioned conventional examples, and its purpose is to propose a redundancy suppression coding method that suppresses the redundancy of a binary signal with high efficiency.

Means for Solving Problem E] In order to solve the above problem, 2, which is an example of a binary signal,
The redundancy reduction encoding method of the embodiment shown in FIG. 1, which is applied to suppress the redundancy of value image data, can be used as preprocessing for the run-length encoding unit 2 that performs MH encoding, for example. , a bit interleave reconstruction unit 3 which rearranges the z-value image data 4 by bit interleaving at a predetermined period to obtain a binary signal sequence 5,
The preprocessing unit 1 includes a change point extracting unit 6 for converting a value signal sequence 5 into a binary signal sequence 13 in which changes and non-changes in logical values are used as new z values.

[Operation] Under the above configuration, if the input binary image data 4 is a halftone image area-modulated by the dither method as shown in FIG. 3, a binary signal sequence 5 with a large white or black bias is obtained. The reason for this is that the dither matrix is, for example, shown in Figure 2 (
If the image data is 4×4 as shown in b), the image data after dither processing will include periodicity as shown in Figure 3(b), so
This is because white or black is unevenly distributed in the binary signal string 5 due to bit-by-bit interleaving, and the white run length and black run length become long.

Furthermore, the changing point extracting unit 6 performs z-value conversion by extracting changing points,
For example, if the logic value change point of signal string 5 is set to "l" and the other no-change points are converted to z value as "O11", the logic value "
l" will be only the above-mentioned change points. Then, the number of "0" runs will further increase, so run-length encoding by the run-length encoding unit 2 will be efficient, and a high data compression rate can be obtained.Run-length encoding unit 2, for example, the binary signal string 13 is assigned an "O" run and a "1" run is set to 0 by the unit 7.
They are divided into runs and "1" runs, and run-length encoded by run-length encoders 8 and 9, respectively.

[Examples] Examples according to the present invention will be described in further detail below with reference to the accompanying drawings. As mentioned above, the embodiment includes the preprocessing section 1,
It consists of a combination with an encoding section 2.

The preprocessing section 1 consists of a bit interleave reconstruction section 3 and a change point extraction section 6. Furthermore, the internal configuration of the encoding unit 2 differs depending on the encoding method described later (FIGS. 9 and 11). First, let us explain the preprocessing section 1.

Bit Interleaving Reconfiguration Unit> The bit interleaving method will be described with reference to FIGS. 4(a) and 4(b), FIGS. 5(a) to 5(C), and FIG. 6.

FIG. 4(a) shows original image data 4 that has been binarized using the dither matrix shown in FIG. For convenience, the numbers attached to the 0 diagrams indicating those having the same characteristics are the pixel numbers in the main scanning direction and the line numbers in the sub-scanning direction. This image data 4 has a periodicity of 4 bits.As mentioned above, such a dithered image is excellent for expressing halftones, but as shown in the figure, the run length is short. is also clear. When 4-bit interleaving is performed on this image data 4, 1.2, 3, 4. The pixel array of ... is the fourth
1, 5, 9, 13, 17 as shown in figure (b). ..., and it can be seen that the "white" run length and "black" run length are increasing. The reason for using 4 bits is that the dither matrix used for threshold processing is 4 bits, but the above bit interleaving was performed with the same length as the dither matrix. In addition to determining the bit interleaving length in this way, it can also be set to an integer multiple or fraction of the size of the matrix, or with a period corresponding to a threshold with an approximate value in the threshold matrix. There is also a method of grouping.

Now, a circuit for performing such bit interleaving is shown in FIG. 6. The bit interleaving reconfiguring unit 3 in FIG.
Two line memories 40 and 41 are used to rearrange the value image data 4. The two used are binary image data 4
In other words, when inputting (writing) to one line memory, the other line memory is used for outputting (reading). be exposed. To prevent one line memory from being used for writing and reading at the same time,
An address counter 25 for writing, an address counter 26 for reading, and a selector 27 that distributes the outputs of these counters 25.26 to each line memory 40.41.
, 28, 29, 30, 31, 32, and a line memory control unit 42 that performs exclusive control. Line memory control unit 4
2 is a second signal in synchronization with the BD signal 38 generated for each line.
The line memory write signal 36 or the first line memory write signal 37 is set to "°1" alternately, and the selector 27,
28, 31 are selectors that select an output according to the logical value of the second line memory write signal 36 or the first line memory write signal 37; on the other hand, selectors 29, 30 .
32 similarly selects an input according to the logical value of the second line memory write signal 36 or the first line memory write signal 37. In this way, when the first line memory write signal 37 is "1", the second line memory write signal 36 is "O", the selector 27 outputs "0", and the selector 29 inputs "ON". , selector 31
In order to select the output "θ", binary image data 4 is written to the first line memory 40, while the output of the read address counter 26 is input to the second line memory 41 by the selector 28 and the selector 30, and the selector 32 Select the second line memory 41. In this way, simultaneous writing and reading processing can be performed, contributing to increased speed.

The address generation method for each address counter 25 and 26 is shown in FIG. 5. The capacity of the line memory is shown in FIG. 5(a), for example.
As shown in <000 to FFF. The write address counter 25 may be incremented sequentially in ascending order from OOO to FFF as shown in FIG. 5(b), and the read address counter 26 may be increased as shown in FIG. 5(C). Such an address generation circuit of the read counter 26 is as follows.
For example, it can be easily configured by using a counter identical to the write address counter 25, a counter with an output of "1" to "4" for offset, and an adder. The BD signal 38 of this embodiment uses a beam detect signal if the present redundancy suppression encoding method is applied to, for example, a laser beam printer, or uses a horizontal synchronization signal if applied to a facsimile or the like.

In addition, address counters 25 and 26 and line memory 40
．． The driving clock 41 is the synchronous clock 35. This synchronized clock 35 is generated by the encoding unit 2. When encoding in the encoding unit 2, if the signal sequence has a certain pattern, it becomes necessary to forcibly insert a predetermined code. In this case, it is used to stop the operation of the pit interleague reconstruction unit 3 until the synthesis unit 10 finishes sending out the forced insertion code (details will be described later).

Figure 7 (b) shows an example of a circuit for extracting a change point, and Figure 7 (a) shows the result. This is a case of extracting a change point between pixels adjacent to each other by one pixel in the main scanning direction. A flip-flop 2 is used to detect one adjacent pixel, and an EX-OR gate (exclusive OR gate) 21 is used to detect a change point.

The 4-bit interleaved signal string 5 is subjected to EX-OR with the pixel immediately preceding the pixel on the same scanning line as the pixel of interest. That is, if pixels are made to correspond to the threshold value Dij shown in FIG. 2(a), D xij = D ij ■ I)1-+*j. As can be seen by comparing Figure 4 (b) and Figure 7 (a), the "O" run (such °゛O" run is also called °white run) is longer. , it is obvious that it is suitable for run-length encoding.

The preprocessing for redundancy reduction coding has been described above. Next, two embodiments of the encoding unit 2 will be described. The two are implementations that perform run-length encoding processing using one-dimensional encoding for each "l" run and each "on" run, as shown in FIGS. 8(a), (b) and 11. This is an embodiment in which run-length encoding is performed by cutting out blocks shown in FIGS. 10(L) to 10(C) and FIG. 9.

(Run-length encoding) Example of one-dimensional encoding FIG. 8(a) shows the difference between the 40' run and the 1'' run in the signal sequence 13 from which the change points in FIG. 7(a) have been extracted. Indicates how to draw attention.Furthermore, according to the convention in the diagram, 110 IT is
1" is expressed as "black" because it is easy to display the number of digits. If such a run is encoded by MH encoding, for example, the result will be as shown in FIG. 8(b). FIG. 8(a) )'s second line starts with ``Black''. The MH encoding method starts with a "white" run.

Therefore, in such a case, one ° is forced before “black”.
“Insert white ´°.

FIG. 9 shows an example of a circuit for such run length encoding. In FIG. 8, the RL (run length) counter 51. Selector 52. The "white" MH encoding ROM 53 etc. encodes the "O°"("whitepar") run, and the latch 54 latches the encoded code. Also, RL cow 7ta 72, "black" M)
(The encoding ROM 73 etc. encodes the "l°'("black") run, and the code is latched in the latch 61. As for distribution, the circuit 71 changes the signal sequence 13 ("0°'→"OIt
,'O''→“1”, “1”→“O”, “l”→“1”)
Detect. The RL counters 51 and 72 are counters that use CLK as a driving clock, and have "1" at their EN (energization) terminals.
” is input, counting becomes possible, and when “1” is input to the CL (clear) terminal, it is cleared. Therefore, for example, the RL counter 51 continues counting while the signal string 13 is “On”, and the count value is A corresponding MH code is input to the latch 54. Signal train 13 changes from “O” to “l”
”, the sign code of the count value at that time is latched in the latch 54, and at the same time the counter 51 is cleared. The 0 synthesizer 62 synthesizes the “white” code and the black code and stores it in the shift register 63. This is for storage.Since the MH code has a variable length, such a synthesizer is necessary.The shift register 63 performs parallel-to-serial conversion.

As described above, the white "OII insertion section 55 is for inserting one "white" when the beginning of each line (the BD signal 38 is "l") is "l'' (black). For this purpose, A
When the ND gate 70 opens, the white "O" insertion section 55 outputs "0" to the selector 52. In this way, own MH encoding R
OM53 has MH code for “0” = “001101
01". In this way, white "0" is forcibly inserted. Note that the clock control 58 is a circuit that generates the synchronization clock 35 of the bit interleaving section described above, and at the timing of the above-mentioned forced insertion, This '00110
101'' is output from the shift register 63.
The generation of the synchronous clock 35 is stopped. This is for synchronizing the input to the line memory 40 or 41 and the output from the shift register 63. In this way, compressed data 12 with a high compression ratio is obtained from the original image data 4 shown in FIG. 4(a).

Note that the MH encoding method was used in the circuit shown in FIG.
For example, Wyle code may be used as the dimensional encoding, and it is obvious that it can be easily applied not only to one-dimensional encoding but also to two-dimensional encoding processing such as MR symbols and MMR symbols. does not choose the encoding method. Furthermore, for color images, R, G, B or Y, M, C, B
It is applicable to each of the following.

Next, another embodiment of the encoding process will be described.

Run-length encoding〉... Example using block extraction The block extraction method of this embodiment is based on the following facts. The characteristics appearing in the signal sequence 13 obtained by extracting changing points from such a long signal sequence 5 are as follows.

■: There is a high probability that the logical value “l” will be isolated and unevenly distributed surrounded by “O゛” (in other words, it will be “1000”). This is because the “white” run and the “black” run are This is because if the length is long, the change point "1" will occur only at both ends.

■ On the other hand, an isolated "black" in a long "white" run.

And if we catch the change point of the isolated "white" in the long black run, we get "1100".

From ■ and ■ above, signal string 13 has "1000" and "1".
It can be seen that 100" occurs frequently.

This is obvious when looking at Figure 7(a).

Therefore, we focused on the patterns that occur frequently like this,
If a predetermined encoding is performed to make the bit length shorter than the pattern length, the compression rate by encoding will improve.

In this embodiment, this predetermined encoding is performed during the “0” run.
” occurs, a block of a predetermined length is cut out from that “1”. For example, in the example of FIG. 10(b), a block of 4 bits long is cut out, and
0”, 2-bit codes “00” and “o” respectively.
On the other hand, MH encoding is performed for "O+t silane."

FIG. 1.theta.(a) is a diagram explaining the concept of block extraction. The cutting method is to cut out a 4-bit block when a new buffer such as a 14 Q IT silane is generated. Therefore.

There are only 16 4-bit patterns as shown in FIG. 10(b), so a name CB+...B16) and a code are assigned to each block pattern as shown in FIG. 10(b). Here, in order to make the "On run" and the above blocks line up alternately, if a block occurs immediately after the block (the 11th and 1st line of the 1st line),
between the 5th and 34th and 38th pixels of the fourth line), one OIf is forcibly inserted. When this "0" is MH encoded, it becomes "00110101". Furthermore, when the beginning of each line starts with a block (second line), one °°0" is inserted in the same way.The first
Figure 0 (C) shows the signal train of Figure io (a) in Figure 10 (b).
10(C) shows the case of encoding based on the rules of
is referred to as "white".

FIG. 11 shows a circuit configuration diagram of such an embodiment. In FIG. 1, components that are substantially the same as those of the embodiment shown in FIG. 9 are given the same numbers, and major differences are indicated. is a circuit for extracting a 4-bit block and encoding the block. A 4-bit shift register 59 holds the signal string 13 with a length of 4 bits.

The output of the 4-bit shift register 59 is block encoded R.
The OM 60 performs encoding according to the rules as shown in FIG.
A change in the signal string 13 from "Q If" to "L" is detected, and the signal 65 is activated 4 bit times after the change. At this timing, the output of the block encoding ROM 60 is latched into the latch 61.

AND gate 57 follows one block, It O
When the "l" signal is input immediately without inputting the II plan (signal string 13 is "1'°, and signal 64 is "°")
This is to insert one "white pad" into "t").

White “O” insertion part 55, clock control part 58,
The role of gate 70, etc. is the same as in the case of FIG. In this way, when a predetermined pattern occurs, encoding is performed by cutting out blocks, so that high compression can be achieved.

In the above embodiment, the block length is 4 bits, but there is no limitation to this, and it is determined depending on the circuit scale and the type of original image data. Incidentally, setting the length to 8 bits improves efficiency somewhat. Furthermore, the efficiency of MH encoding for the 'O'' run can be further improved by slightly changing the encoding ROM table.Also, if it can be applied to color images as well as the embodiment shown in FIG. It is applicable not only to the MH encoding method but also to other one-dimensional encoding methods.

(Effects of Examples) The effects of the various examples described above are summarized as follows.

(2): Bit interleaving processing is applied to the binary image data, so even if the white run and black run are separated, the run length is restored and becomes longer.

This is particularly effective for image data that has been subjected to halftone processing using a threshold matrix.

■: Since change point extraction processing is further applied to the signal sequence that has been subjected to bit interleaving processing, the run tone of "1" is short,
“The run length of OTL is longer, so we can expect higher compression in the encoding process.As a result, pseudo-halftone images can be compressed with high efficiency while using the encoding algorithm for document images as is. .

In particular, if existing encoding such as MH encoding is used, a redundancy suppression method with a high compression ratio can be obtained with only slight changes to the conventional circuit.

(2): Due to the change point extraction in (2) above, many signal sequences (blocks) having a predetermined pattern are generated. Therefore, this pattern is encoded into a code with a short bit length. Also, '0
The run is encoded by applying one-dimensional encoding such as MH encoding as before.In other words, depending on the type of original image data, the signal sequence from which the change points are extracted may be encoded by applying one-dimensional encoding such as MH encoding. " or "1100..." occur frequently, so the compression rate can be increased by encoding such blocks with short bits.

[Effects of the Invention] As described above, according to the present invention, a highly efficient redundancy suppression coding method can be obtained by combining rearrangement by bit interleaving and lengthening the run length by extracting changing points.

[Brief explanation of drawings]

Figure 1 is a principle configuration diagram of an embodiment according to the present invention, and Figure 2 (a
) and (b) are dither matrix diagrams provided for the embodiment according to the present invention and the conventional example, and FIGS. 3 (a) and (b) explain how the degree of bit dispersion increases due to halftone processing in the conventional example. FIGS. 4(a) and 4(b) are diagrams explaining the principle of bit interleaving. FIGS. 5A to 5C are diagrams explaining the principle of bit interleaving address generation. Figure 6 is a circuit diagram of the bit interleave reconfiguration unit, Figures 7 (a) and (b) are diagrams explaining the operation and circuit configuration of the change point extraction unit, and Figures 8 (a) and (b) are the main FIG. 9 is a circuit diagram of an embodiment that realizes the operations shown in FIGS. 8(a) and (b); FIG. 10 (1iL ) to (C) are diagrams explaining the principle of the encoding method of one embodiment of the present invention, and FIG. 11 is a circuit of the embodiment that realizes the operations shown in FIGS. 10(a) to (C). It is a diagram. In the figure, 1... preprocessing unit, 2... encoding unit, 3... bit interleave reconstruction unit, 4... binary image data, 5...
...Bit interleaved signal sequence, 6. Change point extraction section, 7. 0" run, 1" run allocation section,
8.9... Run-length encoding unit, lO... Combining unit, 12... Two-individual code with redundancy suppressed. No. (G') (b) 5Figure 1- MJB 5- Lumpy σ 2:2 aoq -σA tlN3θ
(IQ (II and
aap(C)

Claims (4)

[Claims] (1) In a redundancy reduction coding method in which a first binary signal sequence is preprocessed and encoded, the preprocessing is performed by
The value signal string is rearranged by bit interleaving with a predetermined period to obtain a second binary signal string, and the second binary signal string is
A redundancy suppression coding method characterized by converting changes and non-changes in logical values of the second binary signal string into a third binary signal string as new binary values. (2) The redundancy suppression coding method according to claim 1, wherein the first binary signal sequence is a binary image signal sequence obtained by binarizing an image signal using a threshold matrix. (3) Changes in logical values are calculated by
2. The redundancy suppression coding method according to claim 1, wherein the redundancy reduction coding method is characterized in that detection is performed by exclusive OR of two binary signals. (4) The redundancy reduction coding method according to claim 1, wherein the coding is one-dimensional coding.