JPS6367968A - Redundancy suppression coding system - Google Patents

Abstract

PURPOSE:To obtain a signal in which a redundancy is suppressed with a high efficiency by executing a run length coding to a zero block and converting to a prescribed signal code and compressing to a fixed length non-zero block. CONSTITUTION:A run length coding part 11CM suppresses the redundancy to the variable length zero block of four rows by the run length coding and a block coding part 8CM executes the coding such as assigning the signal code of the code length shorter than the fixed length of the block, for instance, to the respective blocks of one row and four columns with respect to the specific pattern of the non-zero block. In a synthesizing part 12CM, the run length code, the four block codes are arranged in a prescribed sequence and synthesized to output a picture data string 13CM.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to redundancy suppression coding that suppresses the redundancy of a binary multilevel code of multiple lines, such as color binary multilevel dithered image data. It is related to the method.

[Prior Art] In a redundancy suppression coding method for binary signals such as binary image data, it is necessary to obtain a signal sequence with greater bias in statistical properties than the original element sequence, and to A major challenge is to obtain a high compression ratio by simply encoding the obtained signal sequence.

In a signal sequence with large statistical bias, the length of consecutive sequences with the same logical value becomes longer, so if run-length encoding is performed, so-called entropy is reduced and an extremely high compression ratio can be obtained. .

However, encoding methods in the field of image communications, especially facsimile communications, such as MH (Modified Huffman) encoding, MR (Modified READ) encoding, and MMR (Modified, Modified READ) encoding recommended by CCITT, are Not only facsimile,
It is well known that these encoding methods are also used for electronic files, etc., but these encoding methods focus on the fact that document information such as characters inherently has many "white" runs, and are used to encode such images. This is based on the premise of data transmission. On the other hand, in addition to general document images, binary images such as halftone images such as photographs may be pseudo halftone images that are binarized using a dither method or the like. However, since pseudo-halftone images produce gradation using the area gradation method, due to their nature, printed dots (
゛Black°゛) will be dispersed. That is, the pseudo halftone image has an increased "run length" which is shorter than the original halftone image, which is inconvenient for encoding if left as is.

This situation is explained in Figure 2 (a) to (c) and Figure 3 (a), (b) for a four-value dither as an example of a binary multi-value dither.
). The matrices of FIGS. 2(a) and 2(b) represent threshold matrices, particularly dot-concentrated dither matrices. Figure (C) shows dots (pixels) and data (2-bit pulse width modulation) in a 4-value dither.
It shows the relationship between The solid line in Figure 3(a) is the same as in Figure 2(
The threshold change in the first row of b) is shown. When a halftone image as shown by the dotted line in the figure is created manually for such a threshold value, the third
Pseudo halftone image data having a discrete distribution as shown in Figure (b) is obtained. Like this ゛white°゛゛゛black゛°
It is self-explanatory that when the numbers become disjointed, the compression rate decreases in run-length encoding. Furthermore, if MH encoding or the like is performed on such a pseudo-halftone image, not only is highly efficient suppression not possible, but the amount of data may increase.

Conventionally, a bit interleaving method has been known as a means to solve the above problem. In the bit interleaving method, pixels corresponding to threshold values that are close to each other are grouped and converted into multi-line pit patterns, or pixels with the same threshold are grouped and converted into multi-line bit patterns, and each Although MH encoding is performed on the bit pattern, significant efficiency improvements cannot be expected.

On the other hand, compared to the above-mentioned black and white images, the amount of information in color images is enormous, 3 to 4 times larger, and recently, due to commercialization, the information per pixel has also tended to become binary and multivalued. be. Therefore, it is not the white/black image ratio that requires a highly efficient redundancy reduction coding scheme to transmit or store this information. However, there is currently no effective redundancy suppression coding method for color image information, and a method that combines the conventional methods for black and white images described above, that is, pit interleaving, MH coding, etc., is used for image data of each color. This is the reality, and it is not possible to expect high efficiency.

[Problems to be Solved by the Invention] The above-mentioned problems, especially those related to color image data, are not limited to only those problems, but can also occur with binary multi-valued element sequences that occur simultaneously in a plurality of rows.

SUMMARY OF THE INVENTION The present invention has been devised in view of the drawbacks of the conventional examples described above, and its purpose is to provide a redundancy suppression code that efficiently suppresses the redundancy of an element string that has multiple rows and each row has binary multi-value elements. The objective is to propose a method for converting

[Means for Solving the Problems] One configuration of the present invention for achieving the above-mentioned object is an element string of M rows, in which one element in each row is represented by binary multivalued data of 2N values. From among the columns, M×N fixed-length non-zero blocks with a fixed length that include at least one element that is not “°0°°” and M×N that include only elements that are “0”. a cut-out means for cutting out variable-length zero blocks in rows; a run-length encoding unit for converting the M×N rows of variable-length zero blocks into run-length codes by run-length encoding; a block encoding unit that performs predetermined encoding on each row of a fixed-length non-zero block to generate M×N encoded codes; and a synthesis section that synthesizes and outputs the result in the order of .

According to another configuration of the present invention, the element string is M rows, and one element in each row is represented by M×N binary multi-value data of 2N values.
The first element column of a row is rearranged by bit interleaving at a predetermined period for each row to form a second element column of M×N rows, and the second element column is further rearranged for each row by bit interleaving of a predetermined period. a preprocessing unit that converts changes and non-changes in the logical values of columns into new binary values into M×N rows of third element columns; a fixed-length non-zero block of M×N rows with a fixed length and including at least one non-zero element;
an extraction means for cutting out an M×N row variable-length zero block containing only elements that are “o”; and converting the M×N row variable-length zero block into a run-length code by run-length encoding. a run-length encoding unit; a block encoding unit that performs predetermined encoding on each row of the M×N fixed-length non-cell block to generate M×N encoded codes; It consists of a combining section that combines the code and the predetermined encoding code in a predetermined order and outputs the result.

[Operations] According to one configuration of the present invention described above, variable length zero blocks of M rows of 2N values are shortened in bit length by run-length encoding, and for M×N blocks of fixed length non-zero blocks, Block encoding reduces bit length.

According to another configuration of the present invention, the bit interleaving process and the change point extraction process performed by the preprocessing section increase the run length of data before being encoded, which reduces the compression efficiency of encoding.

[Embodiments] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Embodiments to which the present invention is applied include embodiments characterized by the encoding method itself, and embodiments characterized by the combination of preprocessing, which is a step before encoding, and the encoding.

<Principle of Examples> Therefore, in order to easily understand the outline of the concept of the present invention,
Regarding an example in which the combination of the preprocessing and encoding described above is applied to quaternary color image data, Fig. 1(a) and (
This will be explained using b). The difference between the embodiments shown in FIGS. 2A and 2B is a difference in encoding.

(Outline of First Embodiment) FIG. 1(a) First, the embodiment of FIG. 1(a) will be explained. The element string manually entered in this embodiment is color image data, for example, a 4×2 (=a) row of color binary image data string (7 cu
, 7 CL, 7 ML+.

7 ML, 7 YU+ 7 YL, 7 KLI+
7 KL). Here, C represents cyan, M represents magenta, Y represents yellow, K represents black, and U
It is assumed that L represents the upper bit and L represents the lower bit.

On the other hand, in this embodiment, one pixel consists of four elements of CMYK, and two image data of C and M are grouped into one, and two image data of Y and K are grouped into one. Furthermore, one element consists of two bits, upper (U) and lower (L), and the total is an element string of 4 (CMYK) x 2 (LIL) rows. Also, when I say column, I mean the main scanning direction.
A row refers to the depth direction of each element and the direction perpendicular to the column of each element column. The encoding shown in FIG. 1(a) preprocesses the upper and lower bits of the four rows of binary image data, and further encodes the data after this preprocessing. In this case, C and M, Y and K are preprocessed and encoded as one group (that is, 4 lines and 4 lines), so C and M, Y and K are processed in the same way. Therefore, in the following explanation, the combination of C and M will be explained.

Now, the configuration of the C and M preprocessing sections is 2 x 2 binary image data (4 cu, 4 cb, 4 Mll, 4 ML)
A bit interleaving reconstruction unit (3C, 3M) rearranges the data for each row by bit interleaving at a predetermined period, and further the rearranged binary image data (5CU+5
Change point extraction for converting each of cL, 5MU, 5 ML) into binary image data (7 cu, 7 CL, 7 Mu, 7 ML) with changes or no changes in the logical value as new logical values. (6C, 6M).

According to this configuration, input 2x2 rows of binary color image data (4cu, 4CL, 4M11.4
If M+, ) is obtained by area-modulating a halftone image using the dither method as shown in FIG. Binary color image data (5CU+”
CL+ 5ML1. ”ML) is obtained.The reason is that the dither matrix is 4x as shown in Fig. 2(b).
4, the image data after the dither processing has the image data shown in Figure 3 (b).
), so by bit interleaving every 4 bits in the main scanning direction, two binary signal sequences (
0° for 5 cu, 5 CL+5 Mu, 5 ML)
° or 1°° are unevenly distributed, “o” run length, and ゛1°
This is because the run length becomes longer.

Furthermore, the change point extractor (6C, 6M) performs binarization by extracting the change point, for example, the signal sequence (5 cu, 5 cl, etc.).

If the logical value change point of 5 M11 + 5 ML) is set to 1°, and the other no-change points are binarized to “°0°°,” the logical value “1” will be only at the above changing point. Then , '0' runs further increase, so run-length encoding by the run-length encoding unit 11CH becomes more efficient.
A high data compression rate can be obtained.

The outline of the encoding according to the first example will be further explained. The structure of the 2CM at the bottom of the code is two binary image data strings (7CLI+7CL+7MLI, 7ML
), the 0-1 detection unit 9CM detects a pit whose value is '1°°, and the 0→1 detection unit 9cM detects a change from °゛0°°→``°1゛. At the time of detection, a run-length encoding unit 11 cuts out a 2×2 (=4 rows) variable-length zero block containing only previous zero elements.
CM and the four rows of variable length zero blocks, followed by the four rows of binary code sequences (7cυ+7CI−+7yu, 7M
Regarding L), it consists of a block encoding unit 8CM that cuts out fixed-length non-zero blocks (four 1-row, 4-column blocks) of a predetermined length (for example, 4 columns), and a combining unit 12cM that combines these encoded codes. .

The run-length encoding unit 11CM suppresses redundancy by run-length encoding the four rows of variable-length zero blocks, and the block encoding unit 8CM encodes each extracted four-line zero block.
A predetermined encoding is applied to each of the fixed length non-zero blocks arranged in 1 row and 4 columns to obtain four block codes. Synthesizer 12
In the CM, a run-length code and four block codes are arranged and combined in a predetermined order, and an image data string 13c is output.

According to the configuration of the embodiment shown in FIG. 1(a), “0”
Runs are compressed with high efficiency by run-length encoding. In addition, four binary color image data strings (7C1,
7CL, 7MU, 7ML) signal source type (
For example, in the case of image data, depending on the type of original image, non-zero blocks may include many specific patterns. For such a specific pattern, the block encoding unit ac performs encoding such as assigning a code with a code length shorter than the fixed length of the block to each block of 1 row and 4 columns.
ii, even an image data string containing 1° can be compressed with high efficiency. For example, FIG. 8(a) shows a pattern obtained by the non-zero block, and shows an example of encoding performed on a block in 1st row and 4th column having that pattern.

<Outline of the second embodiment>...Fig. 1(b) Fig. 1(b)
The preprocessing in this embodiment is the same as the embodiment shown in FIG. The encoding unit 2CM includes a pattern determining unit 17cM that examines the pattern of the four non-zero blocks arranged in the 1st row and 4th column, and a flag indicating that such a block has such a pattern. The difference lies in that it includes a flag generating section 14cM that generates the flag.

Now, in the block encoding in the first embodiment, data compression was achieved by using a code with a code length shorter than the block length for frequently occurring patterns. In the example, the flag generation unit 14cM generates a flag indicating that such a specific pattern is present,
By adding this to the encoded compressed signal 13cM, further compression is aimed at. In addition, an example of the flag is shown in the 12th
Shown in Figures (a) and (b).

1. (Explanation of each component) The explanation will be given below in sequence according to the drawings.
As shown in a) and (b), the combination of the C signal and the M signal is equivalent to the combination of the Y signal and the signal.

Therefore, the combination of the C signal and the M signal will be explained. Furthermore, since each component of the embodiment shown in FIGS. 1(a) and 1(b) has many common parts, in order to avoid duplication of explanation, the attached drawings described below are for each one color or two colors. Examples of circuits, etc.

Regarding the signal C, the preprocessing section includes a bit interleave reconstruction section 3c and a change point extraction section 6c. or,
As described above, the encoding unit 2CM has different internal configurations depending on the encoding method (FIG. 10(a) and FIG. 11). First, let us explain the preprocessing section ICM+IYK.

<Bit Interleaving Reconfiguration Unit> The bit interleaving method will be explained using FIGS. 4(a) and (b), FIGS. 5(a) to (C), and FIG. 6.

FIG. 4(a) shows, for example, a C signal 4 CU+ 4 which has been 4-valued using the dither matrix shown in FIG. 2(a) or (b).
CL% and M signals 4MLI+4ML, which have a size of 40 pixels in the main scanning direction (ie, column direction), are shown. The numbers given in the figure are the numbers of pixels in the main scanning direction for convenience. This C signal 4 CU+ 4
The CL and M signals 4MU+4ML each have a periodicity of 4 bits. As mentioned above, such a dithered image is excellent for expressing halftones, but it is clear from the figure that the run length is short.

This binary code 4 CU+ 4 CL and 4MU+ 4
If 4-bit interleaving is performed for each ML, 1.2, 3, 4. in FIG. 4(a). The pixel array of ... is the fourth
1, 5, 9, 13, 17 as shown in figure (b). ..., and it can be seen that the lengths of the ``white'' run and the ``black'' run are increasing. The reason for using 4 bits is that the dither matrix used for threshold processing is 4 bits, but the above bit interleaving was performed with the same length as the dither matrix. In addition to determining the bit interleaving length in this way, it can also be set to an integer multiple or fraction of the size of the matrix, or with a period corresponding to a threshold with an approximate value in the threshold matrix. There is also a method of grouping.

A circuit for performing such bit interleaving is shown in FIG. 6 (only for the C signal). The bit interleaving reconfiguring unit 3° in FIG.
Two sets of line memories 40.4 for CL reordering
1 is used. Although one set of line memories is not shown, it is assumed that the set includes line memories for upper bits and lower bits. Two sets of C signals are used: 4 CU and 4 CL input, rearrangement operation, and rearranged image data string "C".
This is to perform the operation of reading U+5CL at the same time.

That is, when inputting (writing) to one set of line memories, the other set of line memories is used for outputting (reading). In order to prevent one line memory from being used for writing and reading at the same time, an address counter 25 for writing, an address counter 26 for reading, and a selector that distributes the outputs of these counters 25 and 26 to each line memory 40, 41 are provided. 27, 28, 29, 30, 31, 32, and a line memory control unit 42 that performs exclusive control. The line memory control unit 42 alternately sets the second line memory write signal 36 or the first line memory write signal 37 to 1° in synchronization with the BD signal 38 generated for each line.

Further, the selectors 27, 28, and 31 are selectors that select the output according to the logical value of the second line memory write signal 36 or the first line memory write signal 37, while the selectors 29, 30, and 32 similarly The input is selected according to the logical value of the 2-line memory write signal 36 or the 1st line memory write signal 37. In this way, when the first line memory write signal 37 is "1", the second line memory write signal 36 is "0", the selector 27 outputs "o", and the selector 29 outputs "o".
“0”, selector 31 selects 2 to select output “o”.
Evolution codes 4CU+4CL and 4MU+4ML are written to the first line memory 40, while the output of the read address counter 26 is written to the selector 28 and the selector 30.
is input to the second line memory 41, and the selector 32 selects the second line memory 41. In this way, writing and reading can be performed simultaneously, contributing to speeding up.

A method of generating addresses for each address counter 25 and 26 is shown in FIG. For example, the capacity of the line memory is shown in Figure 5(a).
As shown in <000 NFF'F. The write address counter 25 ranges from 000 to FFF as shown in FIG. 5(b).
You can increase them sequentially in ascending order up to. Further, the read address counter 26 is configured as shown in FIG. 5(C). Such an address generation circuit for the read counter 26 can be easily configured by using, for example, a counter that is the same as the write address counter 25, a counter that outputs "1" to "4" for offset, and an adder. .still,
The BD signal 38 of this embodiment uses a beam detect signal when the tree redundancy suppression coding method is applied to, for example, a laser beam printer, and uses a horizontal synchronization signal when applied to a fukushimiri or the like.

In addition, address counters 25 and 26 and line memory 40
．． The driving clock 41 is a synchronous clock 35CM.

This synchronization clock 35cM is generated by the encoding unit 2CM, and when the image data string has a certain pattern during encoding in the encoding unit 2CM, a predetermined code is forcibly applied to achieve synchronization. In that case, the forced insertion code is used to stop the operation of the bit interleaving reconfiguring units 3c and 3v until the combining unit 10 finishes sending out the forced insertion code (details will be described later).

The bit interleaving reconfiguration unit as described above performs bit interleaving for each of the upper and lower bits of each color of the color signal. By the way, as you can see from Figure 1(a) etc., the binary code numbers 7c0°7cL and 7ML++
7ML is simultaneously encoded by the encoder 2 CM.

Further, as will be described later, the run-length encoding unit 11cM performs run-length encoding on the C signal and the M signal together.

In addition, the encoding of the block of 1 row and 4 columns including ``B'' is performed every predetermined length. That is, the bit interleaving preprocessing of the C signal and the Y signal is synchronized, and therefore, as shown in FIG. Among the components, the components other than the first line memory 4o and the second line memory 41 can be made common, and this common use contributes to downsizing of the circuit.The same applies to the combination of the signal Y and the signal Y.

<Extraction of changing points> FIG. 7(b) shows an example of a circuit for extracting changing points for the binary code 7 CLl+ 7 CL, and FIG. 7(a) shows the results. An example of the change point extraction section 6c in FIG. 7(b) is a case where a change point between pixels adjacent to each other by one pixel in the main scanning direction of the signal C is extracted.

Flip-flop 2 to detect one adjacent pixel
EX-O to detect the change point using 0u or 20L
R gate (exclusive OR gate) 2tu (or 21L
) is used. The 4-bit interleaved binary code string 5CLI15CL is subjected to EX-OR with the pixel immediately preceding the pixel on the same scanning line as the pixel of interest. That is, the binary code sequence 5 Cur 5 CL is set to the threshold DIJ in FIG. 2(a).
If each pixel of
(21L) (7) Output DXIJ (7CU, 7CL
) is D xlJ ” D lj ■ D I-1,J. As can be seen by comparing FIG. 4(b) and FIG. 7(a), there is an "o" run (such 0°).

It is obvious that the runs (also called white runs) are long and are suitable for run-length encoding. Also, bit interleaved image data string 5 CLI+ 5
In CL, the run lengths of the °゛white°゛ run and the ゛°black°° run are long. The characteristics appearing in the image data string (7Cur 7CL) obtained by extracting changing points from the image data string 5Cur 5CL are as follows.

■: The logical value °゛1"' is isolated and unevenly distributed, surrounded by "0" before and after (i.e. "100"0 after "o" run)
This is because if the °゛white゛ run and the ゛°black゛ run are long, the change point °゛1°'' will occur only at both ends of them.

■;On the other hand, an isolated 'black'° in a long 'white' run.

And an isolated ``white'' in a long ``black'' run will roar out ``'1100'' when you catch that change point.

From the above ■ and ■, the image data string (7 cu.

7 Cut 7 MU, 7 ML) “1000
” and “110” and “0” occur frequently. This is obvious when looking at Figure 7(a). The above fact has a great deal to do with encoding, which will be described later.

The preprocessing for redundancy reduction coding has been described above. Therefore, next, regarding the encoding section, FIG. 1(a),
Two embodiments corresponding to (b) will be described. In a sense, the above preprocessing section processes each binary image data independently. The encoding embodiment described below processes two color signals (for example, signal C and signal M) as one signal.

<Encoding of the first embodiment> FIG. 9(a) shows the image data string (7CU, 7CL, 7MU, 7ML) from which the change points of FIG. 7(a) have been extracted.

7 YLI, 7 YLI 7 KU+ 7 K
L) is shown for one line, and how to extract a variable length zero block (or fixed length non-zero block) from this image data string is shown. In the drawings, according to convention, °0°' is represented by °"white °°", and "bi" is represented by "black". This is because it is easier to display the number of digits. Binary evolution issue (7Cut 7 CL,
7MU, 7ML), 0゛ simultaneously in these signals.

A run that contains only 100% is cut out as a white (“'o”) run. For example, “white 6°°” means six consecutive white runs of four lines. Such white (°°0″) runs are compressed by, for example, 14H encoding.

On the other hand, if even one 1°° appears in any row, four fixed-length non-zero blocks of 4-bit length arranged in 1st row and 4th column are cut out. Such a block always contains one or more 1'' somewhere, but it is also possible for one row to have all 0'°. If you perform the pretreatment as described above,
There will be more "°O°" runs overall for each color, but if you cut out a block that includes all colors as shown above, it will be a non-block even though the entire row is "o o o o'". There are many things that are included in For example, the 6th block (Bo) is a block of 1 row and 4 columns containing only zeros (=
ooOO) are included.

This is because the stochastic processes of the C signal and M signal are independent in the same pixel, so the difference between colors is "0" and 1.

This is because the occurrence of is random. The fact that there are many patterns of °0000° suggests the possibility of further compression. This will be explained in another embodiment.

The patterns that can be generated in the fixed length non-zero block obtained in this way are combinations of 16 types of patterns shown in FIG. 8(a). B for convenience for these 16 types of patterns. It is given the symbol name -B+5 and is shown in FIG. 9(a). According to this convention, for example, the first fixed length non-zero block in FIG. 9(a) is (Bo , B+ , Ba ,
B9).

Incidentally, depending on the image data, the signal may not start from a variable length zero block, as in the case of the C signal in FIG. 9(a). In such a case, non-zero blocks (in this example, Bo, B+
, Ba, B9 block).
” (in the MH code, “'00110101°°)” is inserted. Also, the same applies when non-zero blocks are consecutive. This is to ensure that variable-length zero blocks and fixed-length non-zero blocks always occur alternately to ensure synchronization during decoding.

By the way, as mentioned above, many '1000' and 'ttoo' occur during programming due to pre-processing.
When °゛1°° occurs in one of the colors, it becomes part of the block, so there are 0000°'. Therefore, if we focus on patterns that occur in large numbers and perform predetermined encoding to make the bit length shorter than the pattern length, the compression rate by encoding will improve. Now, in the above example, 00oo”, “”tooo” and “”ttoooo
Three types of patterns often occur: In the example of FIG. 8(a), the 2-bit code "0" is set to B. =°“0000
", 01°° is assigned to B3="t to o". In this way, high compression is achieved.

Moreover, all the codes in FIG. 8(a) are unique to each other, and are a combination that will not cause confusion.

The compressed code "10°° is B." is not adopted because it cannot be distinguished from patterns other than B3. In this way, the frequently occurring patterns "'o o o o" and "tto
o” is compressed to 2 bits. On the other hand, “o o o o
For an image in which many patterns other than ",""1100", and "1000°° occur with the same probability, the compression code is set to 3 bits. Then, "o o
o”,゛.

011゛, “010”, “011” (7)4
Various types of compression codes are possible. Although the individual compression results in a worse compression ratio than the 2-bit example, the overall compression ratio is further improved. FIG. 9(b) is a diagram showing the compression pattern of each signal according to the above convention. In Figure 9(b), MH
represents MH encoding. Such encoding is performed for each line. Looking at FIG. 9(b), it can be seen that the encoding of this embodiment has a much higher compression rate than simple MH encoding.

FIG. 10(a) shows a circuit for such encoding (FIG. 1(a)).
This is an example of a) 8CM). In the figure, an RL (run length) counter 51. The selector 52, the "°° white" MH encoding ROM 53, etc. encode a zero run, that is, a variable length zero block, by MH encoding and latch the encoded code in the latch 54.The detection circuit 50 is configured as shown in FIG. ), there are four signal trains (7cu, 7ct+
7 MU+7 ML) changes (“0 PA→“
0°°, “o” →゛1°゛, “t” →“0°
°, "1"→"1") is detected. The RL counter 51 is a counter using CLK as a driving clock, and becomes ready for counting when 1° is input manually to its EN (energizing) terminal, and is cleared when 1° is input to its CL (clear) terminal. Therefore, the RL counter 51 receives the signal string (7 cu
, 7 CL, 7 MIJ+ 7 ML) all at °0
It continues to count as long as °°, and manually inputs the MH code conid corresponding to the count value to the latch 54. When any of the binary code sequences (7CU+7CL+7ML++7ML) changes from 0° to 1°, the sign code of the count value at that time is latched into the latch 54 via the signal 72, and at the same time the counter 51 is cleared. On the other hand, the 4-bit shift registers 6o, 63, 66, and 69 have signal strings (7 cu + 7 c 7 MU, 7
ML) is held for a length of 4 bits. Block encoding RO
M61, 64, 67.70 are 4-bit shift register 6
The outputs 0 to 69 are each encoded according to the rules shown in FIG. 8(a). On the other hand, in the 4-bit counter 55, the detection circuit 5o receives the signal string (7 cu, 7 CL+ 7 MU+
7ML) changes from "o" to 1°, and energizes the signal 73 4 bit times after the change. At this timing, block encoding ROMB1, 64
, 67.70 are latched 62, 65, 68.7, respectively.
Latch to 1. The synthesizer 74 is for synthesizing the respective encoded codes and storing the synthesized code in the shift register 75. , MH code is of variable length, so such a combiner is necessary. Shift register 75 performs parallel-to-serial conversion.

AND gate 76 is there to insert the MH code corresponding to white "o" as described above when a non-zero block starts at the beginning of the line. AND gate 59
, when a signal of °1°' is input immediately after one non-zero block without inputting a run of '0' and the signal 77 is 1°゛), white"
o” to insert the corresponding MH code.

The white "o" insertion section 56 is provided to insert this one "white", and when either of the AND gates 59 or 77 opens, it outputs "o" to the selector 52. In this way, white MH encoding is performed. The RQM 53 outputs the MH code = "ooilololooo" corresponding to °'0', and a white '0' is forcibly inserted.The clock control 57 is controlled by the synchronization clock of the bit interleaving reconfiguration unit 3c and 3M described above. This is a circuit that generates 35cM, but at the timing of the above-mentioned forced insertion, this °'00110101°.

The generation of the synchronous clock 350M is stopped until the shift register 75 finishes outputting the synchronized clock 350M. Line memory 40 or 4
This is for synchronizing the output from the shift register 75 and the input from the shift register 75. In this way, the C signal and M signal in FIG.
Compressed data of 13 cM with a high compression rate is obtained from the signal.

Note that although the MH encoding method is used in the circuit of FIG. 10(a), for example, Wy1e encoding may be used as one-dimensional encoding. Furthermore, it is obvious that the present invention can be easily applied not only to one-dimensional encoding but also to two-dimensional encoding processing such as MR symbols and MMR symbols. Basically, there is no choice of encoding method. Furthermore, it is also applicable to R, G, and B for color images.

<Encoding of Second Embodiment> The above-mentioned embodiment is based on the compression rule shown in FIG. 8(a), and a large number of "o o"s occur in a block.

0°゛, 1100°° respectively code "o o",
”.

It was intended to be compressed to loo. In this example, this 00
The purpose is to compress 00°' even more efficiently.

For this purpose, four non-zero blocks arranged in the 1st row and 4th column are extracted as shown in FIG. 9(a) in the same manner as in the previous embodiment. Then, if there is a 4-bit 0000°' (for convenience, this is referred to as a "'zero pattern°°") in any of the four 1-row, 4-column blocks containing 1", it is used in the example described above. Instead of encoding it as 00°°, as in ``'o o o ooo'', a flag is provided, and the value of the flag is set to ``Ooo''. The flag corresponding to a block containing at least one 1° in the 1st row and 4th column (for convenience, such a block in the 1st row and 4th column is referred to as a non-zero pattern°) is set to 1'°. A flag is provided for each such flag column. Further, the code corresponding to the non-zero pattern is executed as shown in FIG. 8(b).

FIG. 11(a) shows the format after compression. The code code corresponding to the signal 7cU which is the upper bit of the C signal is the #1 code, the code code for the signal 7CL corresponding to the lower bit is the #2 code, and the code code of the signal 7+itu corresponding to the upper bit of the M signal is the #3 code. , the signal 7ML corresponding to the lower bit is set as code #4, and the flags corresponding to these code codes are #IF, #2F, #3, respectively.
F, #4F. For example, if #IF is "0", it indicates that the signal 7cu in the 1st row and 4th column has a zero pattern=oooo, and that there is no corresponding #1 code.

Any combination of 4 rows and 4 columns of blocks is always a combination of a zero pattern and a non-zero pattern, so the combination of flags is '1000°.

"0100'',"0010°',"0001°゛.

"1100°°,"'1001°°,"1010°°
.

``otot'', ``0011°°, ``0110''.

"1110",'"1101°°,"1011".

"0111°", "1111", "015".

FIG. 11(b) shows an example of the format including flags and code.

When data is compressed in this way, the zero pattern does not appear as a code, so there is a risk that synchronization may occur during decoding. However, there is always a flag at the beginning, and its length is always 4 bits, and depending on the logical value of that flag, the length of the code following the flag is <#1 code to #4 code.
You can see how many zero patterns there are in a block of 4 rows and 4 columns. Also, as can be seen from Figure 8(b), 8
The code codes corresponding to 1 to BI5 are all unique. Therefore, even if a zero pattern is converted as if there is no code corresponding to it, there will be no loss of synchronization during decoding.

When the block cutout shown in FIG. 9(a) is compressed according to the compression of this embodiment, it becomes as shown in FIG. 13.

For example, B in the figure. /B l /sa The flag part of /B9 is ° “0111”, there is no #1 code, and the #2 code is '
oo″′, the #3 code is 10001°°, and the #3 code is “11001°”.

FIG. 12 shows an example of a circuit that performs such flag-based encoding. That is, the basic configuration is the same as that of the first embodiment described above (FIGS. 10(a) and (b)), and the block encoding ROMs 61, 64°67.70 are configured as shown in FIG. 12, and the output thereof is The flag output is added to a part of the . For example, if a zero pattern is manually entered into this block encoding ROM, the length will be "1" (1 of the flags).
(only bits), the flag is "'o" and the code is "o". The length output of the ROM is sent to the synthesizer 74.
This information is input into the , and becomes the information when compositing. That is, the synthesizer 74 only outputs 'o o o o''' as "1". In this way, even more effective compression is possible for an image signal containing many o o o o".

In the above embodiment, the block length is 4 bits, but there is no limitation to this, and it is determined depending on the circuit scale and the type of original image data. Incidentally, setting the length to 8 bits improves efficiency somewhat. Furthermore, the efficiency of MH encoding for the 0° run can be further improved by slightly changing the encoding ROM table.Also, the encoding method is not limited to the MH encoding method, but can also be applied to other one-dimensional encoding methods. It can also be applied to law.

Furthermore, as is well known, the binary color signals C, M, and Y may be read out from a memory (not shown), or may be obtained by reading an image in real time and performing binarization processing. good.

<Effects of Examples> The effects of the various embodiments described above are summarized as follows.

(2): Since the pit interleaving process is performed on the color image data in the binary representation of four values, even if the white run and black run are separated, the run length is restored and becomes longer.

This is particularly effective for color image data that has been subjected to halftone processing using a threshold matrix.

■°°1° since change point extraction processing is further performed on the image data string that has been subjected to 2-bit interleaving processing.

The run length of ``'0'' becomes shorter and the run length of ``'0゛'' becomes longer, so high compression of the encoding process can be expected.As a result, while using the encoding algorithm for document images as is, pseudo intermediate It is possible to compress tonal images with high efficiency.

In particular, if existing encoding such as Ml encoding is used, a redundancy suppression method with a high compression rate can be obtained with only slight changes to the conventional circuit.

(2): Due to the change point extraction in (2) above, many image data strings (blocks) having a predetermined pattern are generated. Therefore,
The patterns in this block are encoded into short bit length codes for each row and then synthesized. Furthermore, the ``0°'' run is encoded by applying one-dimensional encoding such as MW encoding as before. In other words, depending on the type of original image data, the image data string from which changing points have been extracted may contain 0000" or 100".
Since 0'' or '1100°° occur frequently, the compression rate can be increased by encoding such blocks with short pits, and the signals of two or more rows can be combined into one signal.

■Secondly, create a zero pattern of °'o o o o”°.
By replacing it with a bit flag, more advanced compression becomes possible.

[Margins below] [Effects of the invention] As explained above, according to the present invention, M
For an element string in a row, where one element in the element string is 2N multivalued, variable length zero blocks of NXM rows in the column direction and fixed NXM rows containing 1°° in either direction. Long non-zero blocks are extracted, zero blocks are run-length encoded, and fixed-length non-zero blocks are converted to a predetermined code and compressed to efficiently suppress redundancy. A signal is obtained.

According to another configuration of the present invention, when the element columns of each row are rearranged by bit interleaving and change points are extracted to lengthen the "0" run length, and the above-mentioned encoding is further added, a specific A more efficient redundancy suppression coding method can be obtained for binary codes having variations.

[Brief explanation of the drawing]

Fig. 1(a) is a diagram of the principle configuration of the first embodiment, Fig. 1(b)
2 is a diagram of the principle configuration of the second embodiment, FIGS. 2(a) and 2(b) are dither matrix diagrams used in the embodiment according to the present invention and the conventional example, and FIG. 2(C) is a diagram of the quaternary image data. Figures illustrating the correspondence between data and pits. Figures 3 (a) and (b) are diagrams explaining how the degree of bit dispersion increases due to halftone processing in the conventional example. Figures 4 (a) and (b) Figures 5(a) to 5(C) are diagrams explaining the principle of bit interleaving common to Embodiment 1.2.
) is a diagram explaining the principle of bit interleaving address generation, Figure 6 is a circuit diagram of the bit interleaving reconfiguration unit, and Figures 7 (a) and (b) are extraction points of change common to the 1.2 embodiments. FIG. 8(a) is a diagram illustrating an example of the encoding code according to the first embodiment; FIG. 8(b) is a diagram illustrating an example of the encoding code according to the second embodiment. FIG. 9(a) is a diagram illustrating an example of a code code, FIG. 9(a) is a diagram illustrating a block extraction method in each embodiment, and FIG. 9(b) is a diagram illustrating a code arrangement after encoding in the first embodiment. Figures 10(a) and 10(b) are circuit diagrams for encoding common to the 1.2 embodiment. Figures 11(a) and 11(b) are encoding formats in the 2nd embodiment. FIG. 12 is a diagram explaining the ROM used for encoding in the second embodiment.
FIG. 13 is a diagram illustrating an example of encoding in the second embodiment. In the figure, ICM+IYK... pre-processing section, 2CM+ 2YK・
・'Encoding unit, 3 CM + 3 YK...Bit interleave reconstruction unit, 4 CLI + 4 CLI 4
Mtl+ 4 MLI 4 YLI+ 4 YL+
4 KU+4KL...4-value power color binary image data, 5
CLII 5 CL. 5MU・5ML・5Yυ・5Yb・5 to υ・
Set to 5...Bit interleaved image data string%
6 CM+ 6 YK...change point extraction section, 7 c
u, 7 CLI 7 MLI, 7 M7YU+7
7, 7xu, 7... Signal with change point extracted, 8
CM+ "YK'...Block encoding unit, 14CM
, 14YK...flag generation section, 9 CM+ 9
YK...0→1 detection unit, 11CM, 11YK...run length encoding unit, 12cii. 12YK...combining unit, 13cM, 13Y...redundancy suppressed binarization signal, 17CM, 17YK...
This is a pattern discrimination section. Figure 2 (a) 2nd - Low Mouth-Lo Figure (c) (a) (b) 5th A Drama [Todashi Matre 2ij Unku 1st 2nd 3rd 4th (c) Figure Q- Loco] -81---11000 Loco] Co1 82--- 10100 T1 Co 83--- 01 0 Col 84--- 10010 Loco I Co 85--- 11010 Mouth ml Co1 86--- 10110 Japan Mko 87---- 11110 Figure 8 (0) Mouth]=Koro--81--00 [Koh [1-82-10100 Country I=Ro 83---01

Claims (6)

[Claims] (1) An element string of M rows, in which one element in each row is a fixed length that includes at least one element that is not "0" from among the element strings represented by 2^N binary multivalued data. M× with
a cutting means for cutting out N rows of fixed length non-zero blocks and M×N rows of variable length zero blocks containing only elements that are “0”; and for the M×N rows of variable length zero blocks; a run-length encoding unit that converts into a run-length code by run-length encoding; and a run-length encoding unit that performs predetermined encoding on each row of the M×N fixed-length non-zero blocks to generate M×N encoded codes. A redundancy reduction encoding system, comprising: a block encoding unit that generates a block encoder; and a combining unit that combines the run-length code and the predetermined encoded code in a predetermined order and outputs the result. (2) The redundancy suppression encoding method according to claim 1, wherein each element is color image data. (3) The run-length encoding unit performs run-length encoding on the number of elements for each row or for each multiple rows of M×N variable-length zero blocks. redundancy reduction coding method. (4) The length of the encoded code in the block encoder is:
2. The redundancy reduction coding method according to claim 1, wherein a part of the code code is shorter than the length of at least a fixed-length non-zero block. (5) The first element string of M×N rows, in which one element of each row is represented by binary multivalued data of 2^N values, is bit-interleaved at a predetermined period for each row. The second element column is rearranged by M×N rows, and the second element column is
a preprocessing unit that converts changes and non-changes in logical values of the second element string into a third element string of M×N rows as new binary values for each row; and a third element string of the M×N rows. M× which has a fixed length and includes at least one non-zero element from among
a cutting means for cutting out N rows of fixed length non-zero blocks and M×N rows of variable length zero blocks containing only elements that are “0”; and for the M×N rows of variable length zero blocks; a run-length encoding unit that converts into a run-length code by run-length encoding; and a run-length encoding unit that performs predetermined encoding on each row of the M×N fixed-length non-zero blocks to generate M×N encoded codes. A redundancy reduction encoding system, comprising: a block encoding unit that generates a block encoder; and a combining unit that combines the run-length code and the predetermined encoded code in a predetermined order and outputs the result. (6) The first element sequence divides the image signal into a threshold value matrix.
6. The redundancy suppression coding method according to claim 5, wherein the redundancy suppression coding method is a hex-multivalued color image data string.