JPS6269789A - Encoding system between frames - Google Patents

Abstract

PURPOSE:To delete the number of blocks, to delete the quantity of generating information and to maintain the resolution of a still area by combining a dot interlace system and a vector quantization and properly controlling the size of the block in the vector quantization. CONSTITUTION:A television signal inputted from a terminal 1 is A/D-converted into a PCM signal, delayed in a delay circuit 3, thereafter an output of a filter 23 is subtracted in a subtracter circuit 4. This output, namely, a prediction error signal converts a picture element encoded and stopped and a prediction error of a field step dropped in a dot interlace and a step dropping circuit 5 into zero or a prediction error value of a preceding picture element. An output of the circuit 5 is divided gradually to a large block in accordance with an increase in the quantity of the memory information of a buffer memory 12 in an adaptive block circuit 6. An average value separating circuit 7 calculates the average value every block of an input and the obtained average value is subtracted from the prediction error value every picture element and outputs to a normalization circuit, and supplies the average value information to a multiplex circuit 10 and an average value adding circuit 16.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a highly efficient interframe coding method for television signals.

(Prior art) As an interframe coding method for television signals, two consecutive
There is a method in which differential signals between frames are vector quantized and encoded and transmitted. In such a method, information in the static area of the TV screen can be removed by taking the interframe difference, and if the ratio of the moving area is 10%, the Vlo
Bandwidth compression is possible. Further, for the moving region, vector quantization is performed for each block consisting of p pixels x q lines. Vector quantization significantly reduces the number of combinations of vector quantization representative values in areas where the probability of occurrence is low and the visual sensitivity is low for combinations of pXq pixel values. There are 9 combinations of 512 letters for ×8 blocks. Therefore, 8
A ×8 block contains 64 pixels, and if this is PCM encoded at 8 bits/pixel, an amount of information of 512 bits/block will be generated. Since the index information represented is 9 bits/block, it is possible to compress the bandwidth by about V57. From the above, when the ratio occupied by the moving area is 10%, a total of 11,570 bands can be compressed. However, such a method has the disadvantage that the amount of information generated increases and the band compression ratio decreases as the subject moves significantly and the proportion occupied by the moving area increases.

As a way to increase the bandwidth compression rate even when the proportion occupied by the dynamic area is large, index One possible method is to shorten the bit length per pixel of information. but,
Increasing the block size has the disadvantage that the circuit scale for selecting the optimal vector quantization representative value during vector quantization increases. In addition, as a method to increase the block size with equal constraints without increasing the scale of the vector quantization circuit, it is possible to thin out every other pixel to be encoded. The disadvantage is that the resolution deteriorates.

(Problem to be Solved by the Invention) For this reason, in this type of conventional method, when the proportion of the moving area is large and the amount of information generated is large, the code for each frame or field of the image is In other words, as the amount of information generated increases, the frame drop rate increases to suppress the generation of information. For this reason, in the conventional method, the number of frames or fields that can be transmitted is reduced when the subject moves significantly, and the reproduced image has the disadvantage of causing jerkiness and deteriorating the image quality.

The purpose of the present invention is to solve the following problems: the circuit scale increases when the size of a block that is a unit of vector quantization is increased; the resolution of a reproduced image deteriorates when pixels to be encoded are thinned out; An object of the present invention is to provide an interframe coding method that solves the problem that the frame drop rate becomes too large when the motion of the frame becomes large.

(Means for Solving the Problems) The feature of the present invention for achieving the above object is that n (n=0.1.2.
...) means for constructing a prediction signal from the pixel values of the previous frame, means for calculating the difference between the input signal and the prediction signal and outputting a prediction error signal, and m (m=1 .2゜3...) A means for forming a set of frames and outputting the pixels of each frame among the m frames in a dot interlaced manner based on a predetermined rule; and a means for outputting in the dot interlaced manner based on a predetermined rule. For speed smoothing, the pixels targeted for encoding are divided into blocks of size p pixels x q lines (p and q are natural numbers), and the encoded signal is matched to the speed of the transmission path. A blocking means that adaptively switches the pXq block size according to the amount of information stored in the buffer memory, and a prediction error signal of each pixel in the block divided by the blocking means. vector quantization encoding means for selecting a vector with a minimum evaluation value among promised vector quantization characteristics and outputting index information of the vector; means for assigning a predetermined code to the index information; and index information. A backup memory that temporarily stores the codes assigned to the above and reads out the stored information at a predetermined transmission speed, and outputs a vector quantization representative value based on the index information that is the output of the vector quantization encoding means. and a local decoding means for adding the vector quantization representative value and the predicted signal.

(Function) The present invention secures the resolution in the still area of a reproduced image by thinning out pixels in a dot interlaced manner, and also without increasing the circuit scale for vector quantization by thinning out pixels in the above-described method. The amount of information generated is suppressed by increasing the block size isometrically and reducing the number of blocks as a result. Furthermore, by adaptively switching the block size and performing vector quantization, the frame drop rate can be lowered compared to the conventional method even when motion becomes large.

This method differs from the conventional method in that it combines the dot interlace method and vector quantization, and in that it adaptively controls the block size in vector quantization.

(Embodiment) FIG. 1 shows an embodiment of the present invention, in which 1 is a chimp signal input terminal, 2 is a linear Φ conversion circuit, 3 is a delay circuit, and 4 is a prediction error signal obtained by subtracting a prediction signal from a television signal input. 5 is a dot interlace and frame drop circuit, 6 is an adaptive blocking circuit, 7 is an average value separation circuit, 8 is a normalization circuit that performs normalization based on the standard deviation within the block, and 9 is a vector quantum circuit. 10 is a multiplexing circuit, 11 is a variable length encoding circuit, 12 is a buffer memory, 13 is a data output terminal, 14 is a vector quantization decoding circuit, 15 is a weighting circuit that performs weighting based on standard deviation. , 16 is an average value addition circuit, 17 is a deblocking circuit, 18 is an addition circuit that reproduces the locally decoded signal between frames, and 19 is an interpolation circuit that interpolates the pixel values of thinned out pixels and dropped fields. , plus a frame memory, 21 a motion detection circuit, n
1 is a variable delay circuit, 0 is a filter, 5 is a delay circuit, 5 is a synchronization separation circuit, and 26 is a clock generation circuit.

First, the TV signal input from the TV signal input terminal 1 is converted from an analog signal into a width conversion circuit 2 for each pixel.
After being converted into a bit PCM signal and delayed by a predetermined delay time necessary for motion detection processing to be described later in a delay circuit 3, the output of the filter B is subtracted in a subtraction circuit 4. The output of the subtraction circuit 4, that is, the prediction error signal, is converted into a prediction error value of the pixel whose encoding is stopped and the field whose frame is to be omitted in the dot interlace and frame drop circuit 5 into 0 or the prediction error value of the previous pixel. Ru. This process consists of the sampling clock, field pulse, frame pulse, and buffer memory 1 which are the outputs of the clock generation circuit.
This is done by the encoded control signal which is the output of 2. FIG. 2 is a diagram for explaining the basic principle of the piece dropping method,
A solid line represents an odd field to be encoded, and a dash-dotted line represents a field from among the odd fields that is dropped when the amount of information stored in the backup memory exceeds a threshold value.

Furthermore, every field of even fields is dropped as shown by the broken line. FIG. 3 is a diagram for explaining the basic principle of the dot interlacing method, in which 0 marks represent encoded pixels for odd frames, and Δ marks represent encoded pixels for even frames.

Although FIG. 3 shows an example in which all pixels are encoded in two frames, it is clear that the dot interlace can be constructed so that all pixels are encoded every n frames.

In addition, in the example in Figure 3, two consecutive frames are set as a set, but only the fields to be encoded, excluding the field to be omitted, shown by the dashed-dotted line in Figure 2, are constructed as a set of two consecutive fields. Then buffer memory 12
Even if frame drop occurs every other frame depending on the amount of stored information, it is possible to avoid a situation in which the pixels marked O or Δ in FIG. 3 remain unencoded forever. The output of the dot interlacing and frame dropping circuit 5 is sent to an adaptive blocking circuit 6.
As the amount of information stored in the buffer memory 12 increases, it is divided into gradually larger blocks, such as 4 pixels x 4 lines, 8 pixels x 8 lines, and 16 pixels x 16 lines, for example. These actually become 2 pixels x 4 lines, 4 pixels x 8 lines, or 8 pixels x 16 lines due to the dot interlacing shown in FIG. The average value separation circuit 7 calculates the average value for each block of input, subtracts the obtained average value from the prediction error value for each pixel, and outputs it to the normalization circuit 8, and also sends the average value information to the multiplexing circuit 10. and is supplied to the average value addition circuit 16. The normalization circuit 8 normalizes the input value using the standard deviation of each block of the output of the mean value separation circuit 7, outputs the normalized output to the vector quantization encoding circuit 9, and sends the standard deviation information to the multiplexing circuit 10 and Weighting is supplied to the circuit. However, when the above-mentioned average value and sample deviation are each below a predetermined threshold value, this block is treated as an invalid block and invalid block identification information is output to the multiplexing circuit 10. The vector quantization encoding circuit 9 converts the value of the input signal for each block into an evaluation value, for example, the absolute value of the difference between the input value for each pixel and the quantized representative value, for each block based on predetermined vector quantization characteristics. The vector with the smallest accumulated value is selected as the optimal vector, and index information representing this optimal vector is supplied to the multiplexing circuit 10 and the vector quantization decoding circuit 14. Note that the vector quantization codebook is switched depending on the size of the block to be adaptively switched. The multiplexing circuit 10 receives average value information supplied from the average value separation circuit 7, standard deviation information and invalid block identification information supplied from the normalization circuit 8, and index information and motion supplied from the vector quantization encoding circuit. Motion vector information supplied from the detection circuit 21 and the clock generation circuit 2
The video frame information etc. supplied from 6 is time-division multiplexed,
The multiplexed data is output to the variable length encoding circuit 11. For each input data, the variable length encoding circuit 11
A variable length code based on a predetermined table is allocated and output to the buffer memory 12. The buffer memory 12 temporarily stores variable length encoded data that is input irregularly, reads out the stored data at a constant transmission line clock, converts it into a signal format on the transmission line, for example, an AMI code, and outputs it to the data output terminal 13. Output. It also calculates the amount of information stored in the backup memory and outputs encoding control information based on this.

The vector quantization decoding circuit 14 outputs a quantized representative value for each pixel in the block based on the input index information. For weighting, the circuit 15 multiplies the input quantized representative value by the standard deviation supplied from the normalization circuit 8 to restore the normalized value. The average value adding circuit 16 adds the average value to the output of the weighting circuit 15. In addition, invalid block identification information is input, and the values of all pixels in the invalid block are set to zero. The deblocking circuit 17 deblocks each block whose size has been adaptively controlled by the adaptive blocking circuit 6, and removes the influence of the circuit configuration in which the size of the block is variable after the addition circuit 18. The adder circuit 18 adds the output of the deblocking circuit 17 and the predicted signal obtained via the delay circuit 17, and outputs a locally decoded signal. An interpolation circuit 19 interpolates the values of pixels subjected to dot interlacing and field omission. For pixels thinned out by dot interlacing, there are various methods such as interpolating pixels in a still area with pixel values at the same position in past frames, and interpolating pixels in a moving area using values of neighboring pixels. is possible. Furthermore, various methods such as interpolation using the arithmetic average of the preceding and following fields are possible even for pixels whose field has been omitted. Frame memory 4 is interpolation circuit 1
9 is delayed by about one frame period. The motion detection circuit 21 divides the input signal supplied from the ~Φ conversion circuit 2 into blocks of, for example, 16 pixels x 16 lines, and calculates the optimal prediction block for the input block from the neighboring area of the encoded past frame. The block is selected from among the blocks, and motion vector information representing the optimum predicted block is output to the variable delay circuit n, the interpolation circuit 19, and the multiplexing circuit 10. There are various methods for detecting the optimal predicted block, such as a full search method in which all blocks within the motion compensation range are searched, and any of these methods can be easily realized by a company involved in this type of system. The variable delay circuit n selects and outputs pixel values within the block specified by the motion vector information output from the motion detection circuit 21 from the output of the frame memo IJ 20. The filter performs spatial digital filter processing on the output of the variable delay circuit B to suppress quantization noise at the edges caused by vector quantization. The delay circuit group delays the output of filter B by the same amount of time as the time required for processing from the subtraction circuit 4 to the addition circuit 18.

The synchronization separation circuit 25 separates, for example, a horizontal synchronization signal and a vertical synchronization signal from the input television signal. Clock generation circuit 26
generates, for example, a sampling clock phase-synchronized with the horizontal synchronization signal, a waveform-shaped horizontal synchronization pulse, a frame pulse, etc., and outputs them to each circuit that requires them.

The above explanation describes a monochrome television signal, but the NTSC color television signal is separated into a luminance signal and a color signal, the separated color signal is compressed on the time axis, and this color signal is added to the horizontal blanking period of the luminance signal. It is clear that the present invention can be applied to time division multiplexed signals (TDM signals).

(Effects of the Invention) As explained above, by combining the dot interlacing method that reduces the number of encoded pixels and the vector quantization method, the block size can be adjusted to the same constraint without increasing the circuit scale of vector quantization. This has the advantage that the amount of information generated can be reduced by reducing the number of blocks.

Furthermore, since the dot interlacing method is adopted, there is an advantage that the resolution of the still area can be ensured.

Furthermore, since the size of the block, which is the unit of vector quantization, is adaptively switched, it is possible to suppress the increase in the amount of information generated even when the movement becomes large.
There is an advantage that the frame drop rate of field frame drop used when the amount of information generated increases.

[Brief explanation of drawings]

FIG. 1 is an embodiment of the present invention, FIG. 2 is a diagram for explaining the basic principle of the frame dropping method, and FIG. 3 is a diagram for explaining the basic principle of the dot interlacing method. 1... TV signal input terminal, 2... conversion circuit of ~,
3.24...Delay circuit, 4...Subtraction circuit, 5...
dot interlacing and frame dropping circuit, 6... adaptive blocking circuit, 7... average value separation circuit, 8... normalization circuit, 9... vector quantization coding circuit, 10...
Multiplexing circuit, 11... Variable length encoding circuit, 12...
Buffer memory, 13...Data output terminal, 14...
・Vector quantization decoding circuit, 15... Weighting circuit,
16...Average value addition circuit, 17...Deblocking circuit, 18...Addition circuit, 19...Interpolation circuit, addition...
・Frame memory, 21...Motion detection circuit, n...
variable delay circuit, n... filter, 5... synchronous separation circuit, 26... clock generation circuit.

Claims (1)

[Claims] For digitized television signal input, n (n=0
, 1, 2...) means for configuring a prediction signal from the pixel values of the previous frame; means for calculating the difference between the input signal and the prediction signal and outputting a prediction error signal; m=1,
2, 3...) A means for forming a set of frames and outputting the pixels of each frame among the m frames in a dot interlaced manner based on a predetermined rule, and encoding by the means for outputting in a dot interlaced manner p
It is divided into blocks each having a size of pixels x q lines (p and q are natural numbers), and p is calculated according to the amount of information stored in the speed smoothing buffer memory for matching the coded signal to the speed of the transmission path. Blocking means for adaptively switching the block size of ×q Evaluate among vector quantization characteristics promised in advance for the combination of prediction error signals of each pixel in the block divided by the blocking means vector quantization encoding means for selecting a vector with a minimum value and outputting index information of the vector; means for assigning a predetermined code to the index information; temporarily storing the code assigned to the index information, etc.;
a buffer memory for reading stored information at a predetermined transmission rate; a vector quantization decoding means for outputting a vector quantization representative value based on index information that is an output of the vector quantization encoding means; An interframe coding method comprising local decoding means for adding a representative value and the predicted signal.