JPS6263327A - Oscillation circuit of microcomputer - Google Patents
Oscillation circuit of microcomputerInfo
- Publication number
- JPS6263327A JPS6263327A JP60202931A JP20293185A JPS6263327A JP S6263327 A JPS6263327 A JP S6263327A JP 60202931 A JP60202931 A JP 60202931A JP 20293185 A JP20293185 A JP 20293185A JP S6263327 A JPS6263327 A JP S6263327A
- Authority
- JP
- Japan
- Prior art keywords
- microcomputer
- output
- delay circuits
- oscillation circuit
- shift registers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Manipulation Of Pulses (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、発振周波数に一定範囲のジッタを持たせて放
射ノイズを低減するマイクロコンピュータの発振回路に
関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an oscillation circuit for a microcomputer that reduces radiation noise by adding jitter within a certain range to the oscillation frequency.
近年、自動車の各種制御にマイクロコンピュータが広く
使われているが、この場合マイクロコンピュータの水晶
発振回路から高周波ノイズが生じて近隣のラジオ受信機
等に電磁妨害(EMC)を与えることがある。この対策
として従来はLC。In recent years, microcomputers have been widely used to control various types of automobiles, but in this case, high-frequency noise is generated from the microcomputer's crystal oscillation circuit, which can cause electromagnetic interference (EMC) to nearby radio receivers and the like. The conventional solution to this problem is LC.
RCのフィルタ回路網またはシールド板等により高周波
ノイズがマイクロコンピュータ使用の13711器から
外部へ漏れないようにすることが多い。第4図はその一
例で、1はマイクロコンピュータ、2はそれを使用した
制御器、L、Cは高周波阻止フィルタを構成するインダ
クタンスおよびコンデンサである。High frequency noise is often prevented from leaking outside from a 13711 device using a microcomputer by using an RC filter network or a shield plate. FIG. 4 shows an example of this, where 1 is a microcomputer, 2 is a controller using the microcomputer, and L and C are an inductance and a capacitor that constitute a high frequency blocking filter.
ところが、上述した2MC対策は高周波ノイズそのもの
の発生を阻止している訳ではないので不完全な要素も多
い。本発明はこの点を根本的に改善しようとするもので
ある。However, the above-mentioned 2MC countermeasure does not prevent the generation of high frequency noise itself, and therefore has many imperfections. The present invention attempts to fundamentally improve this point.
本発明は、マイクロコンピュータで使用するクロックを
発生する固定周波数の発振回路において、原振の出力を
一定範囲内でジッタを持たせることを特徴とするもので
ある。The present invention is characterized in that, in a fixed frequency oscillation circuit that generates a clock used in a microcomputer, the output of the original oscillation has jitter within a certain range.
第1図は本発明の原理説明図で、(a)は基本波f。 FIG. 1 is a diagram explaining the principle of the present invention, and (a) shows the fundamental wave f.
に対する高調波2・fo、・・・・・・n−fo、・・
・・・・のスペクトラムである。この場合のように基本
波fa″”−の周波数が一定値に固定されていると特定
の高調波がノイズとなる。同図(b)はその部分拡大図
である。ソコで、基本波foの周波数を制御精度に影響
しない範囲でランダムに変動させると、高周波スペクト
ラムは同図(C)のように分散して各波高値が低下する
。この結果、外部に対する高周波ノイズの影響は低減す
る。基本波fOの周波数変動はマイクロコンピュータの
リード/ライト(R/W)サイクルにより乱数的に行う
ことができる。harmonics 2・fo,...n-fo,...
It is a spectrum of... If the frequency of the fundamental wave fa''''- is fixed to a constant value as in this case, specific harmonics become noise. FIG. 6B is a partially enlarged view of the same. If the frequency of the fundamental wave fo is randomly varied within a range that does not affect the control accuracy, the high frequency spectrum will be dispersed as shown in FIG. As a result, the influence of high frequency noise on the outside is reduced. The frequency of the fundamental wave fO can be varied randomly using read/write (R/W) cycles of the microcomputer.
第2図は本発明の一実施例を示すブロック図で、10は
マイクロコンピュータを用いた制御部、11は周波数f
oの水晶発振回路である。この発振回路(CRでもよい
)11の出力fOをそのまま制御部10に入力するのが
従来の方法であるが、本例ではスイッチSW+〜SW!
1で選択される遅延回路12+〜125を介在させ、そ
れをシフトレジスタ13の出力で選択する。そして、オ
アゲ−)C;+によって周波数がfO付近で変動する出
力r1に合成してから制御部10に入力する。遅延回路
121〜125の遅延時間TD+〜TDsは第3図のよ
うにランダムに設定しておき、それをraをクロック(
CK)とするシフトレジスタ13の並列出力で順番に選
択する。但し、このシフトレジスタ13はマイコン制御
部10からのリード/ライトf言号R/Wがライトモー
ドになるとクリアされ、各段のフリップフロップFF+
〜FF4の出力S W +〜SW4をオールOにする(
これらの出力は1で該当するスイッチをオンにする)。FIG. 2 is a block diagram showing an embodiment of the present invention, in which 10 is a control unit using a microcomputer, 11 is a frequency f
This is a crystal oscillation circuit of o. The conventional method is to input the output fO of this oscillation circuit (CR may be used) 11 as it is to the control unit 10, but in this example, the switches SW+ to SW!
Delay circuits 12+ to 125 selected by 1 are interposed, and the delay circuits 12+ to 125 are selected by the output of the shift register 13. Then, the signal is combined with the output r1 whose frequency fluctuates around fO by C;+, and then input to the control unit 10. The delay times TD+ to TDs of the delay circuits 121 to 125 are set randomly as shown in FIG.
CK) are selected in order by the parallel outputs of the shift register 13. However, this shift register 13 is cleared when the read/write f word R/W from the microcomputer control unit 10 enters the write mode, and the flip-flop FF+ of each stage is cleared.
~Output SW of FF4 +~Set SW4 to all O (
These outputs turn on the corresponding switch at 1).
この結果オアゲー)02の出力が01インバータIの出
力が1となって初段のフリップフロップFF1にlがセ
ットされる。従って、マイコン制御部10のリード/ラ
イトサイクルのランダム性により遅延時間の選択もラン
ダムになる。例えば1回目はSW I、SW2.SW3
までオンになり、ここでクリアされて次はSW+ 、S
W2だけがオンとなってクリアされる、・・・・・・と
いう様にである。As a result, the output of the OR game) 02 becomes 01, and the output of the inverter I becomes 1, and 1 is set in the first stage flip-flop FF1. Therefore, due to the randomness of the read/write cycle of the microcomputer control section 10, the selection of the delay time is also random. For example, the first time is SW I, SW2. SW3
It is turned on until it is cleared, and then SW+, S
Only W2 is turned on and cleared, and so on.
遅延回路125はシフシトレジスタ13のクリア期間に
クロックを出すためのもので、そのスイッチSW5はオ
アゲートG2の出力が0になるとオンになる。The delay circuit 125 is for outputting a clock during the clearing period of the shift register 13, and its switch SW5 is turned on when the output of the OR gate G2 becomes 0.
上述した回路によって得られる周波数f+は、短期的に
は水晶原振fOにθ〜10%程度の周波数のゆらぎを持
たせ、長期的は一定の平均値になるようにしたものであ
るので、マイコン制御部10の制御精度に影響を与える
ことなく、高調波のスペクトラム分布を分散させること
ができる0、尚、遅延回路、シフトレジスタ等はマイク
ロコンピュータに内蔵させてもよい。The frequency f+ obtained by the above-mentioned circuit is obtained by making the crystal original oscillation fO have a frequency fluctuation of about θ~10% in the short term, and keeping it at a constant average value in the long term. The spectral distribution of harmonics can be dispersed without affecting the control accuracy of the control unit 10. Note that the delay circuit, shift register, etc. may be built into the microcomputer.
以上述べたように本発明によれば、マイクロコンピュー
タで使用する発振回路が周辺機器に対して与える電磁波
妨害を、その高調波成分のスペクトラム分布を分散させ
ることで低減できる利点がある。As described above, according to the present invention, there is an advantage that electromagnetic interference caused by an oscillation circuit used in a microcomputer to peripheral equipment can be reduced by dispersing the spectrum distribution of its harmonic components.
第1図は本発明の原理説明図、第2図は本発明の一実施
例を示すブロック図、第3図はその動作を示すタイムチ
ャート、第4図は従来の高周波ノイズ対策の説明図であ
る。
図中、10はマイクロコンピュータを用いた制御部、1
.1は水晶発振回路、121〜125は遅延回路、SW
+〜SW5はその選択スイッチ、13はシフトレジスタ
である。Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is a block diagram showing an embodiment of the invention, Fig. 3 is a time chart showing its operation, and Fig. 4 is an explanatory diagram of a conventional high-frequency noise countermeasure. be. In the figure, 10 is a control unit using a microcomputer;
.. 1 is a crystal oscillation circuit, 121 to 125 are delay circuits, SW
+ to SW5 are selection switches, and 13 is a shift register.
Claims (1)
定周波数の発振回路において、原振の出力を一定範囲内
でジッタを持たせることを特徴とするマイクロコンピュ
ータの発振回路。An oscillation circuit for a microcomputer that is characterized in that, in a fixed frequency oscillation circuit that generates a clock used in a microcomputer, the output of the original oscillation has jitter within a certain range.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60202931A JPS6263327A (en) | 1985-09-13 | 1985-09-13 | Oscillation circuit of microcomputer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60202931A JPS6263327A (en) | 1985-09-13 | 1985-09-13 | Oscillation circuit of microcomputer |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6263327A true JPS6263327A (en) | 1987-03-20 |
Family
ID=16465530
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60202931A Pending JPS6263327A (en) | 1985-09-13 | 1985-09-13 | Oscillation circuit of microcomputer |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6263327A (en) |
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5781742A (en) * | 1994-08-30 | 1998-07-14 | International Business Machines Corporation | Data transfer system interconnecting a computer and a display device |
JP2001068979A (en) * | 1999-07-19 | 2001-03-16 | Mannesmann Vdo Ag | Modulating method for base clock for digital circuit and clock modulator |
JP2001068980A (en) * | 1999-07-19 | 2001-03-16 | Mannesmann Vdo Ag | Modulating method of base clock for digital circuit and modulator |
JP2002500451A (en) * | 1997-09-04 | 2002-01-08 | シリコン・イメージ,インコーポレーテッド | A controllable delay device for a plurality of synchronization signals to reduce electromagnetic interference at peak frequencies. |
US6822499B2 (en) | 2002-06-11 | 2004-11-23 | Oki Electric Industry Co., Ltd. | Clock modulating circuit |
JP2005274782A (en) * | 2004-03-23 | 2005-10-06 | Kawai Musical Instr Mfg Co Ltd | Electronic musical sound generator |
JP2007259435A (en) * | 2006-03-20 | 2007-10-04 | Samsung Electronics Co Ltd | Method, circuit, and system for generating delayed high frequency clock signal used for spread spectrum clocking |
JP2008171393A (en) * | 2006-12-14 | 2008-07-24 | Seiko Epson Corp | Signal bus, multilevel input interface, and information processor |
JP2008306699A (en) * | 2007-06-11 | 2008-12-18 | Hynix Semiconductor Inc | Frequency adjusting apparatus and dll circuit including same |
US7515646B2 (en) | 2004-02-05 | 2009-04-07 | Lexmark International, Inc. | Method and apparatus for reducing EMI emissions for data signals traveling over a data pathway |
JP2009180732A (en) * | 2008-01-30 | 2009-08-13 | Advantest Corp | Jitter application circuit, pattern generator, test apparatus, and electronic device |
WO2012017732A1 (en) * | 2010-08-03 | 2012-02-09 | ザインエレクトロニクス株式会社 | Transmitting device, receiving device and transmitting/receiving system |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5995742A (en) * | 1982-10-20 | 1984-06-01 | プリントロニクス・インコ−ポレ−テツド | Electronic device having low radio wave disturbance from system clock signal |
-
1985
- 1985-09-13 JP JP60202931A patent/JPS6263327A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5995742A (en) * | 1982-10-20 | 1984-06-01 | プリントロニクス・インコ−ポレ−テツド | Electronic device having low radio wave disturbance from system clock signal |
Cited By (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5793988A (en) * | 1994-08-30 | 1998-08-11 | International Business Machines Corporation | Parallel data transfer system and method utilizing different modulating waveforms |
US5781742A (en) * | 1994-08-30 | 1998-07-14 | International Business Machines Corporation | Data transfer system interconnecting a computer and a display device |
JP2002500451A (en) * | 1997-09-04 | 2002-01-08 | シリコン・イメージ,インコーポレーテッド | A controllable delay device for a plurality of synchronization signals to reduce electromagnetic interference at peak frequencies. |
JP2001068979A (en) * | 1999-07-19 | 2001-03-16 | Mannesmann Vdo Ag | Modulating method for base clock for digital circuit and clock modulator |
JP2001068980A (en) * | 1999-07-19 | 2001-03-16 | Mannesmann Vdo Ag | Modulating method of base clock for digital circuit and modulator |
US6822499B2 (en) | 2002-06-11 | 2004-11-23 | Oki Electric Industry Co., Ltd. | Clock modulating circuit |
US7515646B2 (en) | 2004-02-05 | 2009-04-07 | Lexmark International, Inc. | Method and apparatus for reducing EMI emissions for data signals traveling over a data pathway |
JP2005274782A (en) * | 2004-03-23 | 2005-10-06 | Kawai Musical Instr Mfg Co Ltd | Electronic musical sound generator |
JP2007259435A (en) * | 2006-03-20 | 2007-10-04 | Samsung Electronics Co Ltd | Method, circuit, and system for generating delayed high frequency clock signal used for spread spectrum clocking |
JP2008171393A (en) * | 2006-12-14 | 2008-07-24 | Seiko Epson Corp | Signal bus, multilevel input interface, and information processor |
JP2008306699A (en) * | 2007-06-11 | 2008-12-18 | Hynix Semiconductor Inc | Frequency adjusting apparatus and dll circuit including same |
JP2009180732A (en) * | 2008-01-30 | 2009-08-13 | Advantest Corp | Jitter application circuit, pattern generator, test apparatus, and electronic device |
WO2012017732A1 (en) * | 2010-08-03 | 2012-02-09 | ザインエレクトロニクス株式会社 | Transmitting device, receiving device and transmitting/receiving system |
CN102959862A (en) * | 2010-08-03 | 2013-03-06 | 哉英电子股份有限公司 | Transmitting device, receiving device and transmitting/receiving system |
KR101443467B1 (en) * | 2010-08-03 | 2014-09-22 | 쟈인 에레쿠토로닉스 가부시키가이샤 | Transmitting device, receiving device, and transmitting/receiving system |
CN102959862B (en) * | 2010-08-03 | 2016-05-18 | 哉英电子股份有限公司 | Dispensing device, receiving system and receive-transmit system |
US9991912B2 (en) | 2010-08-03 | 2018-06-05 | Thine Electronics, Inc. | Transmitting device, receiving device and transmitting/receiving system |
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