JPS6255240B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device that incorporates a test circuit to enable faster testing and automatic redundancy switching based on test results.

Semiconductor memory devices have “0” or “1”
There is a so-called static memory device in which binary information is held in memory cells that correspond to bits and have a bistable state in terms of circuitry. FIG. 1 is a circuit diagram of a memory cell in a static memory device. The figure shows the case where it is configured with CMOS transistors, and 1a, 1b, 1c and 1d are n-channels.
MOS transistors, 2a and 2b are p channel
It is a MOS transistor. 3 is a word line for selecting the memory cell, and 4a and 4b are bit lines. The word line and the bit line interconnect a plurality of memory cells to form a cell array. In the figure, 5a and 5b are the first and second nodes of the memory cell, and usually the first
When the node 5a is in the "L" state equal to the ground potential, the second node 5b is in the "H" state equal to the power supply potential _VDD . Also, the first node 5
When a is in the "H" state, the second node 5b is in the "L" state, and the first node 5a and the second node 5b assume two stable states at opposite potentials. Therefore, in a static type memory device, information of "0" or "1" is held in correspondence with a bit in a memory cell that can take these two stable states.

The operation when reading or writing information to this memory cell will be described below. In order to read or write to a memory cell, the word line 3 connected to the memory cell is set to the "H" state, and the first and second bit lines 4a, 4b are connected to the first and second bit lines 4a, 4b. 2 nodes 5a, 5
The transistors 1a and 1b between the transistors 1b and 1b are made conductive. This state is the selected state of the memory cell.
At the time of reading, the potentials of the first and second nodes 5a and 5b of the memory cell in the selected state cause the bit lines 4a and 4 connected to the memory cell to be connected to each other.
A potential difference is generated between the memory cell and the memory cell, and by detecting this potential difference, the information held in the memory cell is read out. For writing, one of the bit lines 4a and 4b connected to the selected memory cell is set to the "H" state and the other is set to the "L" state, and the potential of the bit line is used to set the first bit line of the memory cell. The potentials of the first and second nodes 5a and 5b are set.

A semiconductor memory device having such a structure is
By repeating the process of forming conductive patterns, insulating layers, etc. on a silicon single crystal substrate using photolithography, a chip with transistors and wiring is manufactured. Although these processes are usually performed in a dust-free chamber, it is difficult to significantly reduce defects that occur on the substrate during the manufacturing process. For this reason, after the manufacturing process is completed, it is necessary to test whether or not there are any defects in the chips, and to select non-defective products.

Testing methods for semiconductor memory cell devices include the all-0/all-1 scan R/W method,
Marching method, gearing method, etc. are known as conventional methods. A common feature of these test methods is that a test device is prepared outside the semiconductor memory device, the test device generates an address signal for selecting a specific memory cell in the semiconductor memory device, and the address signal is used to select a specific memory cell in the semiconductor memory device. Therefore, information of "0" or "1" is applied to the selected memory cell as a data signal to perform writing or reading. Therefore, information is repeatedly written or read in units of one bit or several bits for each internal state that is a combination of information "0" or "1" written in the cell array. For this reason, in a semiconductor memory device with a storage capacity of N bits, tests must be performed by changing the order of selected addresses and read/write combinations for each possible internal state ( ^2N) . There was a problem in that an enormous amount of testing time was required when the capacity increased.

Currently, advances in microfabrication technology for integrated circuits have dramatically increased the amount of circuitry that can be integrated onto a single chip. It has become possible to collect them all at once. However, 1
When memory devices and logic devices are integrated on a single chip, it is difficult to directly extract all the address signals and data signals of the memory device to the outside of the chip due to limitations such as the number of pins provided on the chip. . For this reason, when memory devices and logic devices are integrated together, conventional testing methods require complicated procedures to realize all internal states within the memory device.

On the other hand, as a conventional technique for relieving defects that occur during the manufacturing of integrated circuits and enabling large-scale integration, a redundant switching method is proposed in which a spare circuit is provided in a semiconductor memory device and a defective circuit is switched to the spare circuit. Means for dealing with defects are known. For example, Tokugansho
No. 50-58206 discloses that a semiconductor memory device is composed of a plurality of units consisting of a basic unit and a spare unit, and that if a defect exists in the basic unit and it does not function properly, the basic unit can be replaced by the spare unit. discloses a method for remediating defects. In this conventional method, each unit is tested from outside the chip constituting the semiconductor memory device, and redundancy switching is performed based on the test results obtained for each unit, so there is a problem that defect relief cannot be automated.

In this way, today's integrated circuits have become larger and larger, and semiconductors are now equipped with the ability to detect the presence or absence of defects in a short time and with a high detection rate without exchanging address signals or data signals with the outside of the chip. A memory device is desired.

SUMMARY OF THE INVENTION In order to eliminate the problems of the prior art, an object of the present invention is to incorporate a means for detecting the presence or absence of defects in a semiconductor memory device, and to efficiently detect defects in a short time using a simple test procedure. An object of the present invention is to provide a semiconductor memory device that performs detection and automates redundancy switching based on the obtained test results.

The present invention will be explained in detail below using examples.

In order to achieve the above object, the present invention has a configuration in which the potentials of the first and second nodes of the memory cells constituting the semiconductor memory device can be detected regardless of the selected or non-selected state of the memory cells, This makes it easier to test semiconductor memory devices, and allows built-in test circuits and faster testing.

FIG. 2 is a circuit diagram of a memory cell forming a semiconductor memory device according to an embodiment of the present invention. The figure shows the case where it is configured with CMOS transistors.
6a and 6b are first and second transistors, 7a and 7b are first and second detection lines, and all others are the same as the conventional memory cell shown in FIG. Here, the gates of the first and second transistors 6a and 6b are respectively connected to the first and second nodes 5a and 5b, and the potentials of the first and second nodes 5a and 5b depend on the potentials of the first and second nodes 5a and 5b. Thus, the source-drain region is controlled to be either conductive or disconnected. In this embodiment, the first and second transistors 6a,
6b is grounded, and the potentials of the first and second nodes 5a and 5b are set to the first and second nodes regardless of whether the memory cell is selected or not by the word line.
Detection lines 7a and 7b are used for detection.

FIG. 3 is a configuration diagram of a memory cell group in which a plurality of memory cells shown in FIG. 2 are connected to form a test circuit. In addition, the part 8 surrounded by a broken line in the figure is
This is the memory cell shown in FIG.
Only the second transistors 6a, 6b and the first and second detection lines 7a, 7b are shown, and the others are omitted. 9a and 9b are pull-up circuits for the first and second detection lines 7a and 7b, and the first and second transistors 6a and 6b connected to the detection lines 7a and 7b and these 9a and 9b
and constitute first and second NOR gates, respectively. 10 is an E _x NOR gate, the first
The output of the NOR gate and the output of the second NOR gate are connected. Reference numeral 11 denotes a memory cell group, which includes a plurality of memory cells 8, pull-up circuits 9a, 9b, and an E _x NOR gate 10. 12 is a signal line that provides the test timing TE1, and a logic symbol 13 provided on the signal line is an inverter. The test result is obtained as the output of the _E
4 is in the "H" state, it is taken into the flag register 15. 16 is an output line of the flag register 15.

Next, the operation of the test means using this test circuit will be explained. Before performing the test, the flag register 15 for holding the test results is reset in advance. Thereafter, "0" or "1" information is written into each memory cell 8 constituting the memory cell group 11. Next, by setting the test timing signal TE1 to the "H" state, the first and second detection lines 7a and 7b are connected to the NOR logic regarding the first node 5a of the memory cell 8 connected to the test line. A NOR logic regarding node 5b of 2 is obtained. At this time, if information is normally written to all of the memory cells 8 and is normally retained,
The potentials of the first and second detection lines 7a and 7b show opposite potentials, with one being in the "H" state and the other being in the "L" state. However, if there is a defect in the word line, bit line, write circuit, or memory cell related to the memory cell group and the memory cell group does not function normally, the first and second detection Both lines 7a and 7b are in the "L" state. Therefore, the first detection line 7a
By applying E _x NOR logic between
A test result is obtained indicating that a defect exists in the memory cell group, and that no defect exists when the memory cell group is in the "L" state. The obtained test result is the test timing signal
TE2 is set to the "H" state, and the test result is stored in the flag register 15, which is a holding means.

FIG. 4 is an overall configuration diagram of the semiconductor memory device of this embodiment. 17 is a cell array, 18 is an address signal line, 19 is a word line selection circuit, 20 is an input line for test timing TE0, 21 and 22 are test data setting lines TD0 and TD1, 23 is a read/write switching signal line R/W, 24 is a redundant switching circuit
SW, 25a, 25b, 25c are internal data lines,
26a and 26b are input/output data lines, and 27 is a test result signal line. In this embodiment, the cell array 17
consists of three memory cell groups 11a, 11b, and 11c, two of which are basic memory cell groups and the remaining one is a spare memory cell group.
Each memory cell group 11a, 11b, 11c
consists of a plurality of memory cells shown in FIG. 2, and these memory cells constitute the test circuit shown in FIG. 3. Also, memory cell groups 11a, 11
b, 11c is provided with an input/output circuit 28 (I/O) for writing information into the memory cell and reading information from the memory cell.

5 to 7 show the word line selection circuit 19, input/output circuit 28, and redundancy switching circuit 2 in FIG.
4 is a configuration diagram.

FIG. 5 shows a word line selection circuit equipped with selection means for selecting a plurality of word lines at once. Reference numeral 29 in the figure represents an address decoder for selecting one of the word lines 3 based on the address signal AD applied from the address signal line 18. The logic symbol 30 is a NOR gate, and together with the inverter 13 at the subsequent stage, realizes the OR logic between the output signal of the address decoder 29 and the test timing signal TE0 applied from the input line 20. As a result, when the test timing signal TE0 is in the "H" state, all word lines 3 are in the "H" state.
state, and all memory cells connected to the word line become selected. Therefore, when the test timing signal TE0 is in the "H" state, a plurality of memory cells connected to the word line selected by the word line selection circuit are collectively set to "0" or "1". It is possible to write the following information.
On the other hand, when the test timing signal TE0 is in the "L" state, only one word line is selected as specified by the address signal AD applied from the address signal line 18, and a specific memory is selected based on the selected state. Information can be written to and read from cells.

Figure 6 shows that “0” or “1” is present in the cell array.
FIG. 2 is a configuration diagram of an input/output circuit 28 equipped with a writing means for collectively writing information of the following information. 31 is a sense amplifier circuit, 32 is a tristate gate, 33a and 33b are write transistors, and 34a and 34b are data setting transistors. A feature of this circuit is that, in addition to the so-called read and write operations in conventional semiconductor memory devices, it enables batch write operations for the purpose of executing tests in a short time. During read operation, that is, switching signal line 23
The read/write switching signal R/
When W is in the "H" state, the potentials of the first and second nodes of the memory cell selected by the word line 3 are input to the sense amplifier circuit 31 via the bit line 4a and bit line 4b, and Depending on whether the result of amplification by the sense amplifier circuit 31 is in the "L" state or the "H" state, it is read as "0" or "1" information, respectively. When the read/write switching signal R/W is in the "H" state, the tristate gate 32 becomes conductive, the output of the sense amplifier circuit 31 is obtained on the internal data line 25, and the read operation is completed.

During a write operation, that is, when the read/write signal R/W is in the "L" state, the write transistors 33a and 33b are driven based on the information given to the internal data line 25, and the bit line 4a or the bit line 4b is The potential of either one is set to the "L" state, which is equal to the ground potential. That is, when the internal data line 25 is in the "L" state, the bit line 4a is brought into the "L" state, and the bit line 4a is in the "L" state.
Let b be in the "H" state. On the other hand, when the internal data line is in the "H" state, the bit line 4a is brought into the "H" state and the bit line 4b is brought into the "L" state. Rewriting the potentials of the first and second nodes of the memory cell connected to the bit line 4a and bit line 4b set to opposite potential states and selected by the word line 3. According to
Perform a write operation.

During batch write operation, test data setting line 2
1, 22, test data setting signals TD0, TD
Give 1. At this time, the test data setting signal TD
0, TD1 is set to the "H" state, either the data setting transistor 34a or 34b is set to the conductive state, and the internal data lines 25 are collectively set to the "L" state or the "H" state. In such a state, by setting the test timing signal TE0 applied from the input line 20 to the "H" state, a plurality of sets of bit lines are simultaneously set to the write state. Therefore, by using this input/output circuit and the word line selection circuit 19 described in FIG. The same information can be written to all memory cells at once.

FIG. 7 is a configuration diagram of the redundant switching circuit SW24, which is the switching means in this embodiment. In the figure, logic symbols 35, 36, 37, and 38 are an AND gate, an OR gate, an _EXOR gate, and a transfer gate, respectively. 16a, 16
b, 16c are flag registers 15, respectively.
a, 15b, 15c, and three memory cell groups 11a, 11b, configuring the cell array.
11c test results are output. Based on the test results of the three memory cell groups, this circuit connects the internal data line 25 to which input/output signals of the memory cell groups are sent.
a, 25b, 25c and the input/output data lines 26a, 26b of this memory device.
of3) has the function of redundant switching. That is, memory cell group (A) 1 which is a basic memory cell group
1a and the memory cell group (B) 11b, both the output lines 16a and 16b of the flag register are in the "L" state, and the internal data line 25a is connected to the input/output data line 26a and Internal data line 25b is connected to input/output data line 26b via transfer gates 38, respectively. There is a defect in memory cell group (B) 11b, and other memory cell group (A) 11a and memory cell group (C) 1
If there is no defect in 1c, the output lines 16a, 16b, and 16c of the flag register become 0, 1, and 0, respectively, and the internal data line 25a is connected to the input/output data line 26a, and 25c is connected to 26b, indicating that there is no defect. The internal data line 25b of the memory cell group (B) that exists and does not function normally is not subject to input/output. In this way, if only one arbitrary memory cell group out of the three memory cell groups does not function normally, the semiconductor memory device will function normally with the help of the other two normally functioning memory cell groups. Defects will be remedied. If two or more of the three memory cell groups do not function normally, an "H" state is obtained on the test result signal line 27, and it can be detected that the semiconductor memory device is unusable.

Next, a procedure for testing and redundancy switching of the semiconductor memory device of this embodiment shown in FIG. 4 will be explained. FIG. 8 is an operation timing diagram of the test circuit built into the semiconductor memory device. The signals required for the test are:
RST, TD0, TD1, TE0, TE1, TE2 6
Of these, TD0, TD1, TE0, TE
1, TE2 are the same as shown in FIG.
The RST signal is transmitted to flag registers 15a, 15b,
This is a signal for resetting 15c to "0" as an initial state, and is omitted in FIG. Further, the () signal is a test end signal of the built-in test circuit.

Test procedure Set flag register reset signal RST to “H”
As a state, flag registers 15a, 15b, and 15c, which are means for holding test results, are reset. This state is the same as a state in which there is no defect in any of the memory cell groups and the memory cells are functioning normally.

Test data setting signal TD0 is set to "H" state, TD1 is set to "L" state, and test timing signal TE0 is set to "H" state. At this time, all internal data lines are in the "L" state, and "0" information is written in each memory cell group in the memory device at once.

The test timing signal TE1 is set to "H" state. At this time, each memory cell group is inspected by the inspection circuit shown in FIG. 3 to see if information is correctly written and retained in the memory cells constituting the memory cell group.

The test timing signal TE2 is set to "H" state. At this time, the test result obtained in is held in the flag register. The content held is in the "H" state when the memory cell group does not function normally, and is in the "L" state when it is functioning normally.

Set test data setting signal TD0 to “L” state.
1 is in the "H" state, and the test timing TE0 is in the "H" state. At this time, all internal data lines are in the "H" state, and "1" information is written in each memory cell in the semiconductor memory device at once.

Similarly, test timing signal TE1
The memory cell is inspected by setting the signal to the "H" state.

Similarly, the test timing signal TE2 is set to the "H" state, and the test result obtained in is taken into the flag register 15. At this time, the flag registers 15a, 15b, 15c have already been set.
If the "H" state is maintained, the flag register is set to "H" regardless of the test result.
Leave it as it is. If a defect is detected in the memory cell group by this or at least one of the tests, the "H" state is set in the flag registers 15a, 15b, and 15c, and the memory cell group does not function normally. It can be determined that

The test is ended by setting the test end signal () to "H" state.

By carrying out the above procedure, the memory cell group
Test results for (A), memory cell group (B), and memory cell group C are obtained. Therefore, in the redundancy switching circuit 24 shown in FIG. 7, redundancy switching can be automatically performed based on the obtained test results.

In the semiconductor memory device of this embodiment described above, as shown in FIG. 3, the first and second test lines constitute a NOR gate by the first and second transistors 6a and 6b provided for each memory cell. However, the test circuit can also be configured with a NAND gate formed by the first and second transistors 6a and 6b.

FIG. 9 is also a configuration diagram of a test circuit which is an embodiment of the present invention. A portion 8 surrounded by wiring in the figure is a memory cell, and the first and second nodes 5a,
5b and first and second transistors 6a, 6b
only is shown. Reference numerals 9a and 9b are pull-up circuits that connect the first and second transistors 6a and 6.
The sources of the memory cells 8 and 8 are sequentially connected to the drains of adjacent memory cells 8 to form first and second NAND gates, respectively, and the NAND gates are used to check whether the memory cells are functioning normally. 1st
The output of the NAND gate becomes "L" only when all of the first transistors 6a constituting the NAND gate become conductive. second
Similarly to the first NAND gate, the output of the NAND gate also becomes "L" only when all of the second transistors 6b constituting the NAND gate become conductive. Therefore, the first and second
By performing an exclusive OR between the outputs of the NAND gates using the E _x NOR circuit 10, it is possible to check whether the same information is correctly written and held in all memory cells constituting the memory cell group. The rest of the circuit configuration of this embodiment is the same as that shown in FIG. Therefore, the test circuit
Even when configured with NAND gates, automatic defect relief can be carried out using the built-in test circuit as in the previous embodiment.

Note that in the configuration of the semiconductor memory device shown in FIG. 4, the memory cell group constituting the test circuit is used as the unit of switching when redundant switching is performed, but it is possible to test multiple memory cell groups so that redundant switching is performed at the same time. Automatic defect relief is possible even in a configuration where the circuit targeted for switching is different from the circuit targeted for switching.

As explained above, in the semiconductor memory device of the present invention, by providing a transistor for defect inspection in each of the memory cells constituting the cell array, it is possible to incorporate a test circuit, and it is simple and fast. Testing becomes possible. For this reason, even for semiconductor memory devices that require complicated testing with conventional testing methods, such as large-capacity semiconductor memory devices or cases where memory devices and logic devices are mixed on one chip, it is possible to test them quickly and easily. The test can be conducted using a standard procedure. Further, by applying a redundant configuration to the cell array of the semiconductor memory device, automatic redundancy switching based on self-defect detection is possible. Therefore, the rate of non-defective semiconductor memory devices can be significantly improved, and the cost of testing required for selecting non-defective products after manufacturing can also be significantly reduced.

As an application field of the present invention, a logic device and a semiconductor memory device of the present invention constitute an arithmetic unit,
When a large chip is constructed by integrating multiple processing units on one chip, each unit can be tested in parallel, so the entire test time is approximately the same as that of one processing unit. This makes it possible to efficiently test large chips. Furthermore, by providing a spare arithmetic unit, it is possible to realize a large chip with a high yield rate.

Note that although the above embodiment shows a case in which a CMOS circuit is used, it is also possible to use a semiconductor memory device using other circuit technologies. Further, the number of cell arrays or the configuration of input/output circuits is not limited to the case shown in this embodiment, and other configurations are also applicable.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram of a conventional memory cell configured with CMOS transistors, Figure 2 is a circuit diagram of a memory cell that is an embodiment of the present invention, and Figure 3 is a test circuit using the memory cell of Figure 2. 4 is an overall configuration diagram of a semiconductor memory device of the present invention that incorporates a test circuit and realizes automatic redundancy switching. FIG. 5 is a configuration diagram of a word line selection circuit used in the present invention. A block diagram of the input/output circuit used in the present invention, Fig. 7 is a block diagram of the redundant switching circuit used in the present invention, Fig. 8 is an operation timing diagram of the test circuit used in the present invention, and Fig. 9 is a block diagram of the test circuit configured with NAND gates. FIG. 1 is a configuration diagram of a test circuit used in the present invention. 1a, 1b, 1c, 1d...n channel MOS
Transistor, 2a, 2b...p channel MOS
Transistor, 3... Word line, 4a, 4b...
Bit lines, 5a, 5b...first and second nodes, 6a, 6b...first and second transistors, 7a, 7b...first and second detection lines, 8
...Memory cell, 9a, 9b...Pull-up circuit, 10... _EX NOR gate, 11...Memory cell group, 12...Test timing line TE1, 13...
...Inverter, 14...Test timing line TE
2, 15...Flag register, 16...Flag register output line, 17...Cell array, 18...
Address signal line, 19...word line selection circuit, 2
0...Input line of test timing TE0, 21,2
2...Test data setting line, TD0, TD1, 23...
...Read/write switching signal line R/W, 24...
...Redundant switching circuit, 25, 25a, 25b, 25c
...Internal data line, 26...Input/output data line, 2
7... Test result output line, 28... Input/output circuit, 2
9... Address decoder, 30... NOR gate, 31... Sense amplifier circuit, 32... Tri-state gate, 33... Write transistor,
34...Data setting transistor, 35...
AND gate, 36...OR gate, 37... _E
OR gate, 38...transfer gate.

Claims (1)

[Scope of Claims] 1. Consists of a cell array in which a plurality of memory cells each having first and second nodes exhibiting opposite potentials are connected by a plurality of word lines and a plurality of bit lines, and each of the plurality of word lines By selecting one of them, one bit of information can be written to some or all of the memory cells connected to the selected word line through the bit line connected to the memory cell. In a semiconductor memory device that can be read,
First and second transistors are provided corresponding to the first and second nodes of each of the plurality of memory cells, respectively, and can be turned on or off depending on the first and second node potentials. and configuring a plurality of memory cell groups by dividing the cell array, and using the first and second transistors of each memory cell included in one memory cell group among the plurality of memory cell groups. first and second NOR gates or first and second NAND gates;
NOR gate or the first and second
1. A semiconductor memory device comprising testing means for testing whether or not a defect exists in a corresponding memory cell group among the plurality of memory cell groups using an output potential of a NAND gate. 2. Selection means for simultaneously selecting a plurality of predetermined word lines among the plurality of word lines for selection of the plurality of word lines, and "0" in the memory cells selected by the selection means. 2. The semiconductor memory device according to claim 1, further comprising writing means for collectively writing information of "1" or "1". 3 k of the n plurality of memory cell groups (k<
n) as a basic memory cell group and the remaining (n-k) memory cell groups as a spare memory cell group, and at least for the basic memory cell group, the test means includes a test result holding means. and a switching means for replacing the basic memory cell group with one or more spare memory cell groups based on the test results when there is a basic memory cell group that does not function normally. A semiconductor memory device according to claim 1.