JPS6072045A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To detect efficiently a defect in a short time by a simple test procedure, and to switch automatically the redundancy of a memory device on the basis of its result, by containing a means for detecting whether a defect exists or not in a semiconductor memory device. CONSTITUTION:Flag registers 15a, 15b and 15c are reset, subsequently, a test data setting signal TD0 is set to ''H'' state, TD1 is set to ''L'' state, and TE0 is set to ''H'' state. As a result, ''0'' information is written in the lump in each memory cell in a memory device. Next, a test timing signal TE1 is set to ''H'' state, and whether the information is written and held exactly in the memory cell concerned is inspected. Also, the test data setting signal TD0, TD1 and TE0 are set to ''L'', ''H'' and ''H'' states, respectively, ''1'' is written in the lump in each memory cell, and the memory cell is inspected. On the basis of the inspection result by said procedure, switching is executed automatically by a redundancy switching circuit 24.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor memory mounting, and particularly relates to a semiconductor memory device that incorporates a test circuit to enable faster testing and automatic redundancy switching based on test results.

d, “o” or “1” in the semiconductor memory device
There is a so-called statinoch type memory device in which binary information is held in bit-corresponding memory cells having a bistable state in terms of circuitry. FIG. 1 is a circuit diagram of a memory cell in a static memory device.

The figure shows the case where it is configured with CMOS transistors.
a, lb, lc and 1d are n-channel MOS+- run shifters, and 2a and 2b are p-channel MOS transistors. 3 is a word line for selecting the memory cell;
Reference numerals 4a and 4b designate Pino}M, which interconnect a plurality of memory cells through the word line and the bit line to form a cell array. In the same figure, 5a and 5b are the first and second nodes of the memory cell, and normally when the first node 5a is in the rLJ state equal to the ground potential, the second
Node 5b exhibits an rHJ state equal to the power supply potential Vl)]). Further, when the first node 5a is in the rHJ state, the second node 5b is in the rLJ state, and the first node 5a and the second node 5b take two stable states in which the potentials are opposite to each other. Therefore, in a static memory device, information of 0'' or 1'' is held in correspondence with bits in memory cells that can take these two stable states.

The operation when reading or writing information to this memory cell will be described below. In order to read or write to a memory cell, the word line 3 connected to the memory cell is set to the rl{J state and the first
And transistors 1a and lb between second bisotho lines 4a, 4b and first and second nodes 5a, 5b are rendered conductive. This state is the selected state of the memory cell.

At the time of reading, the potentials of the first and second nodes 5a and 5b of the selected memory cell cause the bit Ivi! connected to the selected memory cell to be changed. A potential difference is generated between 4a and 4b, and information held in the memory cell is read by detecting this potential difference. When writing,
Bit lines 4a and 4 connected to the selected memory cell
One of the bit lines b is set to the VHJ state and the other to the rLJ state, and the potentials of the second nodes 5a and 5b of the memory cell are set by the potential of the bit line.

Semiconductor memory devices with such a structure are manufactured as chips with transistors and wiring formed by repeating the process of forming conductor patterns and insulating layers on a silicon single crystal substrate using photolithography. Manufacture. Although these processes are usually performed in a dust-free chamber, it is difficult to significantly reduce defects that occur on the substrate during the manufacturing process. For this reason, after the manufacturing process is completed, it is necessary to test whether or not there are any defects in the tinops, and select non-defective products.

Test methods for semiconductor memory devices include ■All-O
・The all-one scan RZw method, ■marching method, and ■gear romping method are known as conventional methods. What are the common characteristics of these test methods?

A test device is prepared outside the semiconductor memory device, the test device generates an address signal for selecting a specific memory cell in the semiconductor memory device, and the memory cell selected by the address signal is set to ゜0'' or Writing or reading is performed by giving information of 1'1''' as a data signal. Therefore, “o” written in the cell array
Alternatively, for each internal state that is a combination of 1'' information, information is repeatedly written or read in units of 1 bit or several bits. , the number of internal states that can be acquired, 2N, must be tested by changing the order of selected addresses and read/write combinations, and as the storage capacity increases, the test time becomes enormous. There was a necessary problem.

Currently, advances in microfabrication technology for integrated circuits have dramatically increased the amount of circuitry that can be integrated onto a single chip. It has become possible to collect them all at once. However, when a memory device and a logic device are integrated on a single chip, due to limitations such as the number of pins provided on the chip, it is necessary to directly extract all address signals and data signals of the memory device to the outside of the chip. That is difficult. For this reason, when a memory device and a logic device are integrated together, conventional testing methods require complicated procedures to realize all internal states within the memory device.

On the other hand, as a conventional technique to repair defects that occur during the manufacturing of integrated circuits and enable large-scale integration, redundancy switching is used to provide a spare circuit in a semiconductor memory device and switch the defective circuit to the spare circuit. Techniques for dealing with defects are known. For example, in Japanese Patent Application No. 1-58206, a semiconductor memory device is constructed with a plurality of units consisting of a basic unit and a spare unit, and if a defect exists in the basic unit and it does not function normally, the spare unit is A method for resolving defects by replacing the basic unit with a semiconductor memory device is disclosed.In such a conventional method, each unit is tested from outside the chip constituting the semiconductor memory device, and the results are obtained for each unit. There was a problem that redundancy switching could not be performed based on the test results obtained, making it impossible to automate defect repair.

In this way, today's integrated circuits have become more and more sophisticated, and now they have the ability to detect the presence or absence of defects in a short period of time and with a high detection rate, without exchanging address or data signals with the outside of the chip. Semiconductor memory components are in disrepair.

An object of the present invention, in order to eliminate the problems of the prior art, is to have a built-in means for detecting the presence or absence of defects in a semiconductor memory device, and to detect defects efficiently in a short time using a simple test procedure. The object of the present invention is to provide a semiconductor memory device in which redundancy switching is automated based on the test results obtained.

The present invention will be explained below in detail by way of examples.

In order to achieve the above object, the present invention has a configuration in which the potentials of the first and second nodes of the memory cells constituting the semiconductor memory device can be detected regardless of the selected or non-selected state of the memory cells. This makes it easier to test semiconductor memory devices, allowing for built-in test circuits and faster testing.

FIG. 2 is a circuit diagram of a memory cell forming a semiconductor memory device according to an embodiment of the present invention. The figure is CMO3)
In this case, 6a and 6b are the first and second transistors, 7a and 7b are the first transistors, and 7a and 7b are the first transistors.
and a second detection line, and all others are the same as the conventional memory cell shown in FIG. Here, the gates of the j-th and second transistors 6a and 6b are connected to the first and second nodes 5a and 5b, respectively, and the sources are connected to the potentials of the first and second nodes 5a and 5b. - the drain is controlled to be in either a conductive state or a closed state. In this embodiment, the sources of the first and second transistors 6a and 6b are grounded, and the potentials of the first and second nodes 5a and 5b are set so that the potentials of the first and second nodes 5a and 5b are set regardless of whether the memory cell is selected or not by the word line. It is configured to detect by first and second detection 117a and 7b.

FIG. 3 is a configuration diagram of a memory cell group in which a plurality of memory cells shown in FIG. 2 are connected to form a test circuit. Note that a portion 8 surrounded by a broken line in the figure is the memory cell shown in FIG. 2, and among the memory cells, the first and second nodes 5a, 5b, the first and second transistors 6a,
6b and the first and second detection lines 7a and 7b are shown,
Others are omitted. 9a and 9b are pull-up circuits for the first and second detection Nfi 7a, 7b;
The first and second transistors 6a and 6b connected to the detection lines 7a and 7b and these transistors 9a and 9b constitute first and second NOR gates, respectively.

10 is an ExNOR gate, which connects the outputs of the first NOR gate and the second NOR gate. 11 is a memory cell group including a plurality of memory cells 8 and a pull-up circuit 9a.

9b and an EXNOR gate 10. 12
is a signal line that provides test timing (TEI), and a logic symbol 13 provided on this signal line is an inverter.

The test result is obtained as the output of the ExNO'R gate 1o, and the signal line 14 that provides the test timing (TE2) is
-■'' state, it is taken into the flag register 15. 1
6 is an output line of the flag register 15.

Next, the operation of the test means using this trial engraving circuit will be explained. Before performing the test, the flag register 15 for holding the test results is reset in advance. After that, memory cell group 1
"o" or "1" information is written into each memory cell 8 constituting the test timing signal (T
By bringing EI) into rHJ state, ml and second
The NOR logic regarding the first node 5a and the NOR logic regarding the second node 5b of the memory cell 8 connected to the detection line 7a and 7b are obtained. At this time,
If information is normally written into all of the memory cells 8 and held normally, the potentials of the first and second detection lines 7a and 7b are such that one is in the rHJ state and the other is in the rLJ state. , indicating the opposite potential. but,
If there is a defect in either the word line, bit line, write circuit, or memory cell related to the memory cell group,
When the memory cell group does not function normally, the first and second detection lines 7a and 7b are both in the rLJ state. Therefore, by taking ExNOR logic between the first detection line 7a and the second detection line 7b, it is determined that when this output is in the rHJ state, there is a defect in the memory cell group, and rLJ A test result indicating that there are no defects is obtained when the condition is the same. The obtained test results are taken into the flag register 15, which is a test result holding means, by setting the test timing signal (TE2) to the rHJ state.

FIG. 4 is an overall configuration diagram of the semiconductor memory device of this embodiment. 17 is a cell array, 18 is an address signal line, 1
9 digit word line selection circuit, 20 is test timing (TKO
) input line, 21.22 is the test data setting line (TDO)
, (TD, t), 23 is a read/write switching signal line (R/W), 24 is a redundant switching circuit (SW), 25a,
25b, 25c are internal data lines, 26a, 26b
2 is an input/output data line, and 27 is a test result signal line. In this embodiment, the cell array 17 includes three memory cell groups 11a.
.

11b and llc, two of the memory cell groups are a basic memory cell group and the remaining one is a spare memory cell group. Each memory cell group 11a, llb.

Reference numeral 11c is a plurality of memory cells shown in FIG. 2, and these memory cells constitute the inspection circuit shown in FIG. 3. Also, memory cell groups 11a, llb, llc
d1 The output circuit 28 (Il) is used for writing information into the memory cell and for reading information from the memory cell.
o) is provided.

5 to 7 are configuration diagrams of the word line selection circuit 19, input/output circuit 28, and redundancy switching circuit 24 in FIG. 4.

FIG. 5 shows a word line selection circuit equipped with selection means for selecting a plurality of word lines at once. 29 in the figure is an address signal (AD) given from the address signal line 18.
This is an address decoder that selects one of the word lines 3 based on .

The logic symbol 30 is a NOR gate, and together with the inverter 13 at the subsequent stage, the output signal of the address decoder 29 and the test timing signal (TE
It realizes OR logic with O). As a result, when the test timing signal (TKO) is in the rHJ state, all word lines 3 are in the rHJ state, and all memory cells connected to the word lines are in the selected state. Therefore, when the test timing signal (TEO) is in the rHJ state, information of "o" or "1" is collectively sent to a plurality of memory cells connected to the word line selected by the word line selection circuit. It is possible to write. on the other hand,
When the test timing signal (TEO) is in the rLJ state,
Address signal (AD
), only one word line is in a selected state, and information can be written to and read from a specific memory cell based on the selected state.

FIG. 6 is a block diagram of an input/output circuit 28 equipped with a writing means for writing information of "0" or II 1 # into the cell array at once. 31 is a sense amplifier circuit, 32 is a tristate gate, 33a and 33b
Write transistors 34a and 34b are data setting transistors. A feature of this circuit is that, in addition to the so-called read and write operations in conventional semiconductor memory devices, it enables batch write operations for the purpose of executing tests in a short time. During a read operation, that is, when the read/write switching signal (R/W) applied from the switching signal line 23 is in the rHJ state, the first memory cell selected by the word line 3
The potential of the second node is input to the sense amplifier circuit 31 via the bit line 4a and the bit line 4b, and the result of amplification by the sense amplifier circuit 31 is set to 0 depending on whether it is in the rLJ state or the rHJ state. '' or read as II II information.

When the read/write switching signal (R/W) is in the rHJ state, the tristate gate 32 is not in a conductive state.
The output of the sense amplifier circuit 31 is obtained on the internal data line 25, and the read operation is completed.

During a write operation, that is, the read/write signal (
R/W) is in the rLJ state, the write transistors 33a and 33b are driven based on the information given to the internal data line 25, and the potential of either the bit line 4a or the bit line 4b is set to the ground potential. Set to equal rLJ state. That is, when the internal data line 25 is in the rLJ state, the bit line 4a is brought into the rLJ state, and the bit line 4b is brought into the rHJ state. On the other hand, the internal data line is rHJ
When the bit line 4a is in the rHJ state, the bit line 4b is in the rLJ state. By reversing the potentials of the first and second nodes of the memory cell connected to the focus line by the bit line 4a and bit 114b set to opposite potential states and selected by the word line 3, Perform a write operation.

During batch write operation, test data setting line 21°22
In addition, test data setting signals (TDO) and (TDI) are provided. At this time, the test data setting signal (TDO).

(TDI) is set to "H" state, either data setting transistor 34a or 34b is set to conductive state, and internal data lines 25 are collectively set to rLJ state or rHJ state. In such a state, the test timing signal (TEO) applied from the input line 20 is
By entering the HJ state, multiple sets of bit lines are set to the write state at the same time. Therefore, the principal output circuit and the fifth
By using the word line selection circuit 19 explained in the figure, the same memory cells are connected to word lines indicating multiple selection states and multiple sets of bit lines set to the p↓ write state. Information can be written in bulk.

FIG. 7 is a configuration diagram of the redundant switching circuit (SW) 24, which is the switching means in this embodiment. In the same figure, theory B!
Symbols 3s, 36, 37.38 are respectively
These are an AND gate, an OR gate, an EXOR gate, and a transfer gate. 16a, 16b, and 16c are output lines of flag registers 15a, 15b, and 15c, respectively, and output the test results of three memory cell groups 11a, llb, and llc constituting the cell array.

This circuit is based on the test results of three memory cell groups.
Internal data line 2 that sends input/output signals of the memory cell group
5a, 25b, 25c and the input/output data lines 26a, 26b of this memory device from 3 to 2 (2 out
-of3) redundancy switching. That is, memory cell group (A) 1 which is a basic memory cell group
If there is no defect in either memory cell group 1a or memory cell group (B) llb, the output line 16a of the flag register
.

16b are both in the rLJ state, and the internal data line 25a
is connected to the input/output data line 26a, and the internal data line 25b is connected to the input/output data line 26'b via a transfer gate 38, respectively. Memory cell group (B) llb
If there is a defect in the memory cell group (A) lla and the other memory cell group (C) llc, the flag register output lines 16a, 16b, 16
c is 0.1.0, the internal data line 25a is connected to the input/output data 1126a, 25c is connected to 26b, and memory cell group B is defective and does not function normally.
The internal data line 25b is not subject to input/output.

In this way, if only one arbitrary memory cell group out of the three memory cell groups is functioning normally, the semiconductor memory device U is replaced by the other two normally functioning memory cell groups.
functions normally and defects are repaired. If two or more of the three memory cell groups do not function normally, an "H" state is obtained on the test result signal line 27, and it can be detected that the semiconductor memory device is unusable.

Next, a procedure for testing and redundancy switching of the semiconductor memory device of this embodiment shown in FIG. 4 will be explained. FIG. 8 is an operation timing diagram of the test circuit built into the semiconductor memory device. The signals to be tested are (R8T), (TDO), (
TDI), (TEO), (place).

There are six types of (TE2), among which (TDO).

(TDI), (TEO), (position), and (TE2) are the same as shown in FIG. The (R8T) signal is a signal that is used to reset the flag registers 15a, 15b, and 15c to 0'' in the initial state, and is omitted in FIG. This is the test end signal.

Test procedure ■ Set the flag register reset signal (R8T) to rl (J state) and reset the flag registers 5a, 15b, and 15c, which are means for holding test results.This state indicates that there is no defect in any of the memory cell groups. This is the same state as when it is functioning normally.

■ Set the test data setting signal (TDO) to rHJ state, (
TDI) is in the rLJ state and the test timing signal (TE
O) is set to rHj state. At this time, all internal data lines are in the rLJ state, and "'0" information is collectively written into each memory cell in the memory device.

- Set the test timing signal (TEI) to "H" state.

At this time, in each memory cell group, a test is performed by the test circuit shown in FIG. 3 to determine whether information is correctly written and held in the memory cells constituting the memory cell group.

(2) Set the test timing signal (TE2) to rHJ state.

At this time, the test result obtained in (2) is held in the flag register. Regarding the content held, when the memory cell group does not function normally, it is in the rHJ state, and when it functions normally, it is in the rLJ state.

■ Test data setting signal (T'DO) is set to rLJ state (T
DI') is in the rHJ state, and the test timing (TEO) is
Let be the rHJ state. At this time, all internal data lines are in the rHJ state, and It III information is written in each memory cell in the semiconductor memory device at once.

Similarly to ■■, the test timing signal (TEI) is
By setting the memory cell to the HJ state, the memory cell is inspected.

Similarly to ■■, the test timing signal (TE2) is set to rHJ state, and the test result obtained in ■■ is sent to the flag register 15.
Incorporate into. At this time, flag register 15 is set to ■.
a, 15b, 15c K If the rHJ state is maintained, the flag register remains in the rHJ state regardless of the test result of (2).

As a result, if a defect is detected in the memory cell group by at least one of the tests (1) and (2), the rHJ state is set in the flag registers 15a, 15b, and 15c, and the memory cell group is normally operated. It can be determined that it does not work.

(2) Set the test end signal (T END ) to rHJ state and end the test.

By carrying out the above procedure, the flag register 15
The test results of memory cell group A, memory cell group B, and memory cell group C are obtained in a, 15b, and 15c. Therefore, in the redundancy switching circuit 24 shown in FIG. 7, redundancy switching can be automatically performed based on the obtained test results.

In the semiconductor memory device of this embodiment described above, as shown in FIG.
b constitutes a NOR gate, but the detection circuit is configured with NA by the first and second transistors 6a and 6b.
It can also be configured with an ND gate.

FIG. 9 is also a configuration diagram of a test circuit which is an embodiment of the present invention. The part surrounded by the broken line in the figure is 8 memory cells υ
, only the first and second nodes 5a, 5b and the first and second transistors 6a, 6b are shown. 9a,
Reference numeral 9b is a pull-up circuit, which sequentially connects the north of the first and second transistors 6a and 6b to the drain of the adjacent memory cell 8 to connect the first and second ONANs, respectively.
A D gate is configured, and the NAND gate is used to test whether the memory cell is functioning normally. 1st ONA
The output of the ND gate is the first
The rLJ state is entered only when all of the transistors 6a become conductive. Similarly to the first ONAND gate, the output of the second NAND gate also enters the rLJ state only when all of the second transistors 6b constituting the NAND gate become conductive. Therefore, the EXNOR circuit 10 is connected between the outputs of the first and second NAND gates.
By calculating the exclusive OR, it is possible to check whether the same information is correctly written and held in all memory cells constituting the memory cell group. The rest of the circuit configuration of this embodiment is the same as that shown in FIG. Therefore, even when the inspection circuit is constructed of NAND gates, automatic defect relief can be carried out by the built-in test circuit as in the previous embodiment.

Note that in the configuration of the semiconductor memory device shown in FIG. 4, redundancy switching is performed for the memory cell groups constituting the test circuit in units of row 5; Automatic defect relief is possible even in a configuration where the circuit targeted for switching is different from the circuit targeted for switching.

As explained above, in the semiconductor memory device of the present invention,
Since each of the memory cells constituting the cell array is provided with a transistor for defect inspection, a test circuit can be built in, and a simple and high-speed test can be performed. For this reason, even for semiconductor memory devices that require complicated testing with conventional testing methods, such as large-capacity semiconductor memory devices or cases where memory devices and logic devices are mixed on one chip, it is possible to test semiconductor memory devices quickly and easily. The test can be performed using a standard procedure. However, by applying a redundant configuration to the cell array of a semiconductor memory device, automatic redundancy switching based on self-defect detection is possible. Therefore, the rate of non-defective products when semiconductor memories are installed can be significantly improved, and the cost of testing required for selecting non-defective products after manufacturing can also be significantly reduced.

As an application field of the present invention, a logic device and a semiconductor memory device of the present invention constitute an arithmetic unit, and a plurality of arithmetic units are collectively assembled on one chip to form a huge chip. Since the test can be performed in parallel on each unit, the entire test time can be reduced to approximately the test time of one arithmetic unit, making it possible to efficiently test a large chip. 1. By providing a spare arithmetic unit, it is possible to create huge chips with a high yield rate.

Note that although the above embodiment shows a case in which a CMO8 circuit is used, it is also possible to use a semiconductor memory device using other circuit technologies. Further, the number of cell arrays or the configuration of input/output circuits is not limited to the one shown in this embodiment, and other configurations can also be applied.

[Brief explanation of drawings]

Figure 1 is a circuit diagram of a conventional memory cell configured with CMiO8) transistors, Figure 2 is a circuit diagram of a memory cell that is an embodiment of the present invention, and Figure 3 is a test using the memory cell of Figure 2. 4 is an overall configuration diagram of a semiconductor memory device of the present invention that incorporates a test circuit and realizes automatic redundancy switching; FIG. 5 is a configuration diagram of a word line selection circuit used in the present invention;
Figure 6 is a configuration diagram of the input/output circuit used in the present invention, Figure 7 is the M4 configuration of the redundant switching circuit used in the present invention, Figure 8 is an operation timing diagram of the test circuit used in the present invention, and Figure 9 is the NA
FIG. 4 is a configuration diagram of a test circuit 4) used in the present invention and configured with ND gates. la, lb, lc, Id - n-channel MOS transistor, 2a, 2b... p-channel MO8) transistor, 3... word line, 4a, 4b - bit line, 5a
, 5b...first and second 7-de, 6a, 6+b-
First and second transistors, 7a, 7b...first and M2 detection lines, 8...memory cell, '9a
, 9b... Group amplifier circuit, lO... ExN, OR
Gate, 11...Memory cell group. 12...Test timing test (position), 13...Inverter, 14...Test timing line (TE2), 15...
・Flag register, 16...Flag register output line, 17...Cell array, 18...Address code line,
19...Word line selection circuit, 20...Test timing (TEO) input line, 21, 22...Test data setting line (TDO), (TDI), 23...Read/
Write switching signal line (R/W>, 24...redundant switching circuit. 25, 25a, 25b, 25cm internal data line, 2
6. Input/output data line, 27. Test result output line,
2B...Input/output circuit, 29...Address decoder,
30...NOR gate, 3]...Sense amplifier circuit, 32...Tri-state gate, 33...Write transistor, 34...Data setting transistor, 35...AND gate, 36...OR gate ,
37...E, xOR gate, 38...transfer gate. Congee 1 Room 20 3rd Kasumikata 8 Figure 9

Claims (3)

[Claims] (1) First and M2 each exhibiting opposite potentials to each other
A cell array in which a plurality of memory cells having nodes are connected by a plurality of word lines and a plurality of pins. In the semiconductor memory device, each of the plurality of memory cells is capable of writing and reading information of an Ebinod into and from a part or all of the memory cells through a bit i connected to the memory cell. The cell array is provided with first and second transistors corresponding to the first and second nodes of the cell array, respectively, and capable of switching between a conduction state and a cutoff state depending on the potentials of the first and second nodes, and dividing the cell array. forming a plurality of memory cell groups, and using the first and second transistors of each memory cell included in one memory cell group among the plurality of memory cell groups, the first and second NOR gate or first and second
constitute a NAND gate, and the first and second NOR
The present invention is characterized by comprising a test means for testing whether or not a defect exists in a corresponding memory cell group among the plurality of memory cell groups described in h11 above using the output potential of the gate or the first and second NAND gates. semiconductor memory device. (2) selection means for simultaneously selecting a plurality of predetermined word lines among the plurality of word lines to select the plurality of word lines; 1. A semiconductor memory device according to item 1 of the patent, characterized in that the semiconductor memory device is provided with a write means for writing each piece of information at once. (3) Among the plurality of memory cell groups n (k<n
) is configured as a basic memory cell group and the remaining (n-k) memory cell groups are configured as a spare memory cell group, and the testing means includes a test result holding means for at least the basic memory cell group. At the same time, it is equipped with a switching means for replacing the basic memory cell group with one or a plurality of spare memory cell groups based on the results of 17 experiments in the case that there is a basic memory cell group that does not function normally. A patented semiconductor memory device characterized by: