JPS6254343A - Data processor - Google Patents

Abstract

PURPOSE:To reset a microprocessor without intermission of I/O operation and to prevent a read/write memory from being damaged by inputting a reset signal to the microprocessor at the detection of the stop of the microprocessor. CONSTITUTION:If a RESETA signal on a signal line 101 is set up to '0' by the operation of a switch 1, a flip flop (FF) 4 is set up at the trailing edge of the RESETA signal. An FF 5 is set up by the output of the FF 4 and a clock signal outputted from a CPU 11. An output signal INTA on a signal line 105 is inputted to an interruption control circuit 10 and the CPU 11 starts interruption processing on the basis of the RESETA signal. The execution of a holding instruction built in the final stage of the processing turns the CPU 11 to stop status and then reset status. Thereby, no I/O operation is executed and the contents of the read/write memory is not damaged.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to reset signal control of a microprocessor (CPU) used in a data processing device, and in particular, the present invention relates to reset signal control of a microprocessor (CPU) used in a data processing device. The present invention relates to a method for validating a reset signal that is input asynchronously to the execution of instructions in a microprocessor (CPU).

(Prior art) In data processing devices using microprocessors (CPUs), initial test programs for hardware and read/write
Most processing programs are stored on the read/write memory, except for the program loader for the write memory.

Conventionally, a reset signal of a data processing device was input asynchronously to the operation of a microprocessor, and the device was reset unconditionally.

(Problems to be Solved by the Invention) In the conventional data processing device described above, the reset signal is input asynchronously to the operation of the microprocessor (CPU), so depending on the timing, the reset signal may be input to the microprocessor (CPU).
There is a drawback that the write access operation to the read/write memory in U) does not satisfy the AC standard of the memory element and may be terminated midway, resulting in destruction of the contents of the memory.

The purpose of the present invention is to transfer the reset signal to a microprocessor (C
PU) as an interrupt signal, maintains that the interrupt is being reported by the reset signal, starts the interrupt processing program by the interrupt signal, and then stops (holds) the microprogram with an instruction at the end of the interrupt processing. As a result of the execution of the interrupt routine by the microprocessor, the above disadvantages are eliminated by putting it in a stopped state, and finally, a reset signal can be input to the microprocessor (CPU) and related hardware, and the memory contents are not destroyed. An object of the present invention is to provide a data processing device configured to prevent such occurrences.

(Means for Solving the Problems) A data processing device according to the present invention uses a microprocessor (CP
1), a gate means, a holding means, an interrupt control means, and a CPU 1,1 set signal generation means.

The microprocessor (CPU) is for executing processing including interrupts, and the gate means is for notifying an external reset signal as an interrupt signal for the microprocessor. The holding means is for holding that an interrupt due to a reset signal is being reported.

The interrupt control means executes necessary processing prior to resetting according to the interrupt signal, and then controls the microprocessor (CP).
This is to stop U).

The CPU reset signal generation means is a microprocessor (C
This is to ultimately generate a CPU reset signal when the CPU (PU) is stopped as a result of an interrupt.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing a control circuit for a reset signal input to a microprocessor (CPU). In FIG. 1, 1 is a reset switch, 2 is a filter, 3.
6 are AND gates, 4, 5, and 7 are D-type flip-flops, 8 is a NAND gate, 9 is a NOR gate, 10 is an interrupt control circuit, and 11 is a microprocessor (CPU).

12 is a clock generation circuit. Also, 101 is RES
IE: TA* signal line, 102 is RESETB* signal line,
103 is the RESETC signal gauze, 1 signal is on the INTA signal line, 105 is the INTA* signal line, 106 is the INTB* signal line, 107 is the INTn* signal line, 108i, ! ,INT
*Signal line, 109 is CLOCK signal line, 110 is HAL
T signal line, 111 is DO signal line, 112 is D1 signal line,
113 is the D20 signal line, 114 is the D21 signal line, 115
is a D20* signal line, 116 is a D21* signal line, 117 is a D22* signal line, and 118 is a RESET* signal line.

RESETA*, RESETB*, RESETC, RE
SET* is a reset signal, INTAl INT
A*, INTB*, I N T n *, INT* are respectively interrupt request signals, CLOCK is a clock signal, H
ALT is the HALT signal, Dl is the AND gate output signal,
Do, D20, D21, D20*, D21*, D22*
are the D-type seven rib-flop output signals, respectively.

In FIG. 1, the microprocessor (CPU) 11 is a general one, and among the input/output bins of the microprocessor (CPU) 11, addresses/
All data bins are omitted. microprocessor (
For each pin of the microprocessor (CPU) 11, R8T is the reset input pin, INT is the interrupt input pin, CLK is the clock input pin, and HALT is the microprocessor (CPU) input pin.
) 11 is an output pin indicating that the HALT command has been executed and the system has entered a halt state. The interrupt control circuit 10 selects one of the interrupt request signal lines 105 to 107 according to a predetermined priority order,
A microprocessor (C
This is for interrupting the PU) 11. Although which interrupt input is selected is not shown in FIG.
PU) 11.

The D-type flip-flops 4.5 and T hold input data in synchronization with the rising edge of the clock.

The RESETA* signal on signal line 101 is a reset signal by switch 1, and the RESETB signal on signal line 102
The * signal is, for example, a reset signal that sets other microprocessors. Now, RESET on signal line 101
Assuming that the A* signal is set to @0'' by operating switch 1, the D-type flip-flop 4 is set by the trailing edge (rising edge) of the RESETA* signal.D
The output DO of the D-type flip-flop 4 is sent onto a signal line 111 and set in the D-type flip-flop 5 by the clock signal CLOCK of the microprocessor (CPU) 11. The false output signal INTA* sent from the D-type flip-flop 5 onto the signal line 104 is input to the interrupt control circuit 10, and if there is no other interrupt request or INTA* on the signal line 105 has the highest priority. If the microprocessor (CPU) 11 is connected to the signal line 1
Starts the interrupt service specified by the RESETA* signal on 01. The interrupt processing program includes a hold instruction to bring the microprocessor to a halt state at the end of processing, and by executing this hold instruction, the microprocessor (CPU) 11 is HALT.
At the same time as the output bin becomes active, it becomes inactive.

The HALT signal on signal line 110 is ANDed with signal line 104.
The signal is applied to the DO input terminal of the D-type flip-flop 7 via the gate 6, and the output signal lines 115, 114, and 117 of the D-type flip-flop T are sequentially set by the clock signal. The signals output from the D-type flip-flops 4.5 and T are output through the NAND gate 8 and the NOR gate 9, and the RESET* on the signal line 118 is @0#.
becomes. As a result, the microprocessor (CPU) 1
1 is reset.

At this time, since the microprocessor (CPU) 11 has already stopped operating, no input/output operations are performed. Therefore, destruction of the contents of the read/write memory cannot occur. RESET* on signal line 118
D20 on signal lines 115-117 to set the signal.
The purpose of calculating and using the logical sum of the *~D22* signals is to ensure that the microprocessor (CPU) 11 is reset, and is not directly related to the present invention. The RESETC signal on the signal line 103 is an asynchronous reset signal that is input directly to the NOR gate 9 without passing through the NAND gate 8 for reset control described above and input to the R8T terminal of the microprocessor (CPU) 11. This is used when the contents of the /write memory are not concerned about destruction, and a possible cause of this is, for example, turning on/off the power of the data processing device.

FIG. 2 is a time chart showing the above-mentioned operation, and illustrates the operation from setting the RESETA* signal on the signal line 101 to setting the RESET* signal on the signal line 118. .

In Figure 2, the part of the microprogram processing in the bottom column summarizes the processing contents of the microprogram, and jumps from normal processing (a) to the interrupt routine by the RESETA* signal, and the final processing. After the hold command is executed (b) and the RESET* signal is released, the process proceeds to reset processing.

Regarding the processing content of the interrupt processing program, it is generally considered that information is saved when an interrupt occurs, but the conditions of the present invention are also satisfied by simply executing a hold instruction. In a microprocessor that is not equipped with a hold output pin, a register that can be set by the microprogram may be defined in order to notify an external reset control circuit that the microprocessor is held. That is, in this case, the interrupt processing program executes the register fund of the above-mentioned register at the end of processing, and then executes the hold instruction. The reset control circuit determines that the microprocessor will stop operating after a certain period of time due to the register being set. The configuration may be such that the microprocessor reset signal becomes active after a certain period of time has elapsed.

(Effects of the Invention) As explained above, the present invention notifies the microprocessor of the asynchronously inputted reset signal in the form of an interrupt, and inputs the reset signal to the microprocessor when the microprocessor is in a stopped state. This has the effect of allowing the reset operation to be performed without interrupting the input/output operations of the microprocessor, thereby preventing the read/write memory from being destroyed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a data processing apparatus according to the present invention. FIG. 2 is a time chart showing the operation of the data processing device shown in FIG. 1... Reset switch 2... Filter 3.6... ・AND gate 4.5.7... D type 7 lip-flop 8... NAN
D gate 9...NOR gate 10...Interrupt control circuit 11...Microprocessor (CPU) 12...Clock generation circuits 101 to 118...Signal line

Claims (1)

[Claims] A microprocessor (
a CPU); gate means for notifying a reset signal from the outside as an interrupt signal for the microprocessor; holding means for holding that an interrupt is being reported by the reset signal; interrupt control means for stopping the microprocessor (CPU) after executing necessary processing prior to resetting; 1. A data processing device comprising: CPU reset signal generating means for generating a reset signal.