JPS62150416A - Transition system to low power consumption state - Google Patents

Abstract

PURPOSE:To eliminate the disturbance of other task execution by bringing the computer system to the standby mode when the absence of a task to be executed is detected in the system applying multi-task processing. CONSTITUTION:A computer system is added with a program memory 1, a program counter (PC) 2, an instruction decoder 3, a peripheral equipment 4, a clock generator 5, a data memory 6, a decision circuit 7, an AND gate 8 and a latch 21 with inverter, the instruction decoder 3 activates each signal line for the system operation. In this case, a clock is fed to the peripheral equipment 4 and the PC 2 via the AND gate 8 and when the output 20 of the latch 21 is inactive, the mode is brought into the standby mode where the peripheral equipment 4 is stopped. Further, the standby mode continues until the latch state is released.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field] The present invention relates to a microcombination processor that is equipped with a standby mode to reduce power consumption in parts that are not in an operating state, and that performs all information processing in addition to multitasking processing.

Method for transitioning to standby mode in a system % Formula % In recent years, advances in microcomputer manufacturing technology and demands for lower power consumption have led to the emergence of many micro combinators based on 0MO8 manufacturing technology. Furthermore, not only does it directly reduce power consumption by simply converting the device to 0MO8, but it also effectively cuts off the clock supply to parts of the hardware system that are not doing actual work, except for the parts necessary to resume program execution. Standby mode technology has been introduced to actively reduce power consumption by stopping hardware execution. This situation and the basic technology are detailed in the literature (13K). The method of using standby mode is to enter standby mode by executing an instruction in the microcomputer, and return from standby mode to normal operating mode in response to an interrupt (external interrupt, reset interrupt, timer interrupt, etc.). In other words, the program currently running on the microcomputer judges the situation at an appropriate point, issues a command to enter standby mode, enters standby mode, and waits until some kind of interrupt occurs. It maintains a low power consumption state and continues executing the original program again after one interrupt occurs. Figure 1 shows this situation. However, this method of transitioning to standby mode has the following problems. .

l) Judgment is required for each execution program before issuing a standby mode transition command.

2) When there are multiple programs to be executed on a microcomputer system, if each program enters the standby mode for judgment, it may interfere with the execution of other programs.

In particular, problem 2) is serious in a multitasking environment where a plurality of programs are executed and managed as tasks under the control of an operator ink system (hereinafter referred to as O8).

〔the purpose〕

Is the present invention an effective solution to the above problems? The purpose of this invention is to provide a means for effectively transitioning to standby mode in a multitasking environment without interfering with the execution of other tasks.

〔composition〕

The present invention provides a first means for detecting the presence or absence of a task to be executed in a computer system under the control of an operating system that performs multitasking processing in which multiple tasks are executed in parallel, and a system for setting the system to a low power consumption state. A low power consumption method, comprising a second means, and when it is detected by the first means that there is no task to be executed, the second means sets the computer system to a low power consumption state. This is a method of transitioning to a state.

[action, effect]

Generally, tasks under O8 control transition between various states according to execution conditions. Figure 1%2 is an example of a state transition diagram. In the diagram, the inside of the circle represents the condition.
All the conditions necessary for execution (e.g., securing memory area, securing equipment, etc.) are met, but the program is in a waiting state (Rt)N state before being given control of the CPU to be executed. 1 represents a state in which a task that was in the Ready state is executing a program after gaining control of the CPU, and a state in which it is waiting for some condition other than the control right of the 1dcPU to be satisfied. Re
When multiple tasks exist in the ady state, they are sorted in order of execution priority (priority) or HRJeady, i.e. FeF2 (first come
first served). Arrows indicate the direction of the transition. As can be seen from the state transition diagram, under O8 control, as long as there is a task in the Ready state, the CPU must execute it. In other words, it is not possible to shift to standby mode. But 1-LLINRe
If there are no tasks in either state of ady, this indicates that all the tasks are in a wait state, that is, waiting for some condition, and cannot be executed. That is, in this state, by setting the O8 to transition to standby mode, it is possible to transition the Combita system to a low power consumption state without interfering with the execution of other tasks.

〔Example〕

Next, the present invention will be explained in detail with reference to the drawings. Figure 3 shows Ru
This is a memory representation of a task in the Ready state. 1 is called cue head.

Control block of a task in Run state (
(abbreviated as TCB) 3, that is, the address value P1 of the TCH linked to the queue and the pointer P2 to the last TCB linked below are stored.

4.5 TCH of each task in Ready state
It is. Ps and P4i are pointers to the TCB of the next linked task. Tasks related to n-1 TCBs from 4 to 5 are Ready state tasks, and can obtain CPU execution rights in the order of links.

The pointer value @0” at 5 is the next linked TCB
It shows that there is no The control method of O8 at the time of task state transition will be explained below.

When the execution of the task related to 3 is completed, the contents of 08nP1 are replaced with a pointer to P3, that is, 4, and the execution right is given to task 4. Also, from Wait to Ready
Ready
Search for the TCBi of the last linked task in the current state, then link the new TCBI, and at the same time create a pointer value of 1&:0 and set the new task's pointer area to @0'' at the address of the new task's TCB.Here, New Re
Assume that there is no task that becomes ady, the links are followed one after another, task 5 becomes Run, and this execution ends. 0
8 [Since there is no TCB for the next task to be linked, set Pl to ``0m. In other words, nothing is connected to the queue and there is no task to be executed. Conversely, if Pl becomes 10#, it will be executed. This means that it has been detected that there is no task to be performed.At this point, O8 has no choice but to instruct transition to standby mode.FIG. 4 is a flowchart showing this procedure.

FIG. 5 is a block diagram showing an embodiment of the present invention. 1
is program memory, 2μ program counter (PC)
31d is an instruction decoder, 4 is a peripheral circuit, 5 is a clock generator, 6 is a data memory, and 7 is a determination circuit. 8 is AN
A D gate, a latch with an inverter at 21, a line from 9 to 20 and a line at 20, and a signal line with double diagonal lines generally represent a signal line consisting of a plurality of elements. Operating system and other programs [stored in 1 and 2
The instruction address kl 7'! The output is input to the 16-karat gold via 3. 3 activates the signal lines necessary for each command and operates as a computer system. Here, it is assumed that a TCB and a queue head equivalent to the 6KIE3 diagram have already been created in addition to other general instructions.

When a command to determine whether the cue head pointer value is O is issued, the address line 10 is activated and the data line 12 is set to the cue head pointer value specifying the address of the memory where the cue head in 6 is stored. via 7
is input to. This command activates 11 at the same time and 7
make it work. If the data input from 77H12 is O, 13 is activated, the contents of 2 are modified, and the instruction address is moved to the standby mode setting instruction. When the instruction is read, 9 is activated. -10,000,5 is constantly supplied to various parts of the flock tr via 18 in order to maintain the operation of the system. A clock is supplied to 4 and 2 through 14°8.15' (l-. Since 8 is an AND gate, 20 is inactive and cannot transmit the signals of 15 to 14.However, , 20 which is the output of 21 since 9 is inactive unless a standby mode command is issued.
It is always activated and therefore the clock is input to 4. Since 9 can be activated here, 21
The output 20 becomes inactive, the signal line 15 becomes inactive, and the operation stops at 4, when no clock is supplied. In other words, it becomes standby mode. Since 21 is a latch, the standby mode continues until the latch state is released, and the contents of 2 do not change.

Here, when an interrupt is input from the outside via 221-, the latch state of 21 is released, and at the same time, the value of 2 becomes a specific instruction address that is set for each interrupt, and generally the interrupt process is executed.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to effectively utilize the standby mode, which has conventionally been unable to take full advantage of its advantages, by introducing some means under the intervention of the operating system.

[Brief explanation of drawings]

Figure 1 is a conceptual diagram of IH standby mode and operation mode, Figure 2 is a task state transition diagram, Figure 3 is [TCB
FIG. 4 is a flowchart showing the implementation procedure of the present invention, and FIG. 5 is a block diagram of the embodiment.

Claims (1)

[Claims] In a computer system under the control of an operating system that performs multitasking processing in which multiple tasks are executed in parallel, there is a first means for detecting the presence or absence of a task to be executed, and a second means for setting the system to a low power consumption state. A method for transitioning to a low power consumption state, characterized in that the computer system is set to a low power consumption state by the second means when it is detected by the first means that there is no task to be executed. .