JPS6254268B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a still image broadcast receiving apparatus, and more particularly to a still image broadcast receiving apparatus that receives a still image signal superimposed on a vertical blanking period of a television signal and displays a still image.

Recently, still image broadcast receiving devices have been proposed and are being improved for practical use. This still image broadcast receiving device receives still image signals such as characters and graphics that are superimposed on normal video signals during the vertical blanking period of the television signal, and converts the still image signals into a microprocessor, etc. After the data is processed by the central processing unit, it is stored in a buffer memory and read out to display a still image. Here, the still image signal is superimposed and transmitted separately from the normal video signal during the vertical blanking period of the television signal, and has, for example, the following format. In other words, if one still image screen has 248 bits in the horizontal direction (horizontal direction) and is divided into 204 lines in the vertical direction (vertical direction), then the total number of pixels is 248 x 204 = 50592 bits in matrix form. If one block consists of a pattern signal, which is the information of a pixel, and 96 bits (8 x 12 = 96) of pixels, 8 bits in the horizontal direction and 12 bits in the vertical direction, there are 31 blocks in the horizontal direction and 31 blocks in the vertical direction.
It is composed of a color signal which is color information of a total of 31×17=527 blocks, which are 17 stages. For each still image signal, one horizontal scanning line corresponds to 248 pattern signals.
The color signal consists of 31 blocks (248 bits). When transmitting a still image signal of a still image to be displayed in one frame, when the vertical blanking period of the television signal is divided by the time of one horizontal scanning period, the 10th The so-called th horizontal scanning period
From the 10th H (273rd H for even fields) to the
Data packets with various control codes added thereto are sent out during an arbitrary period of the 21st horizontal scanning period, so-called 21st H (284th H in even fields). Here, various control codes include, for example, start reference signals (RUN, IN), framing codes (FC), and service identification codes (SI/IN).
and data identification code (DI). Furthermore, when a still image consists of a plurality of pages, a data packet (PCP) for controlling the page or the entire program is sent out before the pattern signal and color signal packets.

By the way, in the still image broadcast receiving apparatus proposed so far, if a test signal other than the still image signal exists in a predetermined 12 horizontal scanning period in which the still image signal is to be superimposed in the vertical blanking period,
There was a problem that still images could not be accurately reproduced. Here, the test signal includes, for example, a vertical signal inserted into the vertical blanking period of the video signal.
Examples include interval test signal (hereinafter referred to as VITS signal). In addition, in conventional still image broadcast receiving devices, if the number of superimposed still image signals increases or decreases during broadcasting, the storage order of each still image signal stored in the buffer memory is disrupted, and the still image for one frame is In some cases, it was not possible to reliably reproduce the

Therefore, it is an object of the present invention to provide a still image that can reliably reproduce a correct one-frame still image even when a test signal is inserted during the vertical blanking period or when the number of superimposed still image signals increases or decreases. An object of the present invention is to provide a video broadcast receiving device.

To summarize, this invention devises buffer memory address assignment and address designation in the case where a still image signal for multiple lines and multiple buckets is simultaneously superimposed and transmitted on a television signal during a vertical blanking period. By doing,
It is designed to allow accurate movement.

Hereinafter, specific embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a still image broadcast receiving apparatus which forms the background of this invention and to which this invention is applied. In the figure, an antenna 1 receives a television signal and provides it to a tuner 2. This television signal includes, in addition to a normal video signal, a still image signal superimposed during the vertical blanking period. The tuner 2 selects a desired channel from the television signal on which the still image signal is superimposed, amplifies the signal of the channel, converts it to a video intermediate frequency, and supplies it to the video intermediate frequency amplification circuit 3. After the video intermediate frequency amplification circuit 3 amplifies and detects,
The signal is converted into a video signal and provided to the video amplification circuit 4 and sampling circuit 7. The video amplification circuit 4 supplies the video signal to the output interface circuit 5 to display a normal television image on a CRT display (cathode ray tube) 6.

On the other hand, the sampling circuit 7 extracts only the still image signal superimposed during the vertical blanking period from the television signal and supplies it to the buffer memory 8. Since the bit rate (for example, 5.73 Mbit/sec) of the still image signal to be sent out is much faster than the data processing speed of the central processing unit (hereinafter referred to as CPU) 9, the buffer memory 8 temporarily stores one packet of the still image signal. The stored contents are stored and read out as necessary during one field period until a new still image signal of the next field is received. In addition,
Details of the storage area of the buffer memory 8 and the writing control of video signals will be explained in detail with reference to FIGS. 2A and 2B, which will be described later. The contents stored in the buffer memory 8 are stored in the CPU 9 during one field period after one packet of the desired still image signal selected by the still image program selection device 10 is sent out.
The data is processed and read by. For this purpose, the CPU 9 has a memory (ROM) 11 that stores programs, a memory (RAM) 12 that includes a storage area used for data processing, a pattern memory 13, and a color memory 14 connected to the CPU 9 via a bus line 16. Connected. pattern memory 13
has a storage capacity of the number of pixels for displaying a still image on the CRT display 6. The color memory 14 has a capacity of total coloring units. The bus line 16 includes a data bus line for transmitting data, an address bus line for transmitting address data of each memory, and a control bus line for controlling reading or writing of each memory.

The CPU 9 data-processes the still image signal stored in the buffer memory 8 based on the program in the ROM 11, controls writing of the pattern signal included in the still image signal into the pattern memory 13, and
The color signal included in the still image signal is stored in the color memory 14.
Write control to. In this way, the buffer memory 8
The operation of transferring and storing the contents to the pattern memory 13 and color memory 14 is repeated until one frame of a still image (for example, 204 horizontal scanning lines) is stored. As a result, one page worth of data of the selected desired still image is stored in the pattern memory 13 and color memory 14.

The read control circuit 15 sequentially specifies the read addresses of the pattern memory 13 and color memory 14 in synchronization with the horizontal scanning of the CRT display 6. The pattern signal read from the pattern memory 13 and the color signal read from the color memory 14 are
given to output interface 5 and synthesized
Displayed on CRT display 6.

Next, the buffer memory 8 which is a feature of this invention
The details of how to allocate the addresses of the storage areas and the write or read control of the buffer memory 8 will be explained.

FIGS. 2A and 2B are diagrams schematically showing the storage areas of the buffer memory 8, and in particular, FIGS.
The figure shows the storage area of the buffer memory 8.
The figure shows a state in which still image signals are stored in the buffer memory 8. In the figure, the buffer memory 8 of this embodiment includes a storage area for 12 horizontal scanning lines (12 packets). Each storage area includes a storage area of 34 bytes (272 bits) including pixel signals and various control signals per packet of still image signal. In the figure, the addresses of storage areas corresponding to one packet are shown in the Y-axis direction, and the addresses of storage areas included in each storage area are shown in the X-axis direction. Therefore, buffer memory 8 includes X-axis and Y-axis address lines for specifying areas for writing or reading, respectively.
In other words, the Y axis specifies a group of storage areas (storage areas) included in the buffer memory 8. On the other hand, the X-axis specifies a storage area for bit data constituting a still image signal in one group specified by the Y-axis.

By the way, when the vertical blanking period is divided by the horizontal scanning period as described above, the timing at which one packet of still image signal is superimposed on the television signal is the 10th H from the start of the vertical blanking period. (273H for even feeds
There are a maximum of 12 periods from the 21st H (284th H) to the 21st H (284th H). However, during the 12H period in this vertical blanking period, a test signal other than the still image signal (for example, a VITS signal) exists for several hours, and it is difficult to imagine that the maximum number of still image signals (12H) is always superimposed. Not exclusively. Therefore, in the present invention, in view of such a situation, the buffer memory 8 is arranged in a one-to-one manner for each horizontal scanning period from the 10th H to the 21st H from the start of the vertical blanking period. The addresses are selected as 12 storage areas shown on the Y-axis, and each storage area consists of a storage area for storing one horizontal scanning line, that is, one packet of the still image broadcast receiving device. The feature is that it can be specified by address.

To be more specific, the first and second addresses on the Y axis
Address...The 12th address is the 10th H, 11th H,...21st H from the start of the vertical blanking period, respectively.
The eyes correspond. For example, if the still image signal is in the 14th to 16th H and
When superimposed on the 4H section of 21H, the still image signal of each horizontal scanning line is stored at the address in the Y-axis direction of the diagonally shaded portion of the buffer memory 8, as shown in FIG. 2B. In other words, CPU9
specifies each address 1 to 12 on the Y axis sequentially from the 10th H timing from the start of the vertical blanking period, and from 1 to 272 on the X axis during the period in which one address on the Y axis is specified. Y-axis and X-axis address data are generated so as to sequentially specify the addresses of .

Now, when multiple data packets are superimposed at the same time, data for one page of a still image broadcast program exists only in the same H interval (for example, the 14th H), and data packets in different H intervals The transmission form of the still image signal is selected so that the signals do not straddle each other. Therefore, when the CPU 9 processes data and writes still image signals to the pattern memory 13 and color memory 14 to form one still image, it is difficult to determine in which H interval the selected still image program exists. is important. because,
While receiving a still picture signal, the data of the same H section must be transferred and stored in the pattern memory 13 and color memory 14 until one page of the still picture program is completed. Otherwise, an inconvenience such as still images of different pages being displayed over one page may occur.

By the way, if the broadcasting station always sends out a fixed number of H still image signals, there will be no problem if the CPU 9 processes the data in the order of the still image signals of each packet stored in the buffer memory 8. However, during broadcasting, the number of superimposed still image signals may naturally increase or decrease. Even in such a case, according to this embodiment, each of the 12H of the total H interval in the vertical blanking period is assigned to each Y-axis address of the buffer memory 8, so that in the process of data processing by the CPU 9, the buffer memory Y of the still image signal stored in 8
It is always possible to know in which H interval the still image signal is superimposed from the axis address. Therefore, when data is transferred from the buffer memory 8 to the pattern memory 13 and color memory 14, data of different H sections are not mixed or displayed.

Furthermore, this embodiment can exhibit its features even when a test signal such as a VITS signal is present.
For example, if the VITS signal is extracted by the extraction circuit 7 and stored in the buffer memory 8, it will be processed as a still image signal that has no relation to the still image signal, resulting in a completely abnormal screen. . In order to prevent this, the sampling circuit 7 needs to distinguish between still image signals and signals other than still image signals so that the VITS signal and the like are not stored in the buffer memory 8. However, since test signals such as the VITS signal take various forms, identifying them requires a complex circuit and is extremely expensive. Therefore, if the buffer memory 8 is configured to include storage areas that correspond one-to-one to all H sections of the vertical blanking period, as in this embodiment, the test signal will not be stored in the buffer memory 8 by mistake. However, by incorporating in the CPU 9 program the number of H in the vertical blanking period in which a test signal such as the VITS signal falls, the data corresponding to that H interval can be ignored. There is an advantage that the sampling circuit 7 can reliably display a still image without having to specially distinguish between VITS signals and the like. However, it is assumed that the ROM 11 stores in advance a program for supporting the H number of the VITS signal in the vertical blanking period.

Note that instead of the method of specifying the H section in which the VITS signal exists using a program, various other methods can be considered. That is, since the superimposition position of the VITS signal is unstable, the following method may be used. For example, in connection with the CPU 9, a plurality of preset switches corresponding to all H sections of the vertical blanking period are provided, and the presence of the VITS signal is manually instructed to the CPU 9 by turning each preset switch on or off. You can also.

As described above, according to the present invention, by devising the structure of the storage area of the buffer memory and the method of specifying addresses, it is possible to determine in what state the still image signal is superimposed during the vertical blanking period,
Even when a signal other than the still image signal is superimposed, the still image signal can be accurately received, and the still image can be reliably reproduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram which forms the background of this invention and to which this invention is applied. FIGS. 2A and 2B are diagrams schematically showing the storage area of the buffer memory, which is a feature of the present invention. In the figure, 1 is an antenna, 2 is a tuner, and 3
is a video intermediate frequency amplification circuit, 4 is a video amplification circuit, and 5 is a video intermediate frequency amplification circuit.
is an output interface circuit, 6 is a CRT display (cathode ray tube), 7 is a sampling circuit, 8 is a buffer memory, 9 is a CPU, 10 is a program selection device,
11 is a ROM, 12 is a RAM, 13 is a pattern memory, 14 is a color memory, 15 is a read control circuit,
16 indicates a bus line.

Claims (1)

[Scope of Claims] 1. A still image broadcast receiving device that displays a still image by receiving a still image signal superimposed on a vertical blanking period of a television signal and a clock signal synchronized with the still image signal, comprising: A receiving means for receiving a signal, having a storage area corresponding to a certain number (n) of horizontal scanning lines, each storage area having an area for storing still image signals of a plurality of pixels to be displayed in one horizontal scanning line. a buffer memory including a buffer memory; when the vertical blanking period is divided by the time of one horizontal scanning period, the storage area of the buffer memory is 10th from the start of the vertical blanking period;
Addresses corresponding to each of the predetermined number (n) from the th horizontal scanning period to the predetermined number (n) are assigned, and still image signals for each horizontal scanning line received by the receiving means are transferred to the buffer memory during the vertical blanking period. writing means for writing a corresponding address of a CRT display; and a still image for each horizontal scanning line stored in the buffer memory in response to selection of a mode in which a still image is to be displayed on the CRT display. A still image broadcast receiving device comprising display control means for reading out signals and displaying them on the CRT display. 2. The constant number (n) is 12, and each storage area of the buffer memory corresponds to a period from the 10th horizontal scanning period to the 21st horizontal scanning period from the start of the vertical blanking period. The still image broadcast receiving device according to claim 1, to which an address is assigned. 3. The writing means includes a plurality of preset switches corresponding to each divided period when the vertical blanking period is divided by the time of the one horizontal scanning period, and each of the preset switches corresponds to a still image. 2. The still image broadcast receiving apparatus according to claim 1, wherein a period of signals other than the still image signal that corresponds to a certain period of the signal other than the still image signal is preset.