JPS6251022B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an error retransmission control device, and more particularly to an error retransmission control device when a transmission error or omission of an identification code for identifying a data signal in a facsimile or the like occurs.

A general transmission control procedure for data communication is shown in FIG. 1, taking facsimile as an example. In facsimile, the first step is to set the original to be sent on a transmitter and establish a data link via a telephone line. When the data link is established, the transmitter sends an inquiry signal ENQ to the receiver, the receiver responds by sending an acknowledgment ACK to confirm reception readiness, and then the sender sends an inquiry signal ENQ to the receiver. A control signal CONT for initial conditions such as transmission speed is transmitted, and an acknowledgment ACK is received from the receiving side. Now the image data PIX
It is now possible to send sequential image data PIX1,
PIX2,... are sent to the receiving side. Here too,
When the receiving side detects an error in image data (such as PIX4), the receiving side sends a retransmission request signal RQ and waits for recovery of the erroneous data. When the transmitting side detects the retransmission request signal RQ, the transmitting side retransmits the image data PIX4 previously stored in the memory. If this retransmitted data is received without error,
Data transmission continues. When the final image data PIXn to be transmitted is sent and correctly received, the transmitting side transmits an image data end signal END, and upon receiving ACK from the receiving side, transmits a transmission end signal FIN to terminate the transmission.

Figure 2 shows conventional methods such as facsimile transmission and
2 is a block diagram of a receiver retransmission control device. A signal to be transmitted is inputted from a signal input terminal 1 and stored in a memory 2, while the same input signal passes through a changeover switch 3 and has a test bit added thereto by a test bit addition circuit 4. This method of adding check bits is realized, for example, by a method such as a cyclic redundancy check (hereinafter abbreviated as CRC). The data to which the check bits (CRC) have been added is further processed by the modem interface 5 as an image data identification code (referred to as a picture flag, hereinafter referred to as FP) to identify that it is an image data signal.
) is added, is appropriately modulated by the modem interface 5, and is sent to the transmitting side input/output terminal 8.
is output to a communication line 9 such as a telephone line. At this time, the data signal in time series is the picture flag.
FP, image data PIX, check bit CRC, picture flag FP, image data PIX, etc. are sent in this order. Of course modem interface 5 and 1
It is well known that a training signal TRS is first sent in order to establish and confirm the data link of the line.

Now, the modulated signal sent through line 9 passes through receiving side input/output terminal 10, is demodulated by modem interface 11, and is introduced into error detection circuit 12 and memory 13 as a digital signal. Here, when the picture flag detection circuit 14 detects the picture flag FP, the error detection circuit 12
, and performs error detection on the image data PIX to which the previously introduced CRC check bit has been added. If there is no error in the data, the received data is assumed to be correct and is derived from the memory 13 and sent to the received data output terminal 17.

On the other hand, if an error is detected, the error detection circuit 1
2 activates the retransmission request circuit 16, which generates the retransmission request signal RQ and sends the modem
It is sent from the receiving side input/output terminal 10 via the interface 11. This retransmission request signal sent through line 9 is applied to retransmission detection circuit 6 via transmitting side input/output terminal 8 and modem interface 5, and this retransmission request is detected. At this time, the retransmission control circuit 7 is immediately activated, the switch 3 opens a path through which only the transmission data previously stored in the memory 2 passes, and the retransmission data signal is transmitted in exactly the same manner as described above. , is received.

FIG. 3 is a time chart illustrating the transmission and reception described above. The transmitted data is received by the communication line 9, as shown in FIG. 3a, with a delay of T1 time, as shown in FIG. 3c. On the receiving side, the picture flag FP is detected, and the error detection circuit 12 is activated to detect errors in the image data. If it is determined that the image data PIX1 is erroneous, a retransmission request signal RQ shown in FIG. 3d is immediately sent out. As shown in FIG. 3b, this RQ signal detects the retransmission request signal RQ after a time T2 which is the sum of the time delay of the communication line 9 and the time delay required for retransmission control. The transmitting side has already transmitted the image data PIX2 at this point, and after completely transmitting this PIX2, the transmitting side waits for T3 time when the retransmission request signal RQ is cut off, and then reestablishes the data link between the modems. A training signal TRS is emitted from the receiver to the receiver. Following this, the picture flag FP, the previously received erroneously received image data PIX1, and the check bit CRC are sequentially transmitted. If this retransmitted image data is received correctly, the image data PIX2,
PIX3,... is transmitted.

By the way, in the conventional error retransmission control device described above, if the picture flag, which should be the standard for error detection, becomes erroneous due to various causes during the transmission process, and if it is mistaken for a control signal on the receiving side (for example, a control signal), the picture flag is used as a reference for error detection. All of the specified image data is dropped, and it cannot be detected as an error. Furthermore, if the ratio between the number of bits constituting a picture flag and the number of bits constituting image data is increased, the error detection ability can be expected to improve in terms of probability, but the number of image data bits will increase in the event that a picture flag is dropped. This has the drawback of increasing the risk of data loss.

This invention was made for the purpose of eliminating the drawbacks of the conventional ones as described above, and it detects errors in data specified by a data identification code by referring to detection bits, and also detects errors in data specified by a data identification code by referring to detection bits. If data is not specified by this data identification code after the above predetermined time, it is detected that the data identification code is erroneous, and a data retransmission request is made in response to each error detection. Provided is a highly reliable error retransmission control device that enables data retransmission for any error in an identification code.

The above objects and other objects and features of the invention will become more apparent from the following detailed description with reference to the drawings.

FIG. 4 is a block diagram of an error control device on the receiving side showing an embodiment of the present invention. Analog data input from the receiving side input/output terminal 10 is converted into a digital signal by the modem interface 11, stored in the memory 13 via the receiving data line 11a, and sent to the error detection circuit 12.
Also included. Also, ENQ shown in Figure 1,
Control flag detection circuit and picture flag to identify data such as CONT, END or FIN
It is also introduced into the detection circuit 14 of the FP. counter 1
8 means, for example, the picture flag FP has 16 bits.
If it has a bit configuration, it is a counter that counts 16 bits or more and outputs a significant output signal after time T4 shown in FIGS. 5A and 5B. And this counter 18 is the modem interface 1
Training indicator output line 11b from 1
At the time when the indicator output signal (indicated by c in FIGS. 5A and 5B) is received, the image data immediately before the continuous image data is determined to be "no error" by the error detection circuit 12. It is activated when the Further, this counter 18 is reset when the control flag detection circuit 15 detects a control flag. Then, when counting is started again and a predetermined number of bits are counted (counting is performed beyond the point at which the counter 18 outputs a significant signal), it is automatically reset to return to the initial state. .

The picture flag detection circuit 14 detects whether or not a picture flag FP has been received. If it has been received, the picture flag detection circuit 14 detects whether or not the picture flag FP has been received. Outputs a detection signal indicating. This detection signal is the 5th A
It is shown as a picture flag in Figure b and Figure 5B. For example, when one unit of the data signal is 1024 bits and the CRC check bit is 16 bits, the detection signal indicating the presence of data is the picture flag FP.
It rises when the clock pulse ends, and falls after counting the clock pulses 1040 times with the counter. on the other hand,
If reception of the picture flag FP is not detected, no detection signal indicating the presence of data is output.

Now, after the counter 18 has counted the pulses for T4 time, the picture flag monitoring circuit 19 starts the fifth pulse.
One pulse is generated as shown in Figure A and Figure 5B d. As shown by the arrows in FIGS. 5A and 5B, this pulse determines whether the picture flag (shown in FIGS. 5A and 5B b) detected by the picture flag detection circuit in FIG. It is determined whether If it is determined that the flag is set, the data existing during that period is recognized as image data, and if the error detection circuit 12 determines that there is no error, the image data is transferred from the memory 13. It is output to the output terminal 17. If it is determined that there is an error, the conventional retransmission request control described with reference to FIGS. 2 and 3 is performed.

As soon as the picture flag monitoring circuit 19 recognizes that the picture flag is not set, it issues a retransmission command signal as shown in FIGS. 5A and 5B to the counter 20 shown in FIG. 4. The counter 20 is activated by this command signal. This counter 20 counts the expected image data length, and causes the retransmission request circuit 16 to send out a retransmission request signal RQ after an elapsed time T5 (shown in FIGS. 5A and 5B). At this time, although image data subsequent to the image data has been received, it is completely ignored when a retransmission command is issued.

FIGS. 5A and 5B show time charts of the above-mentioned operations. In FIG. 5A, PIX1 in the received data shown in a is received correctly, and PIX2
The picture flag is set due to some abnormality in the transmission system.
This shows what happens when FP is misrecognized or dropped. Note that an x mark attached to the FP indicates erroneous reception. The same applies below. In Figure 5B,
Picture flag of PIX5 in the received data shown in a
FP is erroneous. Immediately after receiving a new training signal TRS after a retransmission request, the PIX5's picture flag FP is erroneously received again.

First, the case of FIG. 5A will be explained. In FIG. 5A, the pulse signal of the picture flag monitoring circuit 19 is emitted T4 time counted by the counter 18 from the time when the image data PIX1 is determined to be "no error". , the picture flag shown in b
FP is monitored, but since the picture flag FP is not set, PIX2 is immediately activated as shown in e.
A retransmission command is issued to retransmit the . This also activates the counter 20, counts up to the data end of the error data PIX2, and sends out a retransmission request signal as indicated by f after time T5. The transmitting side accepts the retransmission request, sends the training signal TRS, and subsequently sends and receives the previously erroneous data. The counter 18 starts counting from the rising edge of the training indicator output shown in c, and after T4, outputs a monitoring pulse to check the state of the flag. This time it was received correctly,
Since the flag is set, there is no need to request retransmission, and if the image data is "error-free", terminal 1
Output from 7. Continued data PIX3, PIX
The same applies to 4.

Next, the case of FIG. 5B will be explained.
The first half of FIG. 5B is performed in exactly the same manner as the control shown in FIG. 5A. In particular, here, a case is shown in which the picture flag FP immediately after the training signal TRS is erroneously recognized. In this case, after receiving the training signal, the counter 18 is started by the rise of the training indicator output shown in FIG. Thereupon, the retransmission command is immediately followed by a retransmission request after time T5, and the subsequent sequence is exactly the same as that described in FIG. 5A.

According to the above embodiment, even if the picture flag, which controls the image data, is erroneously recognized by the receiving side or dropped due to a cause in the transmission system, the image data can be checked by simply adding a monitoring circuit using a simple counter to the conventional device. Continuity can be guaranteed. This invention will be particularly effective for data transmission with a high data compression rate.

As described above, according to the present invention, an error in the data specified by the data identification code is detected by referring to the check bit, and the data is specified by the data identification code after a predetermined time equal to or longer than the code length of the data identification code. If this is not done, it is configured to detect an error in the data identification code and request data retransmission in response to each error detection. This has the effect of providing an error retransmission control device that enables retransmission and is useful as an extremely reliable error retransmission system.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram showing a general transmission control procedure for data communication. FIG. 2 is a block diagram of a conventional error retransmission control device. FIG. 3 is a time chart showing the operation of the error retransmission control device shown in FIG. FIG. 4 is a block diagram of an error retransmission control device on the receiving side according to an embodiment of the present invention. 5A and 5B are time charts showing the operation of the error retransmission control device shown in FIG. 4. In the figure, the same reference numerals indicate the same or equivalent parts, 2 is a transmitting side memory, 4 is a check bit addition circuit, 6 is a retransmission request detection circuit, 7 is a retransmission control circuit, 5 and 11 are modem interfaces, 12 1 is an error detection circuit, 13 is a reception side memory, 14 is a picture flag detection circuit, 16 is a retransmission request circuit, 1
8 and 20 are counters, and 19 is a picture flag monitoring circuit.

Claims (1)

[Claims] 1. An error retransmission control device that requests retransmission from the receiving side to the transmitting side in response to an error in data transmitted and received from the transmitting side to the receiving side, comprising: a memory that stores the data and outputs the data upon receiving a retransmission request signal; a switch that switches between the data and the output data of the memory in response to the retransmission request signal; and a data identification code and a data identification code for the output data of the switch. a code detection circuit that outputs a detection signal indicating the presence of data to the receiving side during the data signal period and the test bit period when the data identification code is detected; an error detection circuit that is activated by a detection signal from a code detection circuit and detects an error in the data to which the check bit has been added; a timer means which is reset by outputting a significant signal after a predetermined time equal to or longer than the code length of the data identification code; and a timer means which is reset by outputting a significant signal after a predetermined time equal to or longer than the code length of the data identification code; and a retransmission request circuit that transmits the retransmission request signal to the transmitting side in response to each error detection signal of the code monitoring circuit or the error detection circuit. Retransmission control device.