JPS6243237A - Transmission system for looped network - Google Patents

Abstract

PURPOSE:To increase the accommodating efficiency of a low-speed terminal and to reduce the transmission delay by constituting a low-speed channel of a multi-frame structure with the same slot covering two frames. CONSTITUTION:The information sent from a transmission controller means the repetition of a frame consisting of plural transmission units called time slots. The frame length is kept constant and a transmitting device transfers information by means of said time slots. When the transfer information is produced in a fixed quantity and in a fixed period, the idle time slots are occupied in the number equal to the transfer quantity of information for transmission of information. However, the information quantity to be transferred increases for each unit as the transmitting speed is increased. In this respect, a multi-frame structure of low-speed transmission units is applied with suppression kept for the frame length. Then the same time slot covering two frames is allocated to a single low-speed transmission unit. Here only the frames of the same number can be used in the conventional system. However the delay amount equal to a single frame only is needed compared with the conventional system requiring the delay amount equal to many frames. In such a way, the characteristics of a transmission system for circular network is considerably improved.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a transmission method for a ring-shaped local area network, and particularly to a transmission method suitable for a multimedia integrated LAN that provides various speed channels from high speed to low speed. Regarding.

[Background of the invention]

Conventionally, the transmission method of a ring network that integrates multimedia is STDM (Synchronization), which has a frame structure of a fixed length.
Onous Time DiviSion Multi
plθX), and its frame length is specified in NEC Technical Report Vol.
“C&C-NET Loop” by Ito et al.
6830 Universal Link System", or longer to accommodate even the slowest terminals (synchronous type), or " OKINET-2000MODEL 3
As discussed in the document titled ``0'', the basic transmission unit is set to a certain degree (for example, 64 Kb/S) to suppress the frame length, and even the items smaller than that are transmitted by occupying the basic transmission unit. This may depend on what speed terminals are mainly accommodated, but the former has excellent accommodation efficiency but increases transmission delay, so it is more suitable for accommodating low-speed terminals; Although the terminal accommodating efficiency is poor, the transmission delay is short, so it is suitable for accommodating high-speed terminals.However, no consideration has been given to a transmission method that is excellent in both accommodating efficiency and transmission delay.

[Purpose of the invention]

An object of the present invention is to provide a ring network transmission system that has high accommodating efficiency for low-speed terminals and requires short transmission delays.

[Summary of the invention]

The present invention focuses on the fact that if there is a transmission channel that goes around the master station twice, it is possible to transfer information between arbitrary stations, and the low-speed channel has a multi-frame structure and is formed by the same slot spanning two frames. It was made in a similar manner.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG. 1st
The figure is an example of a transmission time chart in a ring transmission system to which the present invention is applied, and shows the features of the present invention. Here, the vertical axis shows the physical position of the transmission device, and the horizontal axis shows the passage of time. A transmission management device is placed at the most downstream position. As shown in the figure, the information sent from the transmission management device is a repeated frame consisting of a plurality of transmission units called time slots. The length of the frame is kept constant, and the transmission device uses these time slots to transfer information. It is known that integrated transmission of various traffic characteristics is easy with this type of transmission system. That is, when a certain amount of transfer information is generated at a certain period, an empty time slot can be occupied and transmitted by the amount of transfer information. However, as the transmission speed increases, the amount of transmission per unit increases, so it becomes difficult to provide low-speed transmission units while keeping the frame length suppressed. Therefore, a multi-frame configuration as shown in the figure is adopted, and the same time slot spanning two frames (this example shows an adjacent case) is assigned to one low-speed transmission unit. In the conventional method, only frames with the same number need to be used. However, regarding the amount of delay, compared to the conventional method which requires multi-frame delay, only one frame is required, and it can be seen that the characteristics can be significantly improved.

Note that in high-speed information transfer, multiple frames are used, so it is only necessary to identify the time slot number without being aware of the frame number.

FIG. 2 is an example of the overall configuration of a ring transmission system to which the present invention is applied. As shown in the figure, various information processing devices 1121 to 1121 are distributed and installed at various locations within the premises, such as factories, buildings, and university campuses.
31 respectively join one transmission system via transmission devices 11 to 16 and exchange information with each other. In the figure, there are 4 transmission devices, and each transmission device has 2 or 4 transmission devices.
An example is shown in which two information processing devices are connected.
The present invention does not limit these numbers.

Now, information processing devices connected to a transmission device are roughly classified into the following two types depending on the characteristics of their transmission traffic.

1) Type 1: Immediacy is critical and requires data transmission with a long hold time.

2) Type 2: Data transmission that does not require much immediacy and has a relatively short hold time.

In the figure, type 1 devices include an ITV camera 26 and a monitor 2.
8. Telephone 25, 29, FAX 22, PBX (Priv
ate Branch Exchange) 23, and Type 2 has the remaining computers 24, L A N (L
27 PCs via local AreaNetwork, filing device! Although E30, printer 31, and workstation 21 are mentioned, it is possible to handle these information transfers having different traffic characteristics in a mixed manner on the same line. It is well known that circuit switching (including dedicated allocation) is generally suitable for the former type of information, and packet switching is suitable for the latter, and a network that allows both types of information to coexist is called a hybrid switching network.

The present invention describes a transmission system for accommodating especially low-speed circuit-switched terminal-to-terminal communications.

FIG. 3 shows an example of the format of information flowing through the circular transmission line. Figure a) shows the overall transmission format employing a multi-frame configuration, where the number of frames N is usually determined by a low-speed transmission unit.

Each frame takes a form in which a frame header is added to the beginning of a plurality of time slots, as shown in b) of the same figure. Each time slot has the same length and is used for data transfer. The frame header section is used for purposes such as synchronization and transmission control.

The frame header has the format shown in C) in the same figure, and each area is used for the following purposes.

SYN: Indicates the beginning of a frame. Each transmission device detects this and synchronizes the frame.

Fixed bit pattern or modulation/demodulation It is realized by violation in .

No: A number indicating the frame order on the multiframe. It is necessary to recognize this when transmitting between low-speed terminals, but it is not necessary between high-speed terminals.

AC: A bit that indicates whether or not the time slot in the frame can be used for transmission. This is also valid only in low-speed transmission units. If not, the slot in the frame is used for the second time on the transmission path. show something.

LNG: Indicates the distance (number of frames) between two time slots, which are low-speed transmission units.

This is due to the signal-circular delay of the circular transmission line. will be determined.

Each time slot has the format shown in d) in the figure, and each area is used for the following purposes.

F/B: Indicates whether the time slot is empty or not.

This bit is kept busy prior to transmission. Transmission of the time slot between certain terminals need to be occupied by

M: Indicates whether data information exists in the time slot. This bit is set when transmitting data information, and is reset after the time slot has made one cycle on the transmission path. Referenced by the corresponding receiver.

DATA: Enter data information into this area.

FIG. 4 shows an example of the hardware configuration of the transmission device.

Among the transmission devices, only one station operates as a transmission management device at a time, but the hardware configuration and functions are all the same. Therefore, transmission management can be backed up by all transmission devices. The method for selecting one management device from a plurality of transmission devices is usually based on a unique priority given to each device, but the explanation will be omitted here. The transmission device 11 includes one line control module 111 and an information processing device for each transmission line 3! ! ! (For example, 22) The two modules, which are composed of corresponding interface modules 111, are connected via two sets of data transfer buses INBUS and 0UTBUS, resulting in a transmission device structure that allows for a wide range of scales.0 line control Module 110 further comprises the following components:

1) Receiving circuit (1101) This is a circuit that receives signals from a transmission line and returns them to digital information, and further includes the following functions.

a) Optical receiver module b) Bit synchronization circuit C) Timing conversion circuit d) Demodulation circuit e) Serial/parallel conversion circuit 2) Transmission circuit (1102) A circuit that converts digital transmission information into a signal suitable for the transmission path and transmits it. , and further consists of the following functions:

a) Optical transmission module b) Modulation circuit C) Parallel/serial conversion circuit 3) Multiplexer (1103) Selects and switches between the output from the frame delay circuit 1104 and the output from the frame generation circuit 1105. The transmission device 1
When the frame delay circuit 1104 functions as a transmission management device, switching is required, but when it functions as a normal transmission device, only the frame delay circuit 1104 is fixedly selected.

4) Frame delay circuit (1104) The transmission device! ! When 11 functions as a transmission management device,
The memory (RAM) in this allows the signal on the circular transmission line to be
Adjust so that the cyclic delay is an integral multiple of the transmission frame. In a normal transmission device, it functions simply as a register and no delay is inserted.

5) Frame generation circuit (1105) The transmission device! ! When 11 operates as a transmission management device,
Since this section directly relates to the present invention, the details thereof will be described later.

6) Bus control circuit (1106) An amount equivalent to the operation delay time of the time slot access circuit 1111 is inserted into the relay path from INBUS to 0UTBUS, allowing the interface module to send and receive information on the bus. In addition, it is in charge of bus control such as bus contention management and timing supply.

The interface module 111 also includes the following functional units.

1) Time slot access circuit (1111) This circuit performs functions such as identifying frames, occupying and releasing time slots, and receiving and passing information based on occupied time slots.
Directly related to the present invention.

Details will be described later.

2) Transmission control circuit (1112) This performs transmission/reception buffer management of transfer information, various transmission error checks, disassembly/assembly of transfer data into time slots, and other transmission/reception controls.

3) Device interface circuit (1113) Controls various interfaces between the main interface module 111 and the information processing device 22.

Next, the flow of information within the ring transmission device made up of these components will be explained.

When the transmission device 22 operates as a transmission management device, frame information from the frame generation circuit 1105 is transmitted to the transmission line 3 via the multiplexer 1103 and the transmission circuit 1102.
sent to. The information that has gone around the transmission path is output to INBUS through the receiving circuit 1101, passes through the bus control circuit 1106, goes to 0UTBUS, and then enters the frame delay circuit 1104.

In addition, in the reception operation, the information output to the INBUS through the reception circuit 1101 is sent to the time slot access circuit 1111,
Transmission control circuit 1112, device interface circuit 11
13 to the information processing device 22.

Similarly, the transmission operation follows the reverse route and is output from the time slot access circuit 1111 to 0UTBUS.

At this time, output from bus control circuit 1106 to 0UTBUS is prohibited. Then, it passes through the frame delay circuit 1104, multiplexer 1103, and transmission circuit 1102, and is output to the line.

FIG. 5 shows a more detailed hardware configuration of the frame generation circuit 1105. This circuit is functionally a frame header generation circuit 11050 and a time slot generation circuit 11051.
It is broadly divided into

The frame header generation circuit 11050 further includes the following components.

1) SYN register (110501) A register that stores frame synchronization patterns.

2) No register (110502) A register for temporarily storing the contents of the frame counter 110507.

3) AC pattern ROM (110503) A ROM that stores the access permission bit issued for each frame, a frame counter 1105 that specifies the address of this memory.
Subtractor 1 showing the output of 07 and the signal delay of the circular transmission line
(Use the output of 10508)N.

4) LNG register (110504) A register that stores interframe distance information and subtractor 1
Store the output of 10508.

5) Dummy register (110505) A register for sending the remaining dummy information of the frame header.

6) Time slot counter (tto506) A counter for counting the number of time slots to be transmitted. When one frame is counted, one output is output.

7) Frame counter (110507) Counter that indicates the transmission frame number, @ count value No register 1
10502, ACno (Turn ROM110503
, is supplied to the subtractor 11050g.

8) Subtractor (110508) Outputs the difference between the transmitted frame number and the received frame number as an absolute value. This value indicates the amount of delay between the circular transmission lines and is used for presenting the interframe distance in units of low-speed transmission.

9) No case storage register (11050) This register stores the number of the received frame and outputs a value to the subtracter 110508.

On the other hand, the time slot generation circuit 11051 consists of the following components.

1) Time slot generation register (110511) A register for storing empty time slot patterns, and receives free/busy bits from the F/B delay RAM 110512 in the case of time slots for low-speed transmission units.

2) F/B delay RAM (110512) A memory for delaying free/busy bits in the slot by multiple frames when a time slot for low-speed transmission unit is received.

3) F/B extraction circuit (110513) A circuit for extracting free/busy bits from the received time slot for low-speed transmission units.

Although it has been explained that this circuit 1105 functions when the transmission device t11 operates as a transmission management device, the operation flow in that case will be described below.

As shown in the transmission format example in Figure 3, the SYN
The contents of register 110501 are multiplexer 1105
Selected by 2. Following that, No register 11
0502, AC pattern ROM 110503, LNG
The register and dummy register 110505 are selected in sequence and the frame header is output. Thereafter, the contents of the time slot generation register 110511 are output for the time slots in the frame, completing one frame.

Repeat this from now on.

FIG. 6 shows the AC pattern R in the humum generation circuit 1105.
This example of the access permission bit pattern stored in the OM 110503 shows a case where the number of time slots in a frame is set to 24. In the vertical direction, the interframe distance in units of low-speed transmission, and hence the signal-to-circuit delay time of the circular transmission path, is taken, and in the horizontal direction, the frame number within the multiframe is shown.

Although the interframe distance changes depending on the system scale, the maximum value is kept at 3 here. In a system like the one shown in the transmission time chart in Figure 1, the interframe distance is 0,
In other words, since the same time slots in adjacent frames constitute a low-speed transmission unit, the AC bit of the frame header output from the transmission management station is 1010... This means that the time slots of odd-numbered frames Indicates that it can be used for transmission.

FIG. 7 shows a detailed hardware configuration of the time slot access circuit 1111 in the interface module 111.

Information received from INBUS is received in the reception register 111101.
, slot header decoder 111102, AC detection circuit 111103, LNGNo register 111104, and o register 111105, respectively. Received data to the transmission control circuit 1112 is sent via the reception register 111101.

The slot header decoder 111102 detects the header pattern of each time slot and sends the results to the slot occupancy detection circuit 111125 and the transmission slot detection circuit 111124.
, - itinerary slot detection circuit 111123. It is transmitted to the reception slot detection circuit 111122.

The AC detection circuit 111103 detects the access permission bit in the frame header and sends the result to the slot occupancy detection circuit 1.
Call 11125.

LNGNo register 111105 Stores interframe distance information in the frame header. Its output is the adder 111
109, and is used to identify a frame to be paired with the occupied frame.

The No. register 111105 stores currently received frame number information. Its output is receive frame register 111107, transmit frame register 111106
, are supplied to comparators 111108.111112.

The transmitting frame register 111106 stores the frame number including the time slot used for transmission, the pair frame register 111110 stores the frame number paired with the transmitting frame, and the receiving frame register 11110 stores the frame number that is paired with the transmitting frame.
7 is used to store each frame number including the time slot used for reception. Comparators 111112 and 111108 respectively determine whether the frame currently being received is the relevant frame. Since the numbers of the transmitted frame and the paired frame are not the same, each comparison is performed by switching in a time-division manner using the multiplexer 111111.

For time slots, the slot counter 111
11g, the current time slot number is counted, and the numbers used for transmission and reception are stored in the transmission slot register 111114 and the reception slot register 111, respectively.
116. Comparator 111
115.111117 each determine whether the time slot currently being received matches the stored value.

On the other hand, the received data from the transmission control circuit 1112 is output to 0UTBUS via the multiplexer 111119 and the transmission register 11111g. In addition, there is a feeder 111121 to the slot for sending header information of the slot, which becomes the other input of the multiplexer 111119 via the slot header register 111120.

Time slot access circuit 1111 and transmission control circuit 1
In addition to the transmitted and received data, there are the following signals between the transmission control circuit 1112 and the time slot access circuit 1111: transmission request, transmission end, and detection of a command addressed to the own station.

In the opposite direction, the slot is occupied, transmission starts, reception starts, and reception ends.

The slot occupancy detection circuit 111125 is for notifying the slot occupancy after receiving a transmission request, and outputs an occupancy output when a free time slot is received in a frame with an accessible bit.

This signal is also conveyed to the slot header coder 111121 to change the transmission time slot to busy.

It also serves as a storage signal for the transmission frame register 111106 and pair frame register 111110.

The transmission slot detection signal 111124 is being transmitted,
Notifies that the time slot to be used has been detected and starts transmission, and also sends the Tsuda coder 1111 to the slot.
21 is busy and has data. Detection determination requires a match of the frame number and timeslot number and that the timeslot is busy. If the time slot is free, an error has occurred and transmission is stopped. Further, when receiving a transmission end signal, it instructs the slot header coder 111121 to release the occupation of the time slot.

- During transmission, the circular slot detection circuit 111123
After transmission, it is detected that the time slot has completed one cycle, and the slot header coder 111121 is instructed to send out no data.

During reception, the reception slot detection circuit 111122
Notify that the time slot to be used has been detected as reception activation. Note that if the time slot is in a free state, it is assumed that the transmission has ended and a reception end signal is output.

〔Effect of the invention〕

According to the present invention, even if a multi-frame configuration is adopted, the transmission delay is only one frame, and low-speed terminals can be efficiently accommodated.

[Brief explanation of drawings]

Fig. 1 is an example of a transmission time chart showing the features of the present invention, Fig. 2 is an example of the overall configuration of a ring transmission system, Fig. 3 is an example of a transmission format, Fig. 4 is an example of the hardware configuration of a transmission device, and Fig. 5 6 is an example of a hardware configuration of a frame generation circuit, FIG. 6 is an example of a pattern of access permission bits, and FIG. 7 is a hardware configuration diagram of a time slot access circuit. 3...Transmission line, 11-16...Transmission device, 21-3
DESCRIPTION OF SYMBOLS 1... Information processing device, 110... Line control module, 111... Interface module, 1101
...Reception circuit, 1102 ... Transmission circuit, 1103.
... multiplexer, 1104 ... frame delay circuit, 1105 ... frame generation circuit, 1106 ... bus control circuit, 1111 ... time slot access,
1112...Transmission control circuit, 1113...Device interface circuit, 11050...Frame header generation circuit, 11051...Time slot generation circuit, 1
10501...SYN register, 110502...
No register, 110503...AC pattern ROM
, 110504...LNGNo register 10505.
...Dummy register, 110506...Time slot counter, 110507...Frame counter. 110508...Subtractor, 110509...NO storage register, 110511...Time slot generation register, 110512...F/Bi extension RAM, 110
513・F/B cutout, rotation i1.11052...Multiplexer, 111101...Reception register, 111
102...Slot header decoder, 111103.
・・AC detection, 111104・LNG 17 register, 111105・N OL/register 111106・・
・Transmission frame register, 111107...Reception frame register, 111108.111115゜1111
17, 111112... Comparator, 111109
... Adder, 111110 ... Pair frame register, 111111.111119 ... Multiplexer, 111113 ... Slot counter, 111114
... Transmission slot register, 111116 ... Reception slot register, 111118 ... Transmission register,
111120...Slot header register, 1111
21...Slot header coder, 111122...
Receive slot detection circuit, 111123... - circular slot detection circuit, 111124... transmission slot detection circuit, 111125... slot occupancy detection circuit. Figure 2 α, 71! Format FH Ni-4 to 1/2゛TS: Time slot 8, Frame format SYN: Frame n period pattern NO: Frame Urinyu △O Near 2 cess iT name LNG; Frame head format F/B: E Reso Busy M: i "Pattern l, i d, tie to slot phon, door 1L + 78 ref's')
5 15) Procedural amendment (formality)

Claims (1)

[Claims] 1. Transmission that goes around the line twice in a circular transmission system consisting of a plurality of information processing devices, a transmission device that accommodates them and executes information transfer, and a transmission line that connects the transmission devices in a circular series. A ring network transmission method characterized by transferring information between transmission devices in units of units. 2. In claim 1, the transmission unit consists of time slots with the same number spanning two transmission frames within a multi-transmission frame generated by one of the transmission devices that functions as a transmission management device. A ring network transmission system characterized by: 3. In claim 2, the transmission management device:
means for generating a multi-transmission frame by assigning a series of numbers to a fixed-length transmission frame consisting of a plurality of time slots; means for adjusting the time during which a signal goes around a line to an integral multiple of the transmission frame length; A means for determining from the track orbit time that there is a time slot used for low-speed terminal transmission within the frame and displaying this within the frame, and a means for determining that there is a time slot paired with the low-speed terminal transmission time slot within the frame. A ring network characterized in that it has a means for determining the line orbit time and displaying it in the frame, and a means for delaying display information as to whether or not the low-speed terminal transmission time slot is empty by the multi-transmission frame. Transmission method. 4. In claim 2, the transmission device includes means for capturing an empty time slot and transmitting data, and when detecting a low-speed terminal transmission time slot addressed to the device itself, the transmission device uses the transmission management device as a reference. , means for receiving data from the time slot when the corresponding transmission transmission device is located upstream, or from another time slot paired with the time slot when the corresponding transmission transmission device is located downstream; 1. A ring network transmission system characterized by having means for returning a time capture time slot to empty.