JPS6232740A - Time slot multiplexing type circular transmission system - Google Patents

Abstract

PURPOSE:To improve transmission efficiency by occupying an idle slot out of time slots formed by one of information processors connected to a circular line to transmit data between transmission equipment, and after the end of transmission, returning the occupied slot to the idle slot on the receiving side. CONSTITUTION:Plural transmission equipments ST1-ST6 are connected to the circular line 3 and one of them is used as a transmission control device. The transmission control device forms and supplies a fixed transmission unit (time slot TS) and respective transmission equipments ST1-ST6 use an idle ST out of the plural ones. Each time slot TS is constituted of the fixed number of frames, a circuit exchange area in each frame is restricted, but a packet exchange area is not restricted. A circuit exchange is applied to an ITV camera, a monitor, a telephone set, a FAX, a PBX, etc. which are characterized by high immediateness and a long holding time and a packet exchange is applied to a personal computer group, a printer, etc. After the end of information transmission, the occupied time slot is returned to an idle slot on the receiving side. Consequently, information transmission having different traffic characteristic can be efficiently attained on the same line.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a ring-shaped local area network transmission system, and is particularly suitable for a digital integrated network that can accommodate a mixture of devices with different traffic characteristics by time slot multiplexing. This paper relates to a time slot multiplexed ring transmission system.

[Background of the invention]

The conventional digital integrated network transmission method is described in Oki Electric Research and Development, No. 124, Vol. 51, Nn3 (1
“0KINET-20” by Takahashi et al.
Packet switching and circuit switching (including fixed connections) as discussed in the document entitled ``00M0DIIEL30''
When accommodating transmissions with different characteristics at the same time, each transfer area was allocated in a semi-fixed manner, so until the transmission path was shared to a high degree, for example, the allocated capacity of both could be made variable according to load fluctuations. No consideration was given to this.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a time slot multiplexed ring transmission system that dynamically varies the ratio of packet switching and circuit switching areas depending on load conditions, thereby enabling a high degree of sharing of transmission paths.

[Summary of the invention]

The present invention focuses on the fact that if there is no need to remember the time slot number used by the transmitting station in packet switching type information transfer, there is no need to set limits on the usage area or the number of timeslots used. The time slot is released at the corresponding receiving station or transmission monitoring station.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG. 1st
The figure shows one feature of the present invention with an example of a transmission time chart in a ring transmission system to which the present invention is applied. Here, the vertical axis shows the physical position of the transmission device, and the horizontal axis shows the passage of time.To simplify the explanation, the case where there are four transmission devices is shown, and the most upstream and downstream positions are It is arranged so that the transmission management device is located next to it. As shown in the figure, the information continuously sent from the transmission management device takes the form of a frame consisting of a plurality of fixed time slots (6 in this example), and is a hybrid switching system that performs both circuit switching and packet switching. In the system, it is necessary to indicate the area used within each frame in some way. In this system, which allows for dynamic area allocation, the circuit switching area has a limited usage range (in this example, time slots 1 to 3), but the packet switching area can use the entire frame. Various methods can be considered to indicate which exchange each time slot is used for, but in this example, an indicator is provided at the beginning of the time slot to indicate this.

The traffic example shown in this example is as follows.

(1) Transmission device 1t (ST^) has time slot T S
z and performs periodic information transfer. Information can be received by any station, but for example, transmission device B (STa
).

(2) At time t1, a request for packet transmission occurs in the transmission bag R(S' T c). The amount of data to be transferred is small, and only one time slot is required. However, the transfer destination spans multiple transmission devices, such as ST^ and STa.

(3) At time tz, a request for packet transmission occurs in the transmission device STa. The transfer amount is equivalent to 3 time slots,
The destination is STc.

After the request is generated, the transmission device STc first detects that the time slot TSa is empty, so it immediately occupies this time slot and transfers information. Transmission device ST^.

STa receives this in the next frame. However, since neither station erases the information, the transmission management station erases it.

After the transmission device STB request is generated, the time slot T S
1 is received. Since the transfer cannot be completed with just 6 slots, which detect that these are empty and start transmitting information, the next time slot T S 2 is verified, but this is already occupied by the transmission device ST^ and the next time slot is Wait for the slot. Thereafter, time slots TSa, T
The transmission device S T c, which transmits information using Sa and is designated for reception, uses slots TSz, TSδ, and TSa.
All are returned to the empty layer and erased from the transmission path.

From the above explanation, an overview of the method of dynamic allocation of circuit switching and packet switching and the method of erasing packet data has been provided, and the implementation method will be explained in more detail below.

Figure 2 is an example of the overall configuration of a ring transmission system to which the present invention is applied.As shown in the figure, various information processing devices are distributed and installed in various locations such as factories, buildings, and university campuses! 21-31
each joins one transmission system via transmission devices 11 to 16 and exchanges information with each other. The transmission devices are connected in a ring by a bit-serial transmission path 3. Although the figure shows an example in which there are six transmission devices and two or four information processing devices are connected to each transmission device, the present invention is not limited to these numbers.

Now, information processing devices connected to a transmission device are roughly classified into the following two types based on the characteristics of their transmission traffic.

(1) Type 1: Immediacy is critical and requires data transmission with a long hold time.

(2) Type 2: Data transmission in which immediacy is not required and the hold time is relatively short.

In the figure, type 1 devices include an ITV camera 26 and a monitor 2.
8. Telephone 25, 29. FAX22. PBX (Pri
vate Branch Exchange) 23, and the remaining calculators 24. for type 2. LAN (L
PC group 27, filing device [30, printer 31, and workstation 21] are mentioned via the local area network), but it is possible to handle these information transfers with different traffic characteristics together on the same line. . It is well known that circuit switching (including dedicated allocation) is generally suitable for the former type of information, and packet switching is suitable for the latter, and a network that allows both types of information to coexist is called a hybrid switching network. To be more specific, as shown in Figure 1, in type 1 circuit-switched information transfer, the time slot (
If the capacity is large, use multiple units, and if the capacity is small, use one unit.
After determining whether to use a portion of the slot (it is also possible to use a portion of the slot), the slot is occupied for a certain period of time to transfer information. Therefore, a certain transfer cycle can be ensured.

On the other hand, in the type 2 packet switching type, it is sufficient to simply find an empty slot and transfer the data, but it is necessary to add header information to all slots indicating which device the data is being transferred between.

FIG. 3 is an example of a transmission format. First, (a) consists of a plurality of time slots for data transfer which are time-divided in a frame format, and a frame header located at the beginning and mainly used for frame synchronization. To identify which time slot it is, it is common to detect a synchronization signal within the frame header. The time slots are all of equal length and the area allocation for circuit switching and packet switching is as described in FIG. Figure (b) shows the time slot format for packet exchange. The slot header information includes access control characters AC,
There is a destination address DA, a source address SA, and an LNG representing the effective data length within the slot. In addition, it consists of a DATA section for transferring data information and an Fe2 section for detecting whether or not there is a transmission error in the DATA. Bit allocation in the access control character AC starts from the P/C bit, which indicates whether the time slot is used for packet switching or circuit switching, and if the slot is used for packet switching, indicates whether this slot is empty or occupied. F for distinguishing
/B bit, and a rotation monitor bit M for preventing the transmission management device from endless rotation of the slot. On the other hand, an example of the time slot format for line switching has the configuration shown in FIG. 2(c). It is the same as for packet exchange except for the F/B bit in the first access control character. In this example, one time slot is further divided into a plurality of low-speed channels CH, and each channel has a table section FBT indicating whether the channel is empty or occupied. The channel part is usually data information only.

FIG. 4 shows an example of the hardware configuration of the transmission device.

Only one of the transmission devices operates as a transmission management station at a time, but the hardware configuration and functions are the same. In other words, transmission management is in a form that allows backup by all devices. The method for selecting one transmission management station from a plurality of transmission devices is usually based on the priority assigned uniquely to each device, but the details will be omitted. The transmission equipment W111 includes one line control module 11 for the transmission line 3 and an interface module (for example, 21) for the information processing device (21).
For example, one module consisting of 112) is connected via two sets of data transfer buses INBUS and 0UTBUS and a transfer control bus C0NTR0L, resulting in a highly expandable structure. Line control module 1
11 further consists of the following components.

(1) Signal transmitting/receiving circuit (1111) This is a circuit for transmitting and receiving digital signals and mainly consists of the following functional sections.

(a) Receiving circuit (1111) This circuit amplifies signals, extracts timing components, reproduces digital signals, etc., and has a photoelectric conversion function when the transmission line is an optical fiber code.

(b) Demodulation circuit (11112) Return digitally modulated signal to original NRZ data6 (c) Modulation circuit (11113) Converts NRZ data into a code suitable for transmission.

(d) Transmission circuit (11114) Drives signals. If the transmission line is an optical fiber cord, it has an electrical/optical conversion function.

(2) Frame control circuit (1112) This circuit generates, maintains and manages frames and mainly consists of the following functional units.

(a) Frame header detection circuit (11121) Establishes frame synchronization by detecting synchronization patterns, monitors frame header information, etc.

(b) Delay memory (11122) This function, which compensates for the amount of ring circulation delay so that the number of frames on the transmission path becomes an integral multiple, operates only in the transmission management device.

(C) Frame generation circuit (11123) This function for generating frame headers and time slots also operates only in the transmission management device.

(d) Multiplexer (11124) Switches between frame information (frame header and empty time slot) and relay information (including transmission data) as information to be sent to the transmission path. Valid only for transmission management devices.

(3) Time slot management circuit (1113) This is a part that manages time slot access control for the entire ring, and operates only in the transmission management device. It mainly consists of the following functional parts.

(a) Access control byte check circuit (11131)
Detect the contents of the access control byte at the beginning of the receive timeslot. More specifically, it is checked whether the receiving time slot is being used for information transfer.

(b) Access control byte generation circuit (11132) Generates a new access control byte to be sent. Specifically, it is initialized when a time slot that is not in use is received.

Further, the interface module 112 is further subdivided into the following functional units.

(1) Time slot access circuit (1121) This is for packet transmission and performs functions such as capturing an empty time slot when a transmission request is made, detecting a time slot addressed to the own station, and erasing unnecessary slots.

(2) Transmission control circuit (1122) This performs functions such as managing transmission and reception buffers of transfer information, checking transmission errors, disassembling and assembling into slots, and adding and separating slot header information.

(3) Equipment interface circuit (1123) Information processing bag [
Controls the interface with 21.

(4) Bus access control circuit (1124) Executes control when competing with other interface modules for the right to use the bus that exists between the line control module 111 and the interface module. The specific method is IEE
There are E802.3 standard C8MA/CD, etc.

The flow of information within the ring transmission device made up of these components will now be explained.

The signal received from the transmission line 3 is sent to the line control module 11.
The signal is taken in from the receiving circuit 11111 in the signal transmitting/receiving circuit 1111 of 1, and is converted into parallel NRZ by the demodulating circuit 11112.
converted into data. In the transmission management device, this information is stored in the delay memory 11122, and after a certain delay is applied to the INB.
Output to US. Other transmission devices simply allow the signal to pass through as is. The information output to INBUS is sent back to the time slot management circuit 1113 of the line control module 111.
After a certain length of delay, this time 0UTBU
If there is a transmission within the transmission device, output from the slot management circuit 1113 to 0UTBLIS is prohibited, and transmission from the transmission interface module is permitted6 Therefore, the transmission information is sent to the multiplexer on 0UTBUS. The signal is then sent out to the transmission line 3 again via the multiplexer 11124 in the frame control circuit 1112, the modulation circuit 11113 in the signal transmitting/receiving circuit 1111, and the transmitting circuit 11114.

FIG. 5 shows a more detailed hardware configuration of the time slot management circuit 1113. The access control byte check circuit 11131 can be broken down into the following components.

(1) Slot counter (111311) Notified by the frame control circuit 1112 that a frame synchronization signal has been detected, the counter is initialized, hexagonally bound, and measures the time slot header position.

(2) Receive register (111312) A register for temporarily storing data information from INBUS (3) Access control byte decoder (111313) In the receive register 111312 after receiving the indication of the time slot header position from the slot counter 111311 above. Verify the contents of the access control byte.

On the other hand, the access control byte generation circuit 11132 can also be divided into the following components.

(1) Transmission register (111321) A register for temporarily storing relay information to be output to OUTBUS.

(2) Byte delay register (111322) INBUS
A certain delay is applied to the relay information from 0UTBUS and then sent to 0UTBUS. This delay compensates for the time required for the interface module to rewrite the slot header information.

(3) Access control byte pattern register (1113
24) This register stores an access control byte that is newly sent when a time slot that is not in use for information transfer is detected.The pattern is as follows in the bit pattern of the access control byte AC shown in FIG. 3(b). P/C=
P, F/B=F, and M=O.

(4) Access control byte pattern register (1113
25) This register stores an access control byte to be newly sent when a time slot in use for information transfer is detected. Only the M bit is set to 0 and the other bits are relayed as they are.

(5) Selector (111323) This selector selects one of the following three forces and sends relay information to the transmission register 111321. That is, (1) access control byte pattern register 111324 (2) access control byte pattern register 111325 (3)
Select each output of the byte delay register 111322.

Here, cases (1) and (2) are selected only when the access control byte is passed.Normally, (3) is selected.

Now, regarding the flow of information within this circuit, the reception information input from INBUS is normally sent to the reception buffer 111312,
Byte delay register 111322, selector 11132
3. Goes out to 0UTBUS via the transmission buffer 111321. However, when the access control byte is stored in the receive buffer 111312 by the slot counter 111311, the relay is interrupted after the same amount of delay time as the byte delay register 111322 has elapsed, and the selector 11132
3 sends out the contents of the access control byte pattern register. The access control byte decoder 111313 determines which pattern register is selected. That is, if M=O, the slot is not used for information transfer, so one of the access control byte pattern registers 111324 is set, and if M=1, the slot is used for information transfer, so one of the access control byte pattern registers 11
1325 are each selected. Therefore, when a time slot with a group address specified is sent from any transmission device, the access control byte of the time slot first passes through the transmission management device, the M bit is rewritten to O, and then the access control byte of the time slot is rewritten to O by the transmission management device. Occupancy will be released (F/B=F).

FIG. 6 shows a more detailed hardware configuration of the time slot access circuit 1121 in the packet transmission interface module. The information received from INBUS is sent to the access control byte pattern detection circuit 112101, 11.
2106.112112 and address detection circuit 112
102 and 112105, and also sent to the transmission control circuit 1122. On the other hand, the transmission information from the transmission control circuit 1122 side is sent out as 0UTBUS via the multiplexer 112113. Multiplexer 112113
Other inputs of the access control pattern register 11
There are 2115 and 112114. Each access control byte pattern detection circuit 112101.112106.112
112 has the following functions.

(1) 112101 is P/C=P, F/B=B, M=
1, and is used to verify the reception of time slots in which the own transmission device is designated to receive by an individual address6.
It is also used for occupying/releasing the time slot at the same time.

(2) 112106 is P/C=P, F/B=B, M=
This is for detecting O, and is used to verify the reception of time slots in which the own transmission device is designated to receive by the group address.

(3) 112112 is for detecting P/C, F/B=F, M=O, and is used to capture empty slots for transmission.

Each address detection circuit 112102.112105 performs the following functions.

(1) 112102 verifies whether or not the time slot is addressed to the own transmission device based on the individual address.

(2) 112105 verifies the time slot addressed to its own transmission device based on the group address (including global).

Each access control byte pattern register 112114-112115 has the following contents.

(1) 112114 stores a pattern (P/C=P, F/B=F, M=O17) for releasing the occupation of the reception time slot.

(2) 112115 stores a pattern including p/c=p, F/B=F, and M=1 in order to notify the acquisition of an empty time slot.

The circuit operation in this configuration will be explained in detail below using a typical case.

(1) When receiving a time slot addressed to the own device using an individual address In this case, the access control byte pattern detection circuit 112
A match is detected by 101 and the flip-flop 112
103. Next, address detection circuit 1121
Since a coincidence output is output at 02, the AND gate 112104 is turned on, and the transmission control circuit 1122 is notified of the start of reception via the OR gate 112109. At the same time, the output of the AND gate 112104 prompts the access control pattern register 112114 to send out the signal, thereby releasing the occupation of the reception time slot.

(2) When receiving a time slot addressed to the own device using a group address A match is detected by the access control byte pattern detection circuit 112106 and stored in the flip-flop 112107. Subsequently, since the address detection circuit 112105 outputs a match, the AND gate 11210g is turned on, and a reception start notification similar to (1) is transmitted to the transmission control circuit 1122 via the OR gate 112109. However, in this case, the access control byte is not rewritten.

It can also be seen that a time slot with a group address is not received by each transmission device unless it passes through the transmission management device once.

(3) When transmitting from the own device First, a transmission request signal is output from the transmission control circuit 1122 and stored in the flip-flop 112110. This output is sent to AND gate 112111.

It is passed to bus access control circuit 1124. When the interface module obtains the right to use 0UTB (Is) in the bus access control circuit 1124, this result is returned to the input side of the AND gate 112111.In this state, when the access control byte pattern detection circuit 112112 detects an empty slot, the AND gate 112111 output turns on and notifies the transmission control circuit 1122 of the start of transmission.At the same time, the access control pattern register 1
2115 and makes the time slot occupied.

〔Effect of the invention〕

According to the present invention, when transmitting information by packet switching,
Since the transmitting device does not need to perform ring-to-cycle elimination of used time slots, it is possible to use any number of time slots at any position within the frame, making it possible to dynamically change the allocation of packet switching and circuit switching areas. Can provide transmission system.

[Brief explanation of drawings]

FIG. 1 is an example of a transmission time chart showing the features of the present invention, and FIG. 2 is an example of the overall configuration of a ring transmission system. Figure 3 shows an example of a transmission format, Figure 4 shows an example of the hardware configuration of a transmission device, Figure 5 shows an example of the hardware configuration of a timeslot management circuit, and Figure 6 shows the hardware of a timeslot access circuit of a packet transmission interface module. FIG. 3... Transmission line, 11-16... Transmission device, 21-
31... Information processing device, 111... Line control module, 112... Interface module, 1
111... Signal transmission/reception circuit, 1112... Frame control circuit, 1113... Time slot management circuit.

Claims (1)

[Claims] 1. Consisting of a plurality of information processing devices, a ring transmission device that accommodates them and executes information transfer, and a transmission line that connects the ring transmission devices in series in a ring, one of the transmission devices is In a device that functions as a transmission management device and sequentially generates fixed transmission units called time slots, and occupies empty time slots for information transfer between transmission devices, the occupied time slots are designated for reception. A time slot multiplexed circular transmission system characterized in that a transmission device or a transmission management device returns to an empty time slot. 2. In claim 1, when the destination address of the occupied time slot indicates an individual transmission device, the determination of the device to empty the occupied time slot is made by the transmission device designated for reception; A time slot multiplexing type multiplex transmission system characterized in that when the destination address indicates a plurality of transmission device groups, a transmission management device performs the transmission. 3. In claim 1, the transmission device includes (a) a signal transmitting/receiving circuit installed in correspondence with the transmission line, (b) a frame control circuit for maintaining and managing a frame configuration composed of a plurality of time slots, and ( C) A line control module consisting of a time slot management circuit that maintains and manages time slots, and (d) A time slot access circuit that accesses time slots and is installed for information processing equipment connected to the transmission equipment. A time slot multiplexed circular transmission system characterized by comprising: (e) a transmission control circuit having a function of transmitting information between transmission devices; and (f) an interface module consisting of an equipment interface circuit that interfaces with an information processing device. . 4. In claim 3, the time slot management circuit includes (a) means for detecting whether or not the time slot is in use for information transfer each time the time slot goes around; and (b) means for detecting whether the time slot is in use for information transfer or not. A time slot multiplexed ring transmission system characterized by having means for initializing and retransmitting the data when it returns. 5. In claim 3, the time slot access circuit includes (a) means for detecting an empty time slot and notifying that it is occupied; and (b) means for notifying the transmission management device that the time slot is occupied. means for notifying that the time slot is used for information transfer; (c) means for determining whether the received time slot is addressed to the device itself; and (d) means for further determining that the time slot is addressed to the device itself. A time slot multiplexed circular transmission system characterized by having means for determining whether or not devices other than the own device are designated to receive reception, and returning the occupation instruction of the time slot to empty when there is no reception designation for any device other than the own device. .