JPS6240914B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention receives a still image signal superimposed and sent during the vertical retrace period of a television signal, and displays characters, figures, etc. on a picture tube. The present invention relates to a still image signal receiving device that displays still images.

[Background of the invention]

There are several known still image broadcasting systems that use television radio waves to transmit still image information such as text and graphics without interfering with normal television signals. This still image broadcasting method is
The television signal has a vertical blanking period (hereinafter referred to as
1 horizontal scanning period (abbreviated as VBL period) (hereinafter referred to as 1H)
Still image information from several programs is multiplexed and inserted into a receiver (abbreviated as ), and the receiving side selects the necessary still image information from these programs and stores it in a field memory circuit.
This is read out and displayed on a television picture tube. A representative example of this still image broadcasting system is the still image broadcasting system C (text broadcasting system) announced by NHK General Research Institute. (Refer to Television Society Television System/Circuit Research Fund 11-4, August 22, 1989, ``Television Multiplexing System for Character Information''). The signal format of the still image broadcasting method C and an outline of the receiver will be described below.

FIG. 1 shows a signal waveform in still image broadcasting C method. Figure a shows the standard television signal VBL.
The signal waveform when still image broadcasting is multiplexed in the 20th horizontal scanning period (hereinafter abbreviated as 20th H) of the period is shown, and FIG. The still image broadcasting signal is multiplexed into the VBL period of the standard television signal, as shown in Figure 1a, and its position is as follows in the first field.
It's 20H and the next field is 283H. Since this still image broadcast signal is within the VBL period, it does not appear on the screen of an ordinary television receiver.

In addition, as shown in Figure 1b, the still picture broadcast signal consists of a 14-bit identification signal and a 240-bit still picture information signal, and the transmission speed is 3.58 MHz, which is the color subcarrier frequency of television (hereinafter abbreviated as fs). Each
The frequencies are 2/5 and 8/5. Therefore, each bit is 0.70μS and 0.17μS, respectively, which is 1H.
Medium, the identification signal is approximately 9.8 μS, and the still image information signal is approximately
It is 41.9 μS, which is about 51.7 μS for the entire still image broadcast signal.
It occupies a time of μS. The still picture broadcast signal is formed by a normal binary pulse code in which the white level of the standard television signal is logic "1" and the pedestal level is logic "0".

The identification signal is always the signal start identification signal (hereinafter referred to as
(abbreviated as STX) 1 bit, still image deletion identification signal 1
It consists of a 4-bit program identification signal that indicates the type of still picture information signal, and an 8-bit scanning line number identification signal that specifies the display position on the picture tube. In addition, pattern information such as text and graphics is transmitted as is in the still image information signal, and if 200 lines of the same program are lined up in the order of arrival, one screen's worth of text and graphics will be reproduced.

FIG. 2 shows the configuration of a conventional receiver that receives the above signal. In FIG. 2, 1 is an antenna, 2 is a tuner, 3 is an intermediate frequency amplification section, 4 is an envelope detection section, 5 is a video signal processing section, 6 is a deflection section, and 7 is a picture tube. The blocks 1 to 7 above have exactly the same functions as blocks in conventional television receivers.

8 is a changeover switch, A is a still image receiving section input terminal, B is a still image receiving section output terminal, and 10 is a still image receiving section. 11 is a still image broadcasting signal extraction circuit, 1
2 is a field memory circuit, 13 is a mixed circuit, 1
4 is a control circuit, 15 is a synchronous reproducing circuit, 16 is a timing signal generation circuit, 17 is an operation panel, and 21 is a buffer memory circuit.

Television broadcast waves arriving at the antenna 1 are tuned by a tuner 2, converted into an intermediate frequency signal, and then amplified by an intermediate frequency amplification section 3. The amplified intermediate frequency signal is detected by the envelope detection section 4, becomes a video signal, and is sent to the changeover switch 8 and the still image reception section 1.
0 input terminal A. The video signal input from the input terminal A is supplied to the synchronization reproduction circuit 15, the still image broadcast signal sampling circuit 11, and the mixing circuit 13. The synchronization reproduction circuit 15 reproduces a vertical synchronization signal, a horizontal synchronization signal, and a color subcarrier signal from the video signal, and supplies them to the timing signal generation circuit 16. Based on these signals, the timing signal generation circuit 16 generates pulses generated only in the horizontal period when still image broadcasting signals are multiplexed, clock pulses with frequencies of 2/5fs and 8/5fs, etc. generate various necessary timing pulses at 10;
Supply to other circuits. Further, in the still image broadcasting signal extraction circuit 11, from the input video signal, as shown in FIG.
Extract only the still image broadcast signal shown in . The extracted still image broadcast signal is sent to the buffer memory circuit 21.
At the same time, the control circuit 14
Also supplied. The control circuit 14 selects only the signal having the identification signal of the program selected on the operation panel 17 from among the still image broadcast signals and reads it out from the buffer memory circuit 21. Then, only the still image information signal therein is stored in the field memory circuit 1 corresponding to the display position specified by the scanning line number identification signal.
The data is controlled to be recorded in the second storage area. At the same time, the control circuit 14 also performs control such as erasing the displayed still image according to the still image erasure identification signal. The field memory circuit 12 is composed of a digital memory that stores still image information signals for one screen, and usually uses a random access memory (hereinafter abbreviated as RAM) or a shift register, and has a large capacity.
There are 48000 (240 x 200) bits. The still image information signal stored in the field memory circuit 12 is read out in synchronization with the scanning of the television screen, and is superimposed on the synchronizing signal portion of the input video signal in the mixing circuit 13 to display a still image. It becomes a video signal.

A video signal for displaying this still image is output to the changeover switch 8 via the output terminal B. When the switch 8 is connected to the a side, a normal video signal is selected, and when the switch 8 is connected to the b side, a video signal for displaying a still image is selected. The selected video signal is supplied to the video signal processing unit 5 and the deflection unit 6, where it is subjected to signal processing and reproduces a normal video screen or a still image screen on the receiving tube 7. The above is an outline of the conventional receiver.

In such a receiver, the configuration of the control circuit 14 is complicated, resulting in a very large circuit scale.

[Purpose of the invention]

An object of the present invention is to eliminate the above-mentioned drawbacks by using a central processing circuit, so that a target signal of the still image signal can be accurately taken into the central processing circuit in synchronization with the still image signal, and the processing can be performed. The purpose is to enable processing.

[Summary of the invention]

In order to achieve the above object, the present invention provides a central processing circuit and configures the buffer memory circuit and the field memory circuit as independent circuits, so that all functions of the control circuit are performed by the central processing circuit. , controls the transfer of still image signals from the buffer memory circuit to the field memory circuit, and at the same time makes it possible to insert characters and pictures into still images, and to enlarge and display them. Furthermore, in order to completely synchronize the processing in the central processing circuit with the still image signal, a means for detecting the arrival of the still image signal is provided, and an interrupt is generated in the central processing circuit every time a still image signal arrives. did.

[Embodiments of the invention]

Hereinafter, specific embodiments of the present invention will be described with reference to the drawings.

FIG. 3 is a block diagram showing an embodiment of the present invention, and is a block diagram when the present invention is applied to the still image receiving section 10 described above. In FIG. 3, the same parts as in FIG. 2 are designated by the same reference numerals. Further, 18 is a central processing unit (hereinafter abbreviated as CPU), 19 is a still image signal arrival detection circuit, 20 is an operation panel, an operation panel interface circuit that transfers signals from 17 to the CPU 18, and 22 is a buffer memory block. 23 is a feed memory clock circuit, 24 is a program memory circuit for storing instructions to be executed by the CPU 18, 25 is a data line, and 26 is an address line.

By using this configuration, all the functions of the control circuit 24 in the conventional receiver shown in FIG.
At the same time, the buffer memory 21 and main memory 12 are independently connected via the data line of the CPU 18.
Other devices can be easily connected.

Hereinafter, the operation of the apparatus shown in FIG. 3 will be explained in detail using FIGS. 4 and 5. Figures 4 and 5 are
This is an example of a circuit block in which the circuit block of FIG. 3 is constructed with a more detailed circuit, and the same parts are designated by the same reference numerals. In Figure 4, 27
is a flip-flop (hereinafter abbreviated as FF) circuit, 2
8 is a NOT (hereinafter abbreviated as NOT) circuit, and 29 is A- which converts the analog signal into a binary digital circuit.
30 to 32 are AND circuits, 33 is an OR circuit, 34 is a 254-bit shift register, and 35 is an address decoder circuit. In addition, in Figure 5, 36 and 37 are NOT circuits, and 38 to 44 are AND circuits.
circuit, 45 is a 48000-bit random access memory (hereinafter abbreviated as RAM), 46 is an OR circuit, 47
is a latch circuit, and 48 is an address decoder circuit.

In FIG. 3, the video signal input from the input terminal A of the still image receiving section is outputted to the still image broadcast signal extraction circuit 11, the synchronous reproduction circuit 15, and the mixing circuit 13, as in the case of FIG. In the signal extraction circuit 11, the input video signal is converted into a binary digital signal by the A-D conversion circuit 29, and outputted to the AND circuit 30, where the timing signal generation circuit 1
The binary digital signal is gated by the 20th H and 283rd H pulses input from 6, and only the still image broadcast signal is extracted. The extracted still image signal is output to a still image signal arrival detection circuit 19 and a buffer memory circuit 21. On the other hand, in the buffer memory lock circuit 22, only the 283rd H is connected to the AND circuit 32.
The clock pulse of 2.54 bits per 1H supplied from the timing signal generation circuit 16 is passed through the OR circuit 33 to the buffer memory circuit 2.
It is output to the 254-bit shift register 34 within 1. Therefore, the arriving stationary signal is
The data is stored as is in the 254-bit shift register 34 in the buffer memory circuit 21 with the bit configuration shown in FIG.

Also, sections (time) other than the 20th and 283rd H.
Then, the still image signal stored in the buffer memory circuit 21 is output to the data line 25 of the CPU 18 in the following order. That is, the 20th H and 283rd H from the timing signal generation circuit 16
The pulse outputted by the detection circuit 19 is NOT
It is inverted by the circuit 28 and output to the reset input of the FF circuit 27.
Undo the reset. Since the arriving still image signal is input to the set input of the FF circuit 27, it usually takes about
The FF circuit 27 is set only for 1H, and the 20th or
Reset at the end of 283H. This FF circuit 27
The positive logic output signal is the output signal of the detection circuit 19 as it is, and is output to the CPU 18 as an interrupt signal. At this time, the 20th H and
Although pulses that are output for only 283H may be output to the CPU 18, by adopting the above configuration, it is possible to accurately know the arrival of a still image signal.

The CPU 18 starts determining the identification signal of the still image signal when the positive logic output signal of the FF circuit 27 rises. That is, the CPU 18 outputs a certain address to the address line 26 to which the address decoder circuit 35 is determined. The circuit 35 decodes this address and ORs it with the AND circuit 31.
A decode pulse is output to the circuit 33. OR33
The input pulse is directly applied as a clock pulse to the 254-bit shift register 34 of the buffer memory circuit 21, and one bit of the stored contents is read out. The read memory contents are sent to AND circuit 3
However, since the decode pulse is applied to the other input of the AND circuit 31 at this time, the stored contents are output as they are to the data line 25 of the CPU 18. By repeating the above operations, the CPU 18 can successively read each bit of the identification signal in the still image signal. The read identification signal is compared with a program selection signal input from the operation panel 17 via the operation panel interface circuit 20 to the data line 25, and it is determined whether the program is selected by the operation panel 17. If the arriving still image signal is not the selected program, the CPU 18
waits until the next arrival of a still image signal is detected. However, if the arriving still picture signal is the selected program, it is determined whether the still picture deletion identification signal is logic "1", and if it is logic "1", the memory contents of the field memory circuit 12 are Erase everything. Then, the 240-bit still image information that has arrived is transferred to the storage area of the memory circuit 12 corresponding to the scanning line position specified by the 8-bit scanning line number identification signal.

On the other hand, an example of the configuration of the field memory circuit 12 is shown in FIG.
It is configured to be separated from the CPU 18. That is, the display pulse that is output from the timing signal generation circuit 16 and becomes logic "0" only during display is output from the AND circuit 4 in the logic "0" period.
The gates 2 and 44 are closed, the logic is inverted by the NOT circuit 37, and the gate of the AND circuit 43 is opened. Therefore, the address pulse output from the timing signal generation circuit 16 is transmitted to the AND circuit 43 and the OR circuit 46.
The data is then output to 48000 bit RAM. Also, the AND
The gate of circuit 39 is also opened, but AND circuit 3
The gates 8, 40, and 41 are closed because the output signal of the AND circuit 44 is logic "0". Therefore, the 48000-bit RAM is set to the read state by the output logic "0" of the AND circuit 41, and the memory contents are read out one after another in response to changes in the address pulse output from the timing signal generation circuit 16. , the read memory contents are
Field memory circuit 12 via AND circuit 39
is output from.

Next, when the display pulse is logic "1", the gates of AND circuits 39 and 43 are closed, and the gates of AND circuits 42 and 44 are opened. Further, an address decoder circuit 48 is connected to the address line 26 of the CPU 18, and an address decoder circuit 48 is connected to the data line 25 of the CPU 18.
A latch circuit 47 is connected to each of , the output of the address decoder circuit 48 is connected to an AND circuit 44 and a latch circuit 47, and the output of the latch circuit 47 is connected to an AND circuit.
Each is connected to a circuit 42. For this reason,
When the CPU 18 outputs a certain address determined by the address decoder circuit 48 to the address line 26, the data outputted to the data line 25 at the same time is latched as is by the latch circuit 47.
48000 bits via AND circuit 42 and OR circuit 46
Output to RAM. At the same time, the AND circuit 44
Since the output signal becomes logic "1", the gates of the AND circuits 38, 40, and 41 are opened. Therefore, CPU18 has 48000 bit RAM4
address decoder circuit 48.
At the same time, specify an address for which the data is determined on the address line 26 and the address of the bit whose contents in the RAM 45 you want to change on the data line 25.
Data line 25 connected to AND circuit 41
can indicate whether to read or write the contents of the specified bit. Further, information to be written to a designated bit can be indicated on the data line 25 connected to the AND circuit 41, and information read out can be indicated on the data line 25 connected to the AND circuit 38. Therefore, a 240-bit still image information signal can be transferred during this period.

In addition, in the above explanation, we have explained that setting the address of 48000-bit RAM and specifying read/write etc. are performed at the same time, but in order to do so,
16 bits for address setting, 1 bit for reading specification,
A CPU that can process more than 19 bits in parallel, including 2 bits for writing and reading information, is required. However, if the number of times the latch circuit 47 is latched is two or three times, a widely used 16-bit or 8-bit parallel processing CPU can be used sufficiently.

As described above, when the arriving still image signal is the selected program, the CPU 18 stores it in the buffer memory circuit 21 while the display pulse output from the timing signal generation circuit 16 is at logic "1". The still image information signal of 240 bits is controlled to be transferred to the field memory circuit 12. At this time, since the display pulse outputted from the timing signal generation circuit 16 is also supplied to the CPU 18, it can be determined whether or not the still image information signal can be transferred to the field memory circuit 12. All such operations performed by the CPU 18 are stored as instructions in the program memory circuit 24.

Also, as in the case of FIG. 2, the synchronous regeneration circuit 15
reproduces various TV synchronization signals and supplies them to the timing signal generation circuit 16.
Now, various timing signals required by the circuits shown in FIGS. 3, 4, and 5 described above are generated. Next, while the display pulse is at logic "0", a still image information signal is read out from the field memory circuit 12, and is converted into a video signal for displaying a still image by the mixing circuit 13, as in the case of FIG. The signal is then output to the still image receiving section output terminal B.

Although the details of the operation of the apparatus shown in FIG. 3 have been described above, FIGS. 4 and 5 are only examples of the configuration, and the present invention is not limited to this. For example, the buffer memory circuit 21 may have the same configuration as that used in the field memory circuit 12, and a RAM capable of storing 254 bits or more may be used. In addition, the program circuit 24 is also used as the field memory circuit 12.
The CPU 18 and the field memory are configured so that they are not separated, and the still image information signal is recorded as data in the program memory circuit 24, read out by direct memory access, and the read parallel data is converted into serial data and supplied to the mixing circuit 13. However, it is possible to provide similar functionality.

〔Effect of the invention〕

As described above, according to the present invention, even when a general-purpose central processing circuit is used in a still image signal receiving device, it is possible to accurately know the arrival of a still image signal.
Accurate processing can be performed using the central processing circuit.

[Brief explanation of the drawing]

Figures 1a and b are examples of still image broadcasting systems.
A signal waveform diagram of a television signal in the NHK still image broadcasting C system. Figure 2 is a block diagram of a conventional still image broadcast receiver. Figure 3 is a still image signal receiving section in the still image broadcast receiver to which the present invention is applied. 4 and 5 are circuit block diagrams showing an example of a case where the circuit block of FIG. 3 is constructed with a more detailed circuit. 1: Antenna, 2: Tuner, 3: Intermediate frequency amplification section, 4: Envelope detection section, 5: Video signal processing section,
6: Deflection section, 7: Picture tube, 10: Still image reception section,
11: Still image broadcasting signal extraction circuit, 12: Field memory circuit, 14: Control circuit, 16: Timing signal generation circuit, 18: Central processing unit, 2
1: buffer memory circuit, 25: data line,
26: Address line, 34: 254-bit shift register, 35: Address decoder circuit, 46:
48000 bit RAM, 47: latch circuit, 48: address decoder circuit.

Claims (1)

[Claims] 1. A still image signal receiving device that receives a still image signal multiplexed with a television signal and transmitted,
still image signal extracting means for extracting the still image signal from the television signal in synchronization with a synchronization signal included in the television signal; a program storage circuit in which a processing procedure is stored in advance; and the still image signal extracting means. an auxiliary storage means connected to the still image signal extracting means for temporarily storing still image signals extracted by the still image signal extracting means; a main storage means connected to the program storage circuit for storing information displayed on the display screen; a central processing circuit that reads a still image signal stored in the auxiliary storage means according to a predetermined processing procedure stored in a program storage circuit, and writes the still image signal in the main storage circuit as information to be displayed on a display screen; The still image detection means is connected to the signal extracting means, and generates an interrupt signal to the central processing circuit according to the output of the still image signal extracting means, and supplies the interrupt signal to the central processing circuit. Still image signal receiving device. 2. In claim 1, the central processing circuit is connected to program selection means that generates a selection signal for selecting a still image signal of a desired program from still image signals that are sequentially transmitted; the still image signal stored in the auxiliary storage means when the determining means determines that the program corresponds to the program indicated by the selection signal; A still image signal receiving device characterized in that the still image signal receiving device reads and writes the still image signal into the main storage means.