JPS6237569B2 - - Google Patents
Info
- Publication number
- JPS6237569B2 JPS6237569B2 JP52122788A JP12278877A JPS6237569B2 JP S6237569 B2 JPS6237569 B2 JP S6237569B2 JP 52122788 A JP52122788 A JP 52122788A JP 12278877 A JP12278877 A JP 12278877A JP S6237569 B2 JPS6237569 B2 JP S6237569B2
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- band
- frequency divider
- division ratio
- reference frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000010355 oscillation Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 4
- 239000013078 crystal Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
- H03J5/00—Discontinuous tuning; Selecting predetermined frequencies; Selecting frequency bands with or without continuous tuning in one or more of the bands, e.g. push-button tuning, turret tuner
- H03J5/02—Discontinuous tuning; Selecting predetermined frequencies; Selecting frequency bands with or without continuous tuning in one or more of the bands, e.g. push-button tuning, turret tuner with variable tuning element having a number of predetermined settings and adjustable to a desired one of these settings
- H03J5/0245—Discontinuous tuning using an electrical variable impedance element, e.g. a voltage variable reactive diode, in which no corresponding analogue value either exists or is preset, i.e. the tuning information is only available in a digital form
- H03J5/0272—Discontinuous tuning using an electrical variable impedance element, e.g. a voltage variable reactive diode, in which no corresponding analogue value either exists or is preset, i.e. the tuning information is only available in a digital form the digital values being used to preset a counter or a frequency divider in a phase locked loop, e.g. frequency synthesizer
Description
【発明の詳細な説明】
本発明は多重バンドフエーズロツクドループ周
波数シンセサイザに関する。第１図は従来のフエ
ーズロツクドループ（以下PLLと略記する）周波
数シンセサイザのブロツク図である。１は基準発
振器、２は基準分周器、３は位相比較器、４はロ
ウパスフイルタ、５はプログラマブル分周器、６
は電圧制御発振器（以下VCOと略記する）、７は
VCOの出力、８はプログラマブル分周器の分周
比設定手段である。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multiband phase locked loop frequency synthesizer. FIG. 1 is a block diagram of a conventional phase locked loop (hereinafter abbreviated as PLL) frequency synthesizer. 1 is a reference oscillator, 2 is a reference frequency divider, 3 is a phase comparator, 4 is a low pass filter, 5 is a programmable frequency divider, 6
is a voltage controlled oscillator (hereinafter abbreviated as VCO), and 7 is a voltage controlled oscillator (hereinafter abbreviated as VCO).
The VCO output 8 is a division ratio setting means of a programmable frequency divider.
基準発振器１は周波数安定度の優れた、例えば
水晶発振器を用い、基準分周器２で基準周波数ま
で分周して位相比較器３の一方に入力する。また
電圧制御発振器VCO６からの信号はプログラマ
ブル分周器５に入力され、プログラマブル分周器
の分周比設定手段８によりセツトされたある分周
比に分周され位相比較器３のもう一方に入力す
る。両者の位相差電圧はロウパスフイルタ４によ
り平滑され、VCO６を制御し位相差をゼロにす
る様にVCOの周波数は動く。従つて分周比設定
手段８の分周比を変える事により、周波数シンセ
サイザが構成でき、分周比と、VCOの周波数は
１対１に対応する。本システムを例えばスーパー
ヘテロダイン受信機の局部発振器として使用する
場合、その受信バンド内の各チヤンネルの局部発
振周波数と最小チヤンネルスペースがわかれば、
最小チヤンネルスペースと基準周波数を等しく、
またはそれ以下に選ぶ事によつて、全チヤンネル
に対応する分周比を設定する事が可能となる。 The reference oscillator 1 uses, for example, a crystal oscillator with excellent frequency stability, and the reference frequency divider 2 divides the frequency to a reference frequency and inputs the frequency to one of the phase comparators 3. Further, the signal from the voltage controlled oscillator VCO 6 is input to the programmable frequency divider 5, divided to a certain frequency division ratio set by the frequency division ratio setting means 8 of the programmable frequency divider, and input to the other side of the phase comparator 3. do. The phase difference voltage between the two is smoothed by a low pass filter 4, and the frequency of the VCO is changed so as to control the VCO 6 and make the phase difference zero. Therefore, by changing the frequency division ratio of the frequency division ratio setting means 8, a frequency synthesizer can be configured, and the frequency division ratio and the frequency of the VCO correspond one to one. When using this system as a local oscillator in a superheterodyne receiver, for example, if the local oscillator frequency and minimum channel spacing of each channel in the reception band are known, then
The minimum channel space and reference frequency are equal,
By selecting a value higher than or equal to that value, it is possible to set a frequency division ratio that corresponds to all channels.
以上が従来のPLL周波数シンセサイザを多チヤ
ンネル受信機に応用した例であるが、受信バンド
が異なり、チヤンネルスペースが異なる２つ以上
のバンドを１ヶのPLL周波数シンセサイザで構成
する事は不可能であつた。例外として異なるバン
ドではあるが、各チヤンネルスペースが等しい
か、又は整数倍の関係にある場合に限つて、基準
周波数を小さい方のチヤンネルスペースに等しく
し、チヤンネルスペースが広いバンドの分周比設
定をその分だけとばしてプログラムするか、また
は基準デイバイダの出力取り出しをスイツチによ
つて切替える事によつて可能であつた。 The above is an example of applying a conventional PLL frequency synthesizer to a multi-channel receiver, but it is impossible to configure two or more bands with different receiving bands and channel spaces with one PLL frequency synthesizer. Ta. As an exception, if the channel spacing is equal or an integral multiple of different bands, then the reference frequency should be equal to the smaller channel space, and the division ratio setting for the band with the wider channel space should be set. This could be done by programming to skip that amount, or by switching the output of the reference divider using a switch.
しかし、チヤンネルスペースが各バンドで等し
くなく、また一方が他方の整数倍とも異なる場
合、基準周波数は、それらの最大公約数に選ばな
ければならないが、基準周波数が低くなる程、ロ
ウパスフイルタによつて、基準周波数成分のスプ
リアスがとれなくなつたり、ロツクアツプタイム
が長くなるといつた特性の劣化が避られなく、実
用上問題が多い。従つて、一般には各バンド毎に
１つのPLLを用いて多重チヤンネルPLL周波数シ
ンセサイザをつくる外はなかつた。また、バンド
を切り換えても、同じローパスフイルターが用い
られているので、フイルター時定数を最適にする
ことができず、ロツクアツプタイムが長くなつた
り、VCOの周波数制御電圧が十分平滑されずに
出力が歪んでしまうという欠点もあつた。 However, if the channel spacing is not equal in each band, and one also differs from an integer multiple of the other, then the reference frequency must be chosen to be their greatest common divisor, but the lower the reference frequency, the more it will be filtered by the low-pass filter. As a result, it becomes impossible to eliminate spurious components of the reference frequency component, and as the lockup time becomes longer, deterioration of characteristics is inevitable, which causes many practical problems. Therefore, there is generally no choice but to use one PLL for each band to create a multi-channel PLL frequency synthesizer. In addition, even if the band is switched, the same low-pass filter is used, so the filter time constant cannot be optimized, resulting in longer lock-up times and the VCO frequency control voltage not being sufficiently smoothed before being output. It also had the disadvantage of being distorted.
本発明は以上の問題を解決し、比較的簡単な構
造をもち、基準周波数成分のスプリアスが十分に
とれ、ロツクアツプタイムの増加がなく、安定な
出力の得られる多重バンドPLL周波数シンセサイ
ザを提供することを目的とする。本発明は基準分
周器を固定分周器ではなく分周比セツト可能なプ
ログラマブル分周器にした点に特徴がある。従つ
ていかなるチヤンネルスペースにも基準周波数を
合わせる事ができるので、いかなるバンドの受信
機にも使用できるばかりでなく、バンド切替時に
基準分周器の分周比を切替える事により多バンド
多チヤンネル受信機に使用できる。 The present invention solves the above problems and provides a multi-band PLL frequency synthesizer that has a relatively simple structure, can sufficiently eliminate spurious noise in the reference frequency component, does not increase lock-up time, and can provide stable output. The purpose is to The present invention is characterized in that the reference frequency divider is not a fixed frequency divider but a programmable frequency divider in which the frequency division ratio can be set. Therefore, since the reference frequency can be matched to any channel space, it can be used not only for any band receiver, but also for multi-band multi-channel receivers by switching the division ratio of the reference frequency divider when switching bands. Can be used for
以下、実施例に沿い、図面を用いて本発明を説
明する。第２図は本発明の一実施例である２バン
ドPLL周波数シンセサイザのブロツク図である。
１は基準発振器、９は基準プログラマブル分周
器、１０は基準周波数設定手段、１１はバンド切
替時の基準周波数切替手段、３は位相比較器４′
−１はロウパスフイルタ１，１２はロウパスフイ
ルタ切替スイツチ、４′−２はロウパスフイルタ
２，５はプログラマ分周器、８は分周比設定手
段、６′−１はVCO１，６′−２はVCO２，１３
はVCO切替スイツチ、１４はVCO１の出力、１
５はVCO２の出力、１６はバンド切替入力であ
る。動作は従来と同じであるが、基準分周器をプ
ログラマブル分周器９にする事によつて、バンド
切替入力１６により切替えた場合、バンド切替手
段１１および基準周波数設定手段１０により基準
周波数は各バンドに応じて変更させ得る。同時に
各バンドの局部発振器となる、VCO１，６′−１
とVCO２６′−２をスイツチ１３で切替えまた、
ロウパスフイルタ１，４′−１とロウパスフイル
タ２，４′−２をスイツチ１２で切替える。ロウ
パスフイルタを切替るのは、各基準周波数に応じ
て最良のフイルタを構成できるようにするためで
ある。チヤンネル設定のためのプログラム分周器
５の分周比設定手段８は各バンドによつて当然分
周比を変える。多バンドの切替えるべきチヤンネ
ルスペースがあらかじめ分つている場合は基準分
周器の必要なビツトだけ、プログラマブル分周器
にしてもよい。 DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in accordance with embodiments and with reference to drawings. FIG. 2 is a block diagram of a two-band PLL frequency synthesizer which is an embodiment of the present invention.
1 is a reference oscillator, 9 is a reference programmable frequency divider, 10 is a reference frequency setting means, 11 is a reference frequency switching means when switching bands, 3 is a phase comparator 4'
-1 is a low-pass filter 1, 12 is a low-pass filter changeover switch, 4'-2 is a low-pass filter 2, 5 is a programmer frequency divider, 8 is a frequency division ratio setting means, 6'-1 is a VCO 1, 6' -2 is VCO2,13
is the VCO selector switch, 14 is the output of VCO1, 1
5 is the output of VCO2, and 16 is the band switching input. The operation is the same as the conventional one, but by using the programmable frequency divider 9 as the reference frequency divider, when switching is performed by the band switching input 16, the band switching means 11 and the reference frequency setting means 10 change the reference frequency to each It can be changed depending on the band. VCO1, 6'-1, which simultaneously serves as a local oscillator for each band
and VCO26'-2 with switch 13,
A switch 12 is used to switch between low pass filters 1 and 4'-1 and low pass filters 2 and 4'-2. The purpose of switching the low-pass filter is to configure the best filter according to each reference frequency. The frequency division ratio setting means 8 of the program frequency divider 5 for channel setting naturally changes the frequency division ratio depending on each band. If the channel space to be switched for multiple bands is divided in advance, only the necessary bits of the reference frequency divider may be made into a programmable frequency divider.
以上の説明から明らかなように、本発明によれ
ば分周比セツト可能なプログラマブル分周器を用
いているので、簡単な構成の多重バンドフエーズ
ロツクドループ周波数シンセサイザを得ることが
できる。また、バンドに応じて基準周波数を切り
替えているので、基準周波数成分のスプリアスも
十分とれ、ロツクアツプタイムが増加することが
できる。更に、バンドに応じてローパスフイルタ
も切り換えているので、最適なフイルター時定数
を選択でき、ロツクアツプタイムがこの点でも増
加することがなく、電圧制御発振器の出力が歪む
こともない。 As is clear from the above description, according to the present invention, since a programmable frequency divider in which the division ratio can be set is used, a multi-band phase locked loop frequency synthesizer with a simple configuration can be obtained. Furthermore, since the reference frequency is switched according to the band, spurious noise of the reference frequency component can be sufficiently removed, and the lockup time can be increased. Furthermore, since the low-pass filter is also switched according to the band, the optimum filter time constant can be selected, the lockup time will not increase in this respect, and the output of the voltage controlled oscillator will not be distorted.
第１図は従来のPLL周波数シンセサイザのブロ
ツク図、第２図は本発明の一実施例である、２バ
ンドPLL周波数シンセサイザのブロツク図であ
る。
１……基準発振器、２……基準分周器、３……
位相比較器、４，４′−１，４′−２……ロウパス
フイルタ、５……プログラマブル分周器、６，
６′−１，６′−２……VCO、７……VCO出力、
８……プログラマ分周器の分周比設定手段、９…
…基準プログラマブル分周器、１０……基準周波
数設定手段、１１……バンド切替時の基準周波数
切替手段、１２……ロウパスフイルタ切替スイツ
チ、１３……VCO切替スイツチ、１４，１５…
…VCO出力、１６……バンド切替入力。
FIG. 1 is a block diagram of a conventional PLL frequency synthesizer, and FIG. 2 is a block diagram of a two-band PLL frequency synthesizer, which is an embodiment of the present invention. 1...Reference oscillator, 2...Reference frequency divider, 3...
Phase comparator, 4, 4'-1, 4'-2...Low pass filter, 5...Programmable frequency divider, 6,
6'-1, 6'-2...VCO, 7...VCO output,
8... Frequency division ratio setting means for programmer frequency divider, 9...
... Reference programmable frequency divider, 10 ... Reference frequency setting means, 11 ... Reference frequency switching means when switching bands, 12 ... Low pass filter changeover switch, 13 ... VCO changeover switch, 14, 15 ...
...VCO output, 16...Band switching input.
Claims (1)
他のバンドを受信するためのバンド切換信号を受
ける端子と、この端子に結合され前記バンド切換
信号に応答して複数の受信バンドのそれぞれに対
応した異なる周波数の基準周波数信号の中から受
信すべきバンドに対応する基準周波数信号を発生
する手段と、分周比を可変できる分周器であつて
設定された分周比で供給された信号を分周する一
つの分周器と、複数の受信バンド毎に設けられた
電圧制御発振器の中から前記受信すべきバンドの
ための電圧制御発振器を選択しその発振出力を前
記分周器に供給する手段と、前記分周器の出力と
前記基準周波数信号を発生する手段からの基準周
波数信号とを位相比較する一つの位相比較器と、
この位相比較器の出力に応答して各電圧制御発振
器の発振周波数をそれぞれ制御する手段とを備え
る多重バンドフエーズロツクドループ周波数シン
セサイザ。1 A terminal for receiving a band switching signal for switching from the band being received to another band and receiving the other band, and a terminal coupled to this terminal and corresponding to each of the plurality of receiving bands in response to the band switching signal. means for generating a reference frequency signal corresponding to a band to be received from among reference frequency signals of different frequencies, and a frequency divider with a variable frequency division ratio to generate a signal supplied at a set frequency division ratio. One frequency divider that divides the frequency, and a voltage controlled oscillator for the band to be received is selected from voltage controlled oscillators provided for each of a plurality of reception bands, and its oscillation output is supplied to the frequency divider. a phase comparator for phase comparing the output of the frequency divider and the reference frequency signal from the means for generating the reference frequency signal;
and means for controlling the oscillation frequency of each voltage controlled oscillator in response to the output of the phase comparator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12278877A JPS5455351A (en) | 1977-10-12 | 1977-10-12 | Multiband phase locked loop frequency synthesizer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12278877A JPS5455351A (en) | 1977-10-12 | 1977-10-12 | Multiband phase locked loop frequency synthesizer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5455351A JPS5455351A (en) | 1979-05-02 |
| JPS6237569B2 true JPS6237569B2 (en) | 1987-08-13 |
Family
ID=14844627
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12278877A Granted JPS5455351A (en) | 1977-10-12 | 1977-10-12 | Multiband phase locked loop frequency synthesizer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5455351A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58207734A (en) * | 1982-05-28 | 1983-12-03 | Matsushita Electric Ind Co Ltd | Receiver |
| US4559505A (en) * | 1983-01-04 | 1985-12-17 | Motorola, Inc. | Frequency synthesizer with improved priority channel switching |
| JPS6098949U (en) * | 1984-10-08 | 1985-07-05 | 日本電気株式会社 | Digital tuning system |
-
1977
- 1977-10-12 JP JP12278877A patent/JPS5455351A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5455351A (en) | 1979-05-02 |
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