JPS6232668B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a packet branching system that accommodates a plurality of terminals, selects packets from the plurality of terminals, and transmits the packets from the terminals to one line (for example, a subscriber line). The present invention relates to an insertion device.

In a system whose purpose is to communicate with a packet switching network or a packet terminal using a packet terminal, for example, when adding one line to the packet terminal, it is necessary to either add one more line to the packet switching network, or Alternatively, it is necessary to install a packet multiplexing device with a function of multiplexing packets from the already installed packet terminals and packets from the packet terminal to be added between the packet switching network and the packet switching network.

However, in the former case, the cost of installing new lines is enormous. In the latter case, equipment that performs packet multiplexing will be introduced, but the data link between the packet switching network and the equipment will require not only frame-level processing according to high-level data link control (HDLC) procedures. Processing of the packet level interface in accordance with CCITT Recommendation X25 is required in the data link between existing packet terminals and newly installed packet terminals and the communication partner packet terminal connected to the packet switching network. In addition, packet multiplexing equipment achieves economic efficiency by accommodating a large number of packet terminals, and even small-scale equipment achieves economic effects by accommodating 16 to 64 terminals. It is economically disadvantageous to use only 2 or 3 terminals.

Furthermore, when setting a line for priority processing, the former method requires the addition of a new function to the packet switching network, while the latter method requires the addition of a priority processing function to the packet multiplexer in addition to the above. In either case, there are disadvantages in addition to the above-mentioned matters.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the drawbacks of the prior art described above, to provide an economical packet add/drop device that can be easily added by several terminals. Furthermore, it is an object of the present invention to provide a packet add/drop device that can arbitrarily set which terminals should be given priority processing for packets.

In order to achieve the above object, the present invention provides a plurality of packets that are provided for each of a plurality of terminals, detect the reception of packets transmitted from the corresponding terminal, accumulate the packets on a first-come, first-served basis, and output the packets on a first-come, first-served basis. The storage means determines whether or not the number of packets stored in a specific packet storage means among the plurality of packet storage means is greater than a preset number, and If packets are accumulated,
a control means for outputting a control signal instructing to output the packets stored in the specific packet storage means with priority over other packet storage means; A packet add/drop device is provided which is provided with a selection means for selecting a packet and sending it to a subsequent line.

Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a block diagram showing an example of a packet add/drop device according to the present invention, in which 1 is a packet add/drop device, 21 to 2n are n terminals, 31 to
3n is a packet storage unit installed corresponding to the terminals 21 to 2n, 4 is a control unit, 5 is a selection unit, 61 to 6
n is a data line that transmits packets from the terminals 21 to 2n, 7 is an uplink from the packet drop/add device 1 to the packet switching network (not shown), and 8 is a down line from the packet switch network to the packet add/drop device 1. , 91-9n indicate data lines for transmitting packets to the terminals 21-2n.

In the figure, packets sent from terminals 21 to 2n are stored in corresponding packet storage units 31 to 3n, respectively.
The reception is detected and stored on a first-come, first-served basis.
The control unit 4 monitors the number of packets stored in each packet storage unit 31 to 3n, and determines which packet storage unit to output the packets stored in, depending on the storage state of each packet storage unit 31 to 3n. The determination is made according to preset priorities, etc., and instructions are given to the packet storage units 31 to 3n and the selection unit 5. In the designated packet storage unit (for example, 31),
The stored packets are output on a first-come, first-served basis, and the output packets are selected by the selection unit 5 and transmitted to the packet switching network via the uplink 7.
During this time, the outputs from the other packet storage units 32 to 3n are suppressed, and selection by the selection unit 5 is prohibited.

On the other hand, packets arriving from the packet switching network via the downlink 8 are branched within the selection section 5 and sent to each of the terminals 21 to 2n simultaneously. Then, each of the terminals 21 to 2n selects a packet addressed to it.

Next, FIGS. 2, 3, and 4 show an embodiment of the packet add/drop device according to the present invention in which one terminal for priority processing and one terminal for non-priority processing are accommodated. I will explain using Since the gist of the present invention lies in the packet transmission side, only that part will be shown here.

In FIG. 2, parts corresponding to those in FIG. 1 are given the same reference numerals. 3A and 3B are data lines 6A and 6 from corresponding terminals 2A and 2B (not shown), respectively.
31A and 31B are packet storage units that accumulate packets sent through B, and 31A and 31B accumulate packets on a first-come, first-served basis and notify the control unit 4 of the storage status, and also store packets on a first-come, first-served basis according to instructions from the control unit 4. The output first-in/first-out buffers (FI FO) 32A and 32B are packet transmission completion detection circuits that monitor the output signals of 31A and 31B, detect that one packet has been output, and notify the control unit 4. , 33A, 33B are packet reception notification circuits that detect the completion of reception of packets from the data lines 6A, 6B and notify the controller 4 of the completion. 41A and 41B in the control unit 4 are 31A and 32A; an interface circuit that receives and holds notification signals from 33A or notification signals from 31B, 32B, and 33B;
42A, 42B are FIFO reading circuits that generate read signals for outputting the packets stored in 31A, 32B, and 43 is an interface circuit 41A, 4 under the control of a built-in program.
This is a microcomputer that reads the signal held in 1B and controls the FIFO reading circuits 42A and 42B as well as the selection section 5. 51A and 51B in the selection section 5 are AND gates that select the output signals from the corresponding packet storage sections 3A and 3B according to the signal from the control section 4, and 52 is a logical sum of the AND gates 51A and 51B, It is an OR gate that outputs to

Below, the microcomputer 4 in FIG.
The operation shown in FIG. 2 will be explained using FIG. 3 showing the memory requirement table in 3 and FIG. 4 showing the process flow. In Fig. 3, SNA is the number of packets stored in the first-in/first-out buffer (FIFO) 31A;
SNB is a table that stores the number of packets stored in FIFO 31B, FLG is a flag indicating whether or not the output of packets stored in FIFO 31A is prioritized, and CN is a flag that indicates when priority processing is started. A table that stores the accumulated number (constant number),
TA is a table indicating whether or not a packet is being outputted from 31A, and TB is a table indicating whether or not a packet is being outputted from 31B.

Now, from the terminal 2A (not shown) to the data line 6
When a packet is sent out via A, the packet is detected by the packet reception notification circuit 33A,
A reception completion signal a is notified to the interface circuit 41A. The microcomputer 43 reads the signal a held in 41A according to the flow shown in FIG. Then, signal a is “1”
(indicates that there is a signal), assuming that one packet has been accumulated in FIFO 31A, add "1" to the value of table SNA indicating the number of accumulations in FIFO 31A, and calculate the value of table SNA and a predetermined constant number. Compare with the value of table CN that stores . As a result of the comparison, if (SNA)≧(CN), “1” is set in table FLG indicating a state where priority is given to outputting the packets stored in 31A, and (SNA)<
(CN), set “O”.

Next, it is determined whether one or more packets are stored in FIFO 31A by reading signal b. If signal b is "1" indicating that one or more packets are stored, data is first stored in FIFO 31A. Table showing whether it is “1” while outputting a packet
Judgment will be made based on the content of the TA. If a packet is being output from 31A, so that that state continues.
Jump. If not outputting, FIFO
Whether the packet is being output from 31B is "1" or not based on the contents of table TB. If neither of them is being output, "1" is set in the table TA, and the signal g is set to "1" in the on state. As a result, a read signal is generated from the FIFO reading circuit 42A and the packet stored in the FIFO 31A is output, and the AND gate 51A is opened by the signal g, and the packet is transferred to the line 7.
sent to.

The packets output from the FIFO 31A are monitored by the packet transmission completion detection circuit 32A, and when one packet is output, the signal C is set to "1" and is notified to the interface circuit 41A. With C=1, the microcomputer 43 sets "O" in the table TA indicating the end of transmission, and writes the table.
Subtract “1” from the SNA value. If the number of packets (SNA) stored in the FIFO 31A is still greater than a certain number (CN) even after transmitting one packet, an instruction is given to output the packets stored in the FIFO 31A with priority.

On the other hand, from the terminal 2B (not shown) to the data line 6
When a packet is sent out via B, the packet is detected by the packet reception notification circuit 33B,
The completion of reception is notified to the interface circuit 41B by setting the signal "d" to "1". In the microcomputer 43, this signal (d=1) causes the FIFO
The value of table SNB indicating the accumulated number of 31B is “1”
Add. Next, when one or more packets are accumulated in the FIFO 31B, the signal e becomes "1". The microcomputer 43 first checks the contents of the table FLG with e=1, and if FLG is "1", it continues the processing on the FIFO 31A side. If FLG is "O", check the contents of tables TA and TB. Then, if both FIFOs 31A and 31B are not outputting, the table TB is set to "1" so that the packets stored in FIFO 31B are output, and the signal g is turned off to "O". As a result, a read signal is generated from the FIFO reading circuit 42B, and the packet stored in the FIFO 31B is outputted, and the AND gate 51B is opened by the signal g, and the packet is sent out to the line 7.

The packets output from the FIFO 31B are monitored by the packet transmission completion detection circuit 32B, and when one packet is output, the signal f is set to "1" and is notified to the interface circuit 41B. The microcomputer 43 sets "O" in the table TB with f=1 and reads "1" from the value in the table SNB.
decrease.

The above operations are repeatedly executed, including error detection and processing, as shown in FIG.

In this way, a certain number (CN) is stored in FIFO31A.
If the above packets have been accumulated, the packet of 31A will be processed preferentially, and this priority processing will be given to the packet of 31A.
This continues until the number of packets stored in A becomes less than a certain number (CN). If the number is less than a certain number, the packets stored in 31A and 31B are alternately selected and output on a first-come, first-served basis or in scanning order. In addition, in the above explanation, terminal 2
Although the case where priority processing is given to the A side has been described, it is also possible to give priority processing to the terminal 2B side by changing the built-in program. Also, FIFO31
It is also possible to set a fixed number (CNA, CNB) corresponding to A and 31B, and change the priority processing by comparing the number of packets stored in each with the corresponding fixed number (CNA, CNB). It is. Furthermore, 3
It is clear that the same processing can be performed even when the above terminals are accommodated.

As mentioned above, when adding a new terminal to the current system, it is necessary to install a new line or install a packet multiplexing device that performs packet multiplexing, which increases the equipment cost for installing the line and the introduction of the packet multiplexing device. Although the cost cannot be ignored, according to the present invention, it is only necessary to prepare a simple logic for inserting and transmitting to a single line by selecting multiple packet accommodation lines, and complex transmission control can be performed using the latest semiconductors. Advances in technology have made it possible to realize this with more than a dozen large-scale integrated circuits (LSIs). Therefore,
If the device of the present invention is introduced when a new terminal is added, the cost will be low.

Further, the distinction between priority and non-priority can be set arbitrarily, and when the distinction is not particularly required, it can be made possible by changing a fixed number of values, and has various effects.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a packet add/drop device according to the present invention, FIG. 2 is a block diagram showing an embodiment of the present invention, FIG. 3 is a diagram showing a memory table in a microcomputer, and FIG. FIG. 4 is a flowchart showing the flow of processing by the microcomputer. 1: Packet add/drop device, 21-2n: Terminal, 31-3n, 3A, 3B: Packet storage section,
4: Control section, 5: Selection section, 61-6n, 91-9
n, 6A, 6B: data line, 7, 8: line, 31
A, 31B: First-in/first-out buffer (FIFO), 32A, 32B: Packet transmission completion detection circuit, 33A, 33B: Packet reception notification circuit, 41A, 41B: Interface circuit, 42A, 42B: FIFO reading circuit, 4
3: Microcomputer, 51A, 51B: AND gate, 52: OR gate.

Claims (1)

[Scope of Claims] 1. A device that accommodates a plurality of terminals, selects packets transmitted from the plurality of terminals, and sends them to a subsequent line, which is provided for each of the plurality of terminals and has a corresponding one. A plurality of packet storage means detect reception of packets transmitted from a terminal, store the packets on a first-come, first-served basis, and output the packets on a first-come, first-served basis; It is determined whether or not the number of packets is greater than a preset number, and if more packets than the preset number are accumulated, the specified packet storage means is given priority over other packet accumulation means. a control means for outputting a control signal instructing the packet storage means to output the packets stored in the packet storage means; and a control means for selecting the packets to be output from the packet storage means instructed by the control signal and transmitting the selected packets to the subsequent line. What is claimed is: 1. A packet add/drop device comprising a selection means for selecting a packet. 2. Each of the plurality of packet accumulation means has a function of detecting completion of reception of packets transmitted from the corresponding terminal, a function of monitoring the number of accumulated packets, and a function of detecting completion of transmission of output packets. 2. The packet add/drop device according to claim 1, further comprising a function of notifying the control means of these detection results and monitoring results.