JP2563821B2 - Packet transmitter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is used for packet communication. In particular, the present invention relates to a packet transmission device that sends out packets having different communication quality requirements to a communication line.

[Conventional technology]

A packet transmission device is used to send a packet supplied from a terminal device to a communication line. A conventional packet transmission device stores packets to be transmitted as a transmission matrix in a FIFO memory, extracts the packets in order of arrival from the memory, and transfers the packets to a communication line.

[Problems to be Solved by the Invention] However, in the conventional packet transmission device, since all the packets are treated equally, there arises a problem in the case of transmitting a packet having a different delay time request or a different discard rate request. In such a case, in the conventional device, both of the strictest values are satisfied at the same time, so it is necessary to suppress the packet traffic of the transmission queue and the communication line to a low value.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above problems and to provide a packet transmission device that processes packets with different delay time and discard rate requirements without limiting the packet traffic of the transmission queue and communication lines. .

[Means for solving problems]

The packet transmission device of the present invention has a means for outputting to a transmission matrix circuit a packet of a small delay class having a strict requirement for a delay time prior to a packet of a small loss class having a strict requirement for a packet discard rate, and a small loss. When the waiting time of a packet of a class exceeds a predetermined time T1, a method of outputting the packet with priority over a packet of a small delay class, and a waiting time T2 of a packet of a small delay class And a means for discarding the packet when the number of packets exceeds.

[Work]

The packet transmission device of the present invention normally preferentially sends a packet of a small delay class to a communication line. Therefore, it is possible to satisfy the strict requirement regarding packet delay.

At this time, if the memory capacity is sufficient, the small loss class packet will not be lost. However, if the packets of the small delay class are always transmitted with priority, the packets of the small loss class are retained in the memory, and the probability of overflow increases. Further, although the demand for the delay of the small loss class packet is not so severe, it does not mean that the packet may be delayed by any amount. Therefore, when a certain period of time has elapsed, the packet of the small loss class is preferentially transmitted.

Furthermore, since the packet of the small delay class cannot be transmitted because the packet of the small loss class is prioritized, and the delay amount exceeds the allowable range, the packet is discarded.

〔Example〕

FIG. 1 is a block diagram of a packet transmission device according to an embodiment of the present invention.

This packet transmission device includes a transmission matrix circuit 100 that controls the transmission order of packets, and a transmission circuit 200 that extracts packets from the transmission matrix circuit 100 and transfers them to a communication line.

FIG. 2 is a block diagram showing details of the transmission matrix circuit 100.

The packet input to the transmission matrix circuit 100 includes a time stamp circuit 110, a header interpretation circuit 120, and a writing circuit 13.
It is output to the transmission circuit 200 via 0, the memory circuit 140, and the read circuit 150. The output of the header interpretation circuit 120 is supplied to the matrix control circuit 170, which controls the write circuit 130 and the read circuit 150. The time stamp circuit 110 and the matrix control circuit 170 include a clock circuit 16
The clock signal from 0 is supplied.

When a packet to be transmitted to the communication line arrives at the transmission matrix circuit 100, the time stamp circuit 110 adds a header field to the packet and records the arrival time of the packet therein. The time information is supplied from the clock circuit 160.

The header interpretation circuit 120 determines a packet having a strict requirement for delay time and a packet having a strict requirement for packet discard rate, and classifies each of them into a small delay class and a small loss class. As a determination method, a class indication is added to the header on the packet generation source side, and the indication is read by the header interpretation circuit 120. It is also possible to identify the class by reading the logical channel number from the header and searching the class discrimination table in the header interpretation circuit 120 based on this. In this case, the contents of the class discrimination table are set during the call connection process.

Further, the header interpretation circuit 120 writes the arrival packet to the memory circuit 140 via the writing circuit 130, and outputs the arrival signal a including the class type and the arrival time of the packet to the matrix control circuit 170.

 The memory circuit 140 includes a FIFO memory for each class.

The matrix control circuit 170 controls the reading of the memory circuit 140, and outputs the packets of the small delay class having a strict demand for the delay time prior to the packets of the small loss class having a strict demand for the packet discard rate. And when the waiting time of a packet of the small loss class exceeds a predetermined time T1, a means for outputting the packet with priority over the packet of the small delay class and a waiting time of the packet of the small delay class. And means for discarding the packet when the predetermined time T2 is exceeded.

FIG. 3 is a block diagram showing the details of the matrix control circuit 170.

Header interpretation circuit 120, writing circuit 130 and reading circuit
150 is an address calculation circuit 17 via a sequencer circuit 171.
Connected to 2. The address calculation circuit 172 is connected to the control memory circuit 173, the residence time determination circuit 174, and the timer circuit 175.

The sequencer circuit 171 receives the arrival signal a from the header interpretation circuit 120, performs competition control with a signal coming from another circuit, then converts it into a memory request signal b, and outputs it to the address operation circuit 172. The memory request signal b includes information on the class type and the arrival time.

The address calculation circuit 172 is a circuit that controls loading and unloading of the transmission matrix stored in the memory circuit 140, and stores the storage address of each packet, the arrival time, and the address of the empty area in the memory circuit 140 as a control memory circuit 173.
Stored in. When the address arithmetic circuit 172 receives the memory request signal b from the see sensor circuit 171, the storage address in the memory circuit 140 for the arrived packet is calculated based on the content of the control memory circuit 173, and the address signal c And the contents of the control memory circuit 173 are changed.

Upon receiving the address signal c, the sequencer circuit 171 outputs the write command d to the write circuit 130. According to this write command d, the write circuit 130 stores the arrival packet at the specified address of the memory circuit 140.

Reading of packets from the memory circuit 140 to the transmitting circuit 200 or discarding of packets is performed independently of writing. When the reading or discarding of one packet is completed, the reading circuit 150 sends the processing completion signal e to the sequencer circuit 171.

Upon receiving the processing completion signal e, the sequencer circuit 171 outputs a packet transmission request signal f to the address arithmetic circuit 172 after performing competition control with signals from other circuits. When the address calculation circuit 172 receives the packet transmission request signal f, the address delay circuit 172 detects the small delay class and the small lost class.
The determination request signal g is output to the retention time determination circuit 174 to determine the respective waiting times for the first packet of the FIFO memory.

The dwell time determination circuit 174 calculates the queued dwell time of the packet from the time information in the determination request signal g and the current time acquired from the timer circuit 175. Further, the dwell time determination circuit 174 determines whether the waiting time of the packet of the small loss class exceeds the predetermined time T1 and whether the waiting time of the small delay class exceeds the predetermined time T2. Based on this result, whether or not the packet is exceeded, and if so, which class of packet (both may be exceeded) is returned to the address operation circuit 172 as a result signal h.

When the waiting time of the leading packet of both the small loss class and the small delay class is less than or equal to time T1 and T2, respectively, according to the result signal h
For the first packet of the small delay class, the storage address is set in the packet transmission instruction i. If the waiting time of the first packet of the small delay class exceeds the time T2, the storage address of the packet is set to the packet discard instruction j. When the waiting time of the first packet of the small loss class exceeds the time T1, the storage address of the packet is set to the packet transmission instruction i, and the first packet of both the small loss class and the small delay class is set. If the waiting time of each exceeds the time T1 or T2, the storage address of the packet of the small loss class is set in the packet transmission instruction i, and then the storage address of the packet of the small delay class is discarded. The instruction j is set, and these instructions are sent to the sequencer circuit 171.

The sequencer circuit 171 outputs the read command k or the discard command l to the read circuit 150 based on the packet transmission instruction i or the packet discard instruction j.

The read circuit 150 reads the packet from the storage address designated by these instructions, performs output processing to the transmission circuit 200 or discard processing, and then returns the processing completion signal e to the sequencer circuit 171.

The control flow of the above matrix control circuit is shown in FIG.
Shown in the figure. FIG. 4 shows control of packet writing, and FIG.
The figure shows the control of read packet decision.

〔The invention's effect〕

As described above, the packet transmission device of the present invention is
Normally, the packets of the small delay class are preferentially sent out, so that the strict requirements regarding the delay of these packets can be satisfied. Further, when a packet of a small loss class stays in the transmission queue for a long time, the packet is preferentially transmitted to prevent packet loss due to overflow of the memory circuit.

Therefore, the packet transmission device of the present invention can process packets having different delay time requirements and drop rate requirements without limiting the packet traffic, and can effectively spread the range of packet communication. is there.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a packet transmission device according to an embodiment of the present invention. FIG. 2 is a block diagram showing the details of the transmission matrix circuit. FIG. 3 is a block diagram showing the details of the matrix control circuit. FIG. 4 is a diagram showing a flow of packet writing control of the matrix control circuit. FIG. 5 is a diagram showing a control flow for determining a read packet of the matrix control circuit. 100: Sending matrix circuit, 110: Time stamp circuit, 12
0 ... Header interpreting circuit, 130 ... Writing circuit, 140 ... Memory circuit, 150 ... Read circuit, 160 ... Clock circuit,
170 ... Matrix control circuit, 171 ... Sequencer circuit, 172 ...
… Address arithmetic circuit, 173 …… Control memory circuit, 174 ……
Residence time determination circuit, 175 ... Timer circuit, 200 ... Transmission circuit.

Claims (1)

(57) [Claims] 1. A transmission matrix circuit for controlling the transmission order of packets, and a transmission circuit for extracting packets from the transmission matrix circuit and transferring them to a communication line. The transmission matrix circuit has a strict requirement for delay time. In a packet transmission device including means for outputting a packet of a small delay class in preference to a packet of a small loss class having a strict requirement for a packet discard rate, the transmission matrix circuit further includes When the predetermined time T1 is exceeded, the packet is output with priority over the small delay class packet, and when the waiting time of the small delay class packet exceeds the predetermined time T2. And a means for discarding the packet.