JPS62264744A - Frame synchronizing circuit - Google Patents

Abstract

PURPOSE:To detect accurately a synchronizing signal by judging whether or not both the 1st and 2nd synchronizing patterns inserted to the tip and the final part of a burst data coexist. CONSTITUTION:In detecting the 1st synchronizing pattern, a synchronizing pattern detection circuit 23 outputs a synchronizing detection pulse SDP. After a prescribed time from the said SDP output, a gate generating circuit 25 outputs the 2nd synchronizing pattern detection gate signal GP1. When the 1st and 2nd synchronizing patterns are both detected, the 1st counter 41 is advanced stepwise and outputs a pulse when the value reaches a prescribed value. In receiving the pulse, the frame control circuit 27 judges it as the establishment of synchronization. On the other hand, when either the 1st or the 2nd pattern is not detected, the 2nd counter 43 is advanced and outputs a pulse when the value reaches a prescribed value. In receiving the said pulse, the frame control circuit 27 commands the re-pull in of the frame synchronization.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention relates to a frame synchronization circuit that detects synchronization of burst data in, for example, a time division multiple access optical network system, and particularly to a frame synchronization circuit that detects synchronization of burst data in an optical network system using a time division multiple access method, and in particular, a frame synchronization circuit that detects synchronization of burst data in an optical network system using a time division multiple access method. Concerning what to prevent.

[Prior art] Figure 5 shows, for example, the rPCM communication technology published by Sanpo Publishing.
This figure shows the configuration of the conventional frame synchronization circuit shown in 5-4 Frame Domei, written by Okimo Kaneko.

In the figure, first, (1> indicates the received burst data RxD from one parent station. This burst data RxD
A synchronization pattern is inserted at the beginning of the .

(2) is a synchronization pattern detection circuit, and the data RXQ
Detect synchronization patterns inserted into the .

(3) shows a gate circuit for synchronization pattern detection.

(4) shows a gate signal @GP that limits the permissible range of synchronization pattern detection.

(5) shows the gate signal WGP which is heard in the hump ink state and is closed as soon as the detection of the synchronization pattern takes place.

(6) shows a synchronization pattern detection pulse SOP that is output when a synchronization pattern is detected.

(7) shows a frame control circuit.

(8) indicates frame pulse FP.

(9) and (10) are the gate circuit G1. G2 is shown respectively.

(11) is synchronous pulse Sp, <12> is asynchronous pulse A
SP is shown respectively.

(13> and ('14) each indicate a counter circuit.

One counter circuit (13>) is incremented by the synchronous pulse SP and reset by the asynchronous pulse ASP.

The other counter circuit (14) is incremented by the asynchronous pulse ASP and reset by the synchronous pulse SP.

(15) is a pulse SSP indicating the frame synchronization establishment state, which is output when the counter content of the counter circuit (13) exceeds the backward protection threshold value.

(16) is a pulse for commanding resynchronization pull-in, which is output when the count content of the counter circuit (14) exceeds the forward protection threshold.

A control pulse CP (17) is sent out from the frame control circuit (7>) and controls the gate generation circuit (13).

FIG. 6 is a timing chart showing the frame synchronization pull-in process from the hump ink state to the synchronization established state in the frame synchronization circuit of FIG.

In the figure, (18>) indicates a step pulse of the counter circuit (14).

(19> indicates the forward protection threshold.

(20) shows the step pulse of the counter circuit (13).

(21) indicates the rearward protection threshold.

Note that one frame has a configuration in which a plurality of burst data from a plurality of slave stations are multiplexed by time division, with burst data from a master station into which a synchronization pattern has been inserted at the beginning.

Next, the operation will be explained with reference to FIGS. 5 and 6.

Burst signals are transmitted at frame intervals and received by each station.
The data RXD is input to the synchronization pattern detection circuit (2) and matched with the synchronization pattern within the gate signal WGP.

The synchronization pattern detection circuit (2) issues a synchronization pattern detection SDP when a periodic pattern is detected in the received burst data RXD of <1-j-2) frames. This synchronization pattern detection pulse SDR is applied to the frame control circuit (7).
), gate generation circuit (3), gate circuit G1. Sent to G2.

The frame control circuit (7) controls the frame period of the frame period.
a frame counter that sends out a pulse FP (8);
It consists of a circuit that monitors the frame synchronization state and sends a control pulse CP to the gate generation circuit (3). The frame counter is provided with a frame reference by a synchronization pattern detection pulse SDP.

The gate generation circuit (3) is a circuit that controls the transmission of gate signals GP and WGP, and once the synchronization pattern detection pulse SDP is output, the gate signal RWG is immediately closed. From the next frame onward, the gate signal AGP for limiting the detection position is output to the position where the synchronization pattern detection pulse SDR is detected.

Received burst data RX of next frame (i-j-1>
D is input to the synchronization pattern detection circuit (2), and pattern matching is performed within the gate signal @GP.

Here, if the detection in the previous frame is an erroneous detection, no synchronization pattern is detected in the gate signal GP, and in this case, the asynchronous pulse ASP is sent from the gate circuit G2.
is output, the asynchronous pulse counter circuit (14) is incremented, and the synchronous pulse counter circuit (13) is reset.

If a synchronization pattern is not detected for (i-1) consecutive frames after the current frame, the asynchronous pulse counter circuit (14) is incremented sequentially, and the count content becomes forward protection threshold j (19 ) (at the time of receiving burst data RxD of (i-2>frame) in FIG. 5).

When the asynchronous pulse counter (14) exceeds the forward protection threshold (19), the asynchronous pulse counter (14) sends NSP to the frame control circuit (7>).
) outputs a control pulse CP to the gate generation circuit (3) to instruct the gate generation circuit (3) to send out the gate signal RW GF. This causes a transition to a frame synchronization re-entrainment state.

In the above state, when the synchronization pattern detection of the received burst data RXD of frame (i-1) is performed and the synchronization pattern detection pulse SDP is output, as described above, the frame reference signal is sent to the frame control circuit (7). Award, gate credit @
GP settings are made.

(j>When a synchronization pattern is detected in the gate signal @GP from RXD of the frame (i in FIG. 5), the synchronization pattern detection circuit (2) transmits the synchronization pattern detection signal SDP of the frame period to the gate circuit G1. ° Send to G2.

The synchronization pattern detection signal @SDP is ANDed with a frame pulse having a frame period in the gate circuit G1. As a result, the gate circuit G1 outputs the synchronization pulse SP.

The synchronous pulse counter circuit (13) is incremented in response to the synchronous pulse SP, and conversely, the asynchronous pulse counter circuit (13) is incremented in response to the synchronous pulse SP.
14) is reset by its asynchronous pulse SP.

From this point on, when the synchronization pattern detection signal SDR is output continuously for (k-1>frames), the synchronization pulse SP is sequentially output, which causes the synchronization pulse counter circuit (13)
are sequentially incremented until the count reaches the backward protection threshold value k(21>).

The synchronization pulse counter circuit (13) sends the SSP to the frame control circuit when its count exceeds the backward protection threshold k (21>).

Due to this SSP, the frame control circuit (7) determines that frame synchronization has been established and is in a stable state, increases the forward protection threshold k (19) by t to j+t, and from the above state, detects hunting due to bit errors, etc. Create a state that prevents the transition to the state.

[Problems to be Solved by the Invention] However, in systems where the same pattern is likely to be continuously transmitted, such as industrial process status information, the above information happens to have the same pattern as the frame synchronization pattern, i.e. Often contains pseudo frame synchronization patterns. If such a pseudo frame synchronization pattern is included, the conventional frame synchronization circuit described above has the problem that it may mistake the pseudo frame synchronization pattern for a regular synchronization pattern, resulting in malfunction. .

The present invention was made to solve this problem, and an object of the present invention is to provide a frame synchronization circuit that can prevent malfunctions caused by pseudo frame synchronization patterns that are continuously transmitted.

[Means for Solving the Problems] The frame synchronization circuit according to the present invention is used, for example, in a time division multiple access type optical network that performs burst transmission of N:N stations by one master station and a plurality of slave stations. The master station inserts the first synchronization pattern at the beginning of the burst data, and adds the second synchronization pattern to the end of the burst data, while the above burst data On the receiving side, the first and second
a synchronization pattern detection circuit that detects a synchronization pattern of the first synchronization pattern; a gate generation circuit that generates a gate signal for synchronization pattern detection; a first counter circuit that is incremented only when both the first and second synchronization patterns are detected; and either the first or the second, or both. a second counter circuit that is incremented when the first and second synchronization patterns are not detected; It is determined that frame synchronization is established, and if one or both of the first or second synchronization patterns are not detected for multiple frames consecutively, a pulse output from the second counter circuit is received to determine whether the frame is erroneously synchronized or synchronized. It has a frame control circuit that determines that the frame synchronization is broken and re-enables the frame synchronization.

[Operation] In the frame synchronization circuit according to the present invention, the first . A second synchronization pattern is detected within the predetermined gate signal, and the first synchronization pattern is detected within the predetermined gate signal. It is determined that a regular synchronization pattern has been detected when the second synchronization pattern is also detected. As a result, even if the pseudo frame synchronization pattern in the information signal is detected as the first synchronization bounce, the gate signal for detecting the second synchronization pattern will be at the position where the regular second synchronization pattern is added. Due to the deviation from the second gate signal, the second synchronization pattern cannot be detected within the second gate signal. This makes it possible to determine whether the above detection is a pseudo frame synchronization pattern.

[Embodiments] Preferred embodiments of the present invention will be described below with reference to the drawings.

In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

FIG. 1 shows an embodiment of a frame synchronization circuit according to the present invention.

In Figure 1, (22) is the received burst signal from the master station.
Data RXDT is shown. This burst data RXDT
is sent from the master station, and the first part is at the beginning.
A synchronization pattern is inserted, and a second synchronization pattern is added to the end of the synchronization pattern.

(23> indicates a synchronization pattern detection circuit. This synchronization pattern detection circuit (23)
Detect the DT synchronization pattern.

24) shows a gate signal for detecting the second synchronization pattern.

(25) shows a gate generation circuit. This gate generation circuit (25) outputs gate signals GP, WGP, and GP1.

(26) indicates the synchronization pattern detection pulse 5DP1. This synchronization pattern detection pulse SDP'l is the gate signal G
When the second synchronization pattern is detected by P1,
It is output from the synchronization pattern detection circuit (23).

(27) indicates a frame control circuit.

(28> and (29>) indicate gate circuits G3 and G4, respectively.

(30) indicates the synchronization pulse SP'l. This synchronization pulse SP1 is multiplied by 1q by the AND output of the gate signal QGP1 and the synchronization pattern detection pulse 5DP1.

(31) indicates the asynchronous pulse ASP1. This asynchronous pulse ASP1 is output when the synchronous pattern detection pulse 5DP1 is not generated.

(32), (33), (34), and (35) are gate circuits G5. G6. G7. Shows G8.

(36) shows a set/reset type flip-flop circuit.

(37) is a set/reset type flip-flop circuit (
36) shows the set output ST.

38) shows the frame same gate pulse FSP.

This frame synchronization pulse FSP is output from the gate circuit G5 (33) when both synchronization pattern detection pulses SDP and 5DP1 are generated.

(39) indicates the pseudo synchronization pulse PSP. This pseudo synchronous pulse PSP is output from the gate circuit G7 (34) when the asynchronous pulse ASP1 is generated after the set output ST is significant (active state).

(40) indicates a frame synchronization error pulse FEP. This frame synchronization error pulse FEP is the asynchronous pulse A
It is given by the logical sum of SP and the pseudo synchronization pulse PSP.

(41) indicates a counter circuit. This counter circuit (4
1) is stepped by the frame synchronization pulse FSP and reset by the frame synchronization error pulse FEP.

(42) is a pulse 5SP1 indicating the frame synchronization established state.
It is. This pulse 5SP1 is generated by the counter circuit (41)
is incremented and output when the count reaches the rearward protection threshold.

(43) also shows a counter circuit. This counter circuit (4
3) is incremented by the frame synchronization error pulse FEP (40) and reset by the frame synchronization pulse FSP.

(44) is a pulse N5 that instructs frame synchronization re-intake.
I am a PI. This pulse N5P1 is applied to the counter circuit (4
3) is incremented, and when its content reaches a certain threshold value, it is output and given to the frame control circuit (27).

(45) indicates the reset signal R8. This Rizel ~ Shin@R8 is issued when receiving N5PI and is set.
The reset type flip-flop circuit (36) is reset.

FIG. 2 shows the configuration of received burst data RxD (22>, gate signals GP (4), GPl (24>) and synchronization pattern detection pulse 5DR (6), when the synchronization pattern of received burst data RxD is detected. 5DPI (26
> shows the phase relationship.

In FIG. 2, (45) is a preamble, and all bits are "1".

(47) is the first synchronization pattern, for example, a specific code pattern "11110010" arbitrarily determined in advance.
consists of a bit pattern of

(48) indicates an information signal. This information signal (48) contains actual data.

(49) is the second synchronization pattern. This second synchronization pattern (49) is provided with the same bit pattern as the first synchronization pattern (47).

Within one burst data, each of the above-mentioned signals is time-division multiplexed and inserted at a predetermined fixed position.

FIGS. 3(a) and 3(b) show the frame structure in a system in which the present invention is used, the gate signals GP and GP1, the synchronization pattern detection pulse 5DR(6), and the synchronization pattern detection pulse 5DR(6) when a regular or pseudo synchronization pattern is detected. 5DPI (26>) shows the phase relationship.

In this case, Fig. 3 (a) shows the phase relationship of each signal GPI, GP1.SDP, and 5DP1 when detecting a regular synchronization pattern. Fig. 3 (b) shows the pseudo synchronization pattern, The phase relationship of each signal GP, GP1.SDP, and 5DP1 is shown.

In FIG. 3 (a>, (b)), (50) indicates the card time Qt of the logic level l (OII).
The time Gt is set to separate the burst signals of each station.

Here, one frame is the first frame. Second synchronization pattern (4
7), (49) from the master station starts with RxDT (22), and the burst data of multiple slave stations are multiplexed in a time division manner and inserted into each at a predetermined fixed time position. The configuration is as follows.

FIG. 4 shows a synchronization pull-in process from a frame erroneous synchronization state to a cycle established state when using the frame synchronization circuit according to the present invention.

In FIG. 4, (51) indicates a step pulse of the counter circuit (43).

(52> is the threshold 1 set in the counter circuit (43)
This threshold value (52) is used to judge whether the occurrence of the frame synchronization error pulse FEP (40) is due to a true frame missynchronization or a pre-synchronization of decay. The circuit (43) is set.

(53) indicates a step pulse of the counter circuit (41).

(54) indicates the backward protection threshold set in the counter circuit (41).

The received burst data RXD (22) is input to a synchronization pattern detection circuit (23), where a search for a synchronization pattern, so-called hunting, is first started within the gate signal 8'vV GP.

When a synchronization pattern is detected, the synchronization pattern detection circuit (23) regards this as a first synchronization pattern and outputs a synchronization pattern detection pulse SDR.

The synchronization pattern detection pulse SDP is transmitted by the frame control circuit (2
7) Give a frame reference. Furthermore, the synchronization pattern detection pulse SDP causes the gate generation circuit (25) to reset the gate signal WGP. Also, the gate signal GP for the next frame and subsequent frames is set. Roughly, the second synchronization pattern detection gate signal QGPI is set.

In FIG. 4, when the received burst data RxDT of the next frame (i-j>) is input and the first synchronization pattern is detected again in the gate signal @GP, the synchronization pattern detection pulse SDR of the frame period is output.

Synchronous pattern detection pulse SDP and frame pulse FP
are ANDed in gate circuit G1. As a result, the gate circuit G1 outputs the synchronization pulse SP. This synchronization pulse SP causes the set/reset type flip-flop circuit (36>) to be set and generate a set output ST.

On the other hand, within the gate signal GPi set by the synchronization pattern detection pulse SDP, the second synchronization pattern (49) added to the received burst data Rx DT is
A search is carried out.

If no detection is performed within the gate signal GPI, an asynchronous pulse ASPI is output from the gate circuit G4.

The asynchronous pulse ASP1 is output as a pseudo synchronous pulse PSP when the set output ST of the set/reset type flip-flop circuit (36) is significant.

This asynchronous pulse PSP1 is output when the first synchronization pattern is not detected. It is logically ORed with the asynchronous pulse ASP. Then, this logical sum (ASPI+ASP
> is input to the counter circuits (41) and (43) as a frame synchronization error pulse FEP.

The frame synchronization error pulse FEP (40) resets the counter circuit (41). In addition, the counter circuit <4
Compare 3) step by step.

From now on, the frame synchronization error pulse FEP is (j-1
>Counter circuit (43) that outputs frames continuously
is sequentially incremented, and the increment pulse (count content > (51) of the counter circuit (43) reaches the threshold value (52) of the counter circuit (43). When the value (52) is reached, pulse N5
P1 is given to the frame system 00 circuit (27).

At this time, the frame control circuit (27) determines that the generation of the synchronization pattern detection pulse SDR is due to a pseudo synchronization pattern, and applies a reset pulse R8 to the gate circuit G5 to provide a set/reset type flip-flop circuit (36).
) to the reset state. At the same time, a control pulse CP (17) is sent to the gate generation circuit (25) to instruct it to send out the gate signal WGP.

This causes a transition to the frame synchronization re-retraction state.

As shown in FIG.
When the first synchronization pattern (47) is detected in xDT, and the synchronization pattern is also detected in the gate signal GP in the received burst data RXDT of the subsequent <(j+1> frame), as described above, the synchronization pulse SP is output, and the set output ST of the set/reset type flip-flop circuit (36) becomes a significant signal.

On the other hand, the second gate pattern (49
) is detected, the synchronization pattern detection circuit (23) outputs a synchronization pattern detection pulse 5DR1.

The synchronization pattern detection pulse 5DPI is output as a synchronization pulse from the gate circuit G3, and is logically ANDed with the significantly held set output ST.

This AND output is inputted to counter circuits (41) and (43) as a frame synchronization pulse FSP. This frame synchronization pulse FSP sets the counter circuit (41) to 1
The bit is incremented and the counter circuit (43) is reset.

When the frame synchronization pulse ESP is continuously output for (k-1>frames), the step pulse (53) of the counter circuit (41) reaches the backward protection threshold (54).At this time, the frame control circuit (27) receives the 5SPI and determines that frame synchronization is established.

As described above, the frame synchronization circuit described above uses the first synchronization pattern (
47) and a second synchronization pattern (49) added at a fixed position S bits apart from the insertion position of the first synchronization pattern (47). When performing this synchronization operation, the gate generation circuit (25) on the receiving side has a first synchronization pattern (
47) from the generation point of the detection pulse SDP to the output of the second synchronization pattern detection gate signal GPI
A constant delay approximating the it bit is given.

And 1. Only when the first synchronization pattern detection pulse SDP is generated, the second synchronization pattern detection gate signal GP1 is output after the delay amount t bits, and the first and second synchronization pattern detection (47), (49 ) is detected together, it is considered that true frame synchronization is detected, and at this time, the backward protection counter circuit (41) is incremented, and when it reaches a predetermined threshold value (54), frame synchronization is established for the first time. I judge that.

On the other hand, as shown in FIG. 3(b), when a pseudo synchronization pattern is detected by the first synchronization pattern detection gate signal MGP, the second synchronization pattern, which is output after a fixed delay of 1t bits, is detected by the first synchronization pattern detection gate signal MGP. Gate signal GP1 is at logic level "Oo"
The second synchronization pattern (49) is no longer detected because it becomes significant at the guard time Gt of o or at the beginning of the other station's burst data (preamble of logic level "1'"). Therefore, it is assumed that the above detection is due to a pseudo-synchronization pattern.If this non-detection state continues for several frames in a row, it is determined that the synchronization is erroneous to the pseudo-synchronization pattern, and the synchronization pull-in operation is performed again at this point. .

[Effects of the Invention] As described above, the present invention first detects the first synchronization pattern from the burst data in which the first and second synchronization patterns are predetermined (inserted in an upright position and attached h0),
From this point of detection, the second synchronization pattern is detected at the expected detection position after a predetermined non-delay amount, and if the second synchronization pattern is detected consecutively for multiple frames, normal frame synchronization is established. If either the first or the second is not detected for several frames in a row, it is assumed to be an erroneous synchronization or a synchronization breakdown, and the pull-in operation is performed again. This has the effect of preventing erroneous synchronization due to pseudo-patterns that happen to be fixedly included in the information signal, thereby making it possible to establish stable and reliable frame synchronization.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a diagram showing an embodiment of the frame synchronization circuit according to the present invention, and FIG. 2 is a diagram showing received burst data, gate signals, and synchronization patterns input to the frame synchronization circuit according to the present invention. A diagram showing the phase relationship of detection pulses, Fig. 3 (a>
, (b) is a diagram showing the frame structure of the system used in one embodiment of the present invention and the phase relationship between the gate signal and the synchronization pattern detection signal when a regular or pseudo synchronization pattern is detected. FIG. 5 is a diagram showing the configuration of a conventional frame synchronization circuit using a timing chart, and FIG. 6 is a diagram showing an example of the operation of the conventional frame synchronization circuit using a timing chart. be. In the figure, (22) is the received burst data RXDT
, (23) is a synchronization pattern detection circuit, (24) is a second synchronization pattern detection gate signal, (25) is a gate generation circuit, (27) is a frame control circuit, (41) is a first counter circuit, (43) is the second counter circuit, (47
) is the first synchronization pattern, and (49) is the second synchronization pattern. In addition, in the figures, the same reference numerals are the same or (indicate the relevant parts. Agent: Patent Attorney Masuo Oiwa (and 2 others) Figure 2 47: 1st/l Synchronous Bakun 49° 2nd f) rU Month 1 (q-n Figure 5 procedural amendment (voluntary)

Claims (1)

[Claims] (1) Synchronization pull-in is performed by detecting a synchronization pattern from burst data in which a first synchronization pattern is inserted at the beginning and a second synchronization pattern is added after a certain delay from this first synchronization pattern. In the frame synchronization circuit, a synchronization pattern detection circuit that detects the first and second synchronization patterns; and a synchronization pattern detection circuit that detects the second synchronization pattern after the above-mentioned certain delay from the time of detection when the first synchronization pattern is detected. a gate generation circuit that generates a gate signal; a first counter circuit that is incremented only when both the first and second synchronization patterns are detected; A frame synchronization established state is established in response to a pulse output from the first counter circuit when both the first and second synchronization patterns are detected consecutively for a plurality of frames. When one or both of the first or second synchronization patterns are not detected for a plurality of consecutive frames, a pulse output from the second counter circuit is received to determine frame missync or synchronization loss. 1. A frame synchronization circuit comprising: a frame control circuit for re-engaging frame synchronization.