JP3234758B2 - Burst synchronization circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a burst synchronization circuit used in a communication device for transmitting burst data.

[0002] Conventional signal transmission between communication devices is a continuous signal, and a receiving side extracts a clock from the signal and takes in data. Therefore, it takes time from when the data is input to the receiving circuit to when the correct data is reproduced.

On the other hand, the conventional clock extraction method cannot be applied to burst transmission. Therefore,
It is necessary to provide a burst synchronization circuit that takes in data correctly for each burst.

[0004]

2. Description of the Related Art FIG. 15 is an explanatory view of a burst data transmission system, in which (a) is a configuration diagram of a main part system and (b) is a schematic configuration diagram of burst data.

[0005] In recent years, sophistication of services provided such as multimedia to telephone subscribers has been planned, and the amount of information to be communicated has become enormous with the sophistication of these services. On the other hand, available services are limited because the amount of information to be transmitted is small in the conventional metallic telephone line.

Therefore, it has been proposed to use an optical fiber for the subscriber transmission line. For example, as shown in FIG. 15A, an optical fiber connected to the main station is optically coupled in the middle of the subscriber transmission line.
/ The optical fiber is divided into n branches by a distributor, and the branched optical fibers are connected to slave stations # 1, # 2,.

[0007] For example, from the master station to slave stations # 1 to #n
Burst data # 1a to #na are multiplexed by the TDMA method and transmitted. On the other hand, the slave stations # 1 to #n each have burst data # 1b, # 2 in a predetermined time slot.
b,..., #nb are transmitted, and these burst data are combined by the optical coupler / distributor described above and sent to the master station in a serial format. Therefore, the master station receives data by synchronizing the bit of data for each burst by an internal burst synchronization circuit.

Here, since the lengths of the branch optical fibers connecting the optical coupler / distributor and each slave station are different, the burst data # 1b, # 2b,..., #Nb transmitted by each slave station are transmitted to the master station. The arrival time and the light receiving level are different. For this reason, an automatic gain control section is provided in the receiving apparatus so that the levels are made to match.

As shown in FIG. 15B, the burst data is composed of a preamble portion, a delimiter portion, and a data portion. The preamble portion has a pattern of 1010... But
In this part, the leading two or three bits may be cut off when transmitting or receiving light. In the delimiter part, a pattern indicating the head of the packet data is inserted. By detecting this pattern, the head position of the data can be known.

[0010]

Here, in a communication system for transmitting burst data, optical coupling as described above is performed.
/ Burst data # 1b, # 2 transmitted by each slave station because the length of the branch optical fiber connecting the distributor and each slave station is different
The time for b, ..., #nb to reach the master station differs.

Therefore, the burst data # 1 received by the master station
b, # 2b, ... The bit phase differs for each #nb, and it is difficult for the master station to capture the input burst data # 1b, # 2b, ..., #nb using the internal system clock. There is a problem.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a burst synchronization circuit which correctly takes in data for each burst data.

[0013]

FIG. 1 is a block diagram showing the principle of the present invention, and FIG. 2 is a diagram for explaining the operation of FIG. The first invention is
A plurality of burst data is added to the edge detection means to perform edge detection a plurality of times, and the edges of the detected plurality of burst data are logically ORed. The configuration is such that an optimum phase selection means for transmitting a phase selection signal for selecting a phase corresponding to the center of the interval is provided.

According to a second aspect of the present invention, the optimum phase selecting means includes a latch / OR part for taking a logical sum of the previous and current edge detection outputs of the same clock timing among the plurality of edge detection outputs, A logical product part that takes a logical product of adjacent inverted outputs of the latch / logical sum part is hierarchized. An optimum phase selection section for generating a phase selection signal for selecting the sampling data of the corresponding phase.

According to a third aspect of the present invention, the above-mentioned optimum phase selecting portion is configured to output one or more inverted outputs of the latch / OR portion.
When a change point cannot be detected with a delay width longer than the clock, it is determined that the operation is abnormal.

According to a fourth aspect of the present invention, the optimal phase selecting section is constituted by a logically compressed circuit. According to a fifth aspect of the present invention, the upper optimal phase selecting portion is constituted by a ROM in which optimal phase outputs corresponding to outputs of various latch / OR portions are calculated and stored in advance, and when the latch / OR output is input,
The corresponding optimum phase output is taken out.

Here, the principle of the present invention will be described with reference to FIGS. First, when a plurality of burst data transmitted by the slave station shown in FIG. 15 is input to the burst synchronization circuit shown in FIG. 1 in the master station receiving apparatus, the sampling means 1 samples the burst data with the clock inside the receiving apparatus. To the edge detecting means 2 and the data selecting means 3.

The edge detecting means 2 performs an edge detection by, for example, taking an exclusive OR of adjacent data of the input sampling data and sending out the edge detection result to the optimum phase selecting means. Perform on data.

Here, the timing for taking in data will be considered. Since the portion where the edge detection result is 0 is not an edge, if data is taken in here, data will not be erroneously taken in. Furthermore, if the center of the longest 0 region is set as the data capturing position, the data is not erroneously captured even if the phase of the burst data fluctuates slightly, and the optimum phase position is obtained.

In order to realize this, as shown in FIG. 2, the logical sum of the edge detection results of a plurality of bursts is calculated by the optimum phase selecting means. For example, when the patterns of the first and second burst data are as shown in FIG. 2, the logical OR output of the edge detection result is a pattern as shown in “OR output of edge detection result”. Here, is the edge of the first burst data, and is the edge of the second burst data.

The longest-edge-free area has four consecutive zeros.
Therefore, if the center (point A in the figure) is selected as the optimum phase, the data is taken in the center of the safe area in FIG.

That is, the logical sum of the edges of a plurality of burst data is calculated, and the center of the portion where the interval between adjacent logical sum edges is the largest is selected as the optimum phase. The possibility of is almost eliminated.

[0023]

FIG. 3 is a block diagram of the first and second embodiments of the present invention, FIG. 4 is an example of a block diagram of the sampling means in FIG. 3, FIG. 5 is an operation explanatory diagram of FIG. FIG. 6 is an example of a configuration diagram of the edge detection means and the latch / OR section in FIG.
6 is an explanatory diagram of the operation in FIG. 6, and FIG. 8 is an example of a configuration diagram of a main part of the optimum phase selecting portion in FIG.

FIG. 9 is an explanatory view of claim 3, wherein FIG. 9 (a) is a configuration diagram of a main part of an optimum phase selecting section, and FIG. 9 (b) is an operation explanatory view of FIG.
10 is an example of a configuration diagram of a main part of an optimal phase selection portion before logical compression, FIG. 11 is an explanatory diagram of logical compression (part 1), FIG. 12 is an explanatory diagram of logical compression (part 2), and FIG. FIG. 14 is an example of a main part configuration diagram of the optimum phase selection part after compression, and FIG. 14 is another main part configuration diagram of the optimum phase selection part in FIG.

Here, the same reference numerals indicate the same objects throughout the drawings. The latch / OR section 41 and the optimum phase selection section 42 in FIG. 3 are components of the optimum phase selection means 4. Hereinafter, FIGS. 3 to 14 will be described. In the edge detection, it is assumed that edge detection is performed a plurality of times by using a plurality of rearmost bambles.

First, as shown in FIG. 4, the sampling means 1 in the burst synchronization circuit shown in FIG.
(DL _{1 to} DL ₁₃ ) and flip-flops (FF _{1 to} FF ₁₃ ), but the delay amount of a certain delay line is increased by Δ from the delay amount of the immediately above delay line. (e.g., increase the delay amount of the delay line DL ₂ only Δ than the delay amount of the delay line DL _1), the delay amount toward near the bottom increases.

The output side of each delay line is connected to a separate flip-flop (FF), and the state of the burst data delayed by each delay line is taken into the corresponding flip-flop with the same clock.

[0028] At this time, although the burst data is delayed significantly toward the DL ₁₃ from DL _1, these burst data is taken into the flip-flop (FF) in the state at time t _1.

Therefore, as shown on the right side of FIG.
1 data is sent from these flip-flops to the edge detecting means 2 and the data selecting means 3. On the other hand, FIG.
The edge detection window portion 5 in the middle has a function of transmitting the preamble fetch timing to a necessary portion. In the case of the present invention, the timing of fetching the last plurality of preambles of the preamble is determined by the edge detection means 2 and the latch.・ Send to the OR section 41 and the optimum phase selecting section 42.

Thus, the edge detecting means 2 shown in FIG.
Is the EX-OR of adjacent sampling data
And outputs a 0 or 1 edge detection result.
Indicates an edge, and 0 indicates a portion other than the edge (see FIG. 7).

The edge detecting means is, for example, 12
It consists of EX-OR gates (called the edge detection part). Here, FIG. 7 shows a case where there are two burst data. However, the edge detection means detects an edge detection result of “010000000010” for the first burst data and “0000000” for the second burst data.
The result of the "100001000" edge detection is sent to the latch / OR section 41 in FIG.

The latch / OR section 41 is composed of a plurality of latch / OR functional sections having the same configuration. Since these functional sections have the same configuration and the same function, the operation of one functional section will be described.

As shown in FIG. 6, the latch / OR function part 41-1 includes an OR gate, a flip-flop (FF), an AND
It is composed of gates and is provided corresponding to the 12 edge detection parts.The previous edge detection result held in the internal flip-flop is added to the OR gate via the turned on AND gate. I have.

Therefore, when the corresponding edge detection part sends the current edge detection result to the latch / OR function part 41-1, the OR gate takes the logical sum with the previous edge detection result, and outputs the logical sum output to the latest. The logical sum output is held by a flip-flop (FF) and added to an internal OR gate, and is inverted and sent to the optimum phase selection section 42 ("inverted OR" in FIG. 8).
Output ").

The reason for inverting the logical sum output is to detect the longest 0 region in the optimum phase selection portion.
The flip-flop in the OR section 41 is reset at the beginning of the input preamble.

The optimum phase selection section 42 is a section for selecting the center of the longest interval between adjacent edges obtained by performing a logical OR operation. When all the products have been obtained, the logical product next to the logical product is further obtained, and this operation is repeated until the logical product can no longer be obtained (see FIG. 8).

Now, when the inverted OR output "1010111110101" of the latch / OR unit 41 is input to the optimum phase selection unit 42, the outputs of the first, second, and third-stage AND gate groups are shown in FIG. The middle of the output of the third stage is 1
And the others are 0.

Therefore, the first part of the third stage is sampling data having an optimum phase, which corresponds to the output of FF ₇ (not shown) in FIG. Therefore, a phase selection signal for selecting this output is sent to the data selection means 3. Thus, the seventh burst data is extracted through the data selection portion.

Note that selection is made at each sampling point.
Select the AND gate in advance as shaded. Even layers are not centered, but one is selected so that there is no omission in the corresponding AND gate. And at the highest level, AND
From sampling points where the output of the gate is 1, point A having a small delay amount is selected.

The optimum phase selecting portion has a configuration as shown in FIG. 9A, and four change points correspond to one clock as shown in FIG. 9B. In this case, since a plurality of change points are detected, there is no change point for one clock or more. Therefore, FIG.
If 1 appears on the right side of point B in the middle, the abnormal information is sent out as an optimal phase selection error.

This information is, for example, Y14, Y24, Y3
An abnormal state can be output easily by taking the logical sum of the outputs of 4, Y44 and Y54. Next, a case where logical compression is performed on the optimum phase selection portion having the configuration shown in FIG. 10 will be described. Generally, the logic of the configuration as shown in FIG. 8 is described as follows.

When X (1) to X (n)

[0043]

(Equation 1)

Output of AND

[0045]

(Equation 2)

OR of each layer

[0047]

(Equation 3)

At the time of the highest hierarchy 1

[0049]

(Equation 4)

Top-level selection

[0051]

(Equation 5)

(In the case where the even-numbered layer is configured to select the one with the smaller delay) Selection information at each sampling point

[0053]

(Equation 6)

(X = i1-int ((y + 1) / 2)) (x> = 1 or x + y <= n) (2 <= i1 <= n) optimal selection

[0055]

(Equation 7)

(Selection of the one with less delay) Here, "AND
"Output" indicates that a circuit for finding the center of 1 is constituted by an AND circuit as shown in FIG. "OR of each level"
And “1 at the time of the highest level” OR the output of each level and
It indicates that the level higher is 0 and the own hierarchy is the highest level of 1. "Top-level selection" is the highest level in the hierarchy
The output of D indicates that one sampling point is selected.

"Selection information at each sampling point"
The AND selected at each sampling point is previously selected in a shaded manner as shown in FIG. Even-numbered layers are not centered, but one of them is selected so that there is no omission in the corresponding AND. "Optimal selection" selects the one with a small amount of delay at the sampling point when the output of a plurality of ANDs is 1 in the highest hierarchy.

Now, logical compression is performed on the optimum phase selection portion shown in FIG. Note that the circuit configurations of FIGS.
It has the same circuit configuration as 0, but is added with, for example, YY (1), SEL (2), etc., in order to clearly indicate in which hierarchy the operation result is to be obtained.

First, the OR of each layer, YY (i), is determined.

[0060]

(Equation 8)

The output M (i) in which only the uppermost layer is 1 and the other layers are 0 is obtained, and the output M (i, j) of each AND circuit is ANDed with the output to obtain the uppermost layer. SM (i, j) that outputs only Y (i, j) of

[0062]

(Equation 9)

The optimum selected phase output SLE (2) is obtained. SEL (2)
Is the OR of S (1, 1) and SM (1, 2).

[0064]

(Equation 10)

Similarly, the optimum selected phase output SEL (3) is obtained.

[0066]

[Equation 11]

Similarly, an optimum selected phase output SEL (3) is obtained. If S2 is selected, it cannot be selected.
AND the NOT of S (2) with S (3).

[0068]

(Equation 12)

Similarly, an optimum selected phase output SEL (4) is obtained. If S (2) and S (3) are selected, they cannot be selected.Therefore, NOT of OR (S) of S (2) and S (3) and S (4)
Take AND.

[0070]

(Equation 13)

To summarize this,

[0072]

[Equation 14]

Is obtained. Then, SEL (2), SEL (3), SEL
When the logic of (4) is formed into a circuit, the circuit becomes as shown in FIG. 13. However, since this circuit operates each logic in parallel, it is possible to increase the speed.

FIG. 14 shows a configuration in which the optimum phase detection section is constituted by a ROM. The optimum phase outputs for the outputs of various latch / OR sections are calculated and stored in the ROM in advance. Then, when the latch / OR output is input, the corresponding optimum phase output is extracted.

That is, by performing a logical sum of a plurality of burst data, a large number of edge detections can be performed even on data with little change such as 0110, and errors in phase selection are reduced.

[0076]

As described in detail above, according to the present invention, it is possible to provide a burst synchronization circuit for correctly capturing data for each burst.

[Brief description of the drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is an operation explanatory diagram of FIG. 1;

FIG. 3 is a configuration diagram of the first and second embodiments of the present invention.

FIG. 4 is an example of a configuration diagram of a sampling unit in FIG. 3;

FIG. 5 is an operation explanatory diagram of FIG. 4;

6 is an example of a configuration diagram of an edge detection unit and a latch / OR section in FIG. 3;

FIG. 7 is an operation explanatory diagram of FIG. 6;

FIG. 8 is an example of a configuration diagram of a main part of an optimum phase selection section in FIG. 3;

9A and 9B are explanatory diagrams of claim 3, wherein FIG. 9A is a configuration diagram of a main part of an optimum phase selecting portion, and FIG. 9B is an operation explanatory diagram of FIG.

FIG. 10 is an example of a configuration diagram of a main part of an optimum phase selection portion before logical compression.

FIG. 11 is an explanatory diagram (part 1) of logical compression.

FIG. 12 is an explanatory diagram (part 2) of logical compression.

FIG. 13 is an example of a configuration diagram of a main part of an optimum phase selection section after logical compression.

14 is another main part configuration diagram of the optimum phase selection part in FIG. 3;

FIG. 15 is an explanatory diagram of a burst data transmission system, in which (a)
FIG. 2 is a configuration diagram of a main part system, and FIG. 2B is a schematic configuration diagram of burst data.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Sampling means 2 Edge detection means 3 Data selection means 4 Optimal phase selection means 41 Latch / OR part 42 Optimal phase selection part

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Masaaki Kawai 1015 Uedanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Kazuyuki Tajima 1015 Ueodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited ( 72) Inventor Setsuo Abiru 1015 Uedanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Masago Miyabe 1015 Ueodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (72) Eiji Maekawa Tokyo Metropolitan Government 3-19-2 Nishi-Shinjuku, Shinjuku-ku Nippon Telegraph and Telephone Corporation (56) References JP-A-9-83500 (JP, A) JP-A-6-152583 (JP, A) JP-A-8-331118 (JP, A) JP-A-63-86921 (JP, A) JP-A-61-152140 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 7/02 H03K 5 / 00

Claims (5)

(57) [Claims] 1. A sampling means for delaying input burst data by a set delay amount, sampling with a clock and outputting a plurality of sampled data, and performing a logical operation next to the plurality of sampled data. a burst synchronization circuit comprising: edge detection means for detecting an edge; and data selection means for selecting sampling data corresponding to the input phase selection signal among the plurality of sampling data. In addition to performing multiple edge detections by adding multiple burst data, the OR of the edge detection outputs of the detected multiple burst data is ORed, and the edge interval between adjacent ORs is the longest,
A burst synchronization circuit comprising an optimum phase selection means for transmitting a phase selection signal for selecting a phase with respect to the center of the longest interval. 2. A latch / OR part for obtaining a logical sum of the previous and current edge detection outputs of the same clock timing among the plurality of edge detection outputs, and a latch / OR part. The logical product part which takes the logical product of adjacent ones of a plurality of inverted outputs of is made hierarchical, and the logical product output is 1
Wherein an uppermost layer having an optimum phase selection section for generating a phase selection signal for selecting sampling data having a phase corresponding to one "1" having the least delay amount is provided. Item 1. The burst synchronization circuit according to Item 1. 3. The method according to claim 2, wherein the optimum phase selection section determines that the operation is abnormal when a change point cannot be detected with a delay width of one clock or more for a plurality of inverted outputs of the latch / OR section. 3. The burst synchronization circuit according to claim 2, wherein: Wherein said optimum phase selection part, also claim 2, characterized in that it is constituted by a circuit that is logically compressed
Is a burst synchronization circuit of 3. 5. The optimal phase selecting section is constituted by a ROM in which optimal phase outputs for various latch / OR sections are calculated and stored in advance, and when a latch / OR output is input, a corresponding optimal phase output is obtained. The burst synchronization circuit according to any one of claims 2 to 4, wherein a phase output is taken out.