JPS62248378A - Picture processor capable of designating recording position - Google Patents

Abstract

PURPOSE:To simplify a circuit constitution and a control by extracting only picture information in a reading designating area, applying an enlarging and reducing processing to the extracted picture data and recording the enlarged and reduced picture data in the recording designating position. CONSTITUTION:The picture information such as an original is converted into the picture data of prescribed number of bits in a picture reader 50, the picture processing such as an enlargement and a reduction is performed in a picture processing circuit 2, thereafter, the processing based on a picture recording processing or a recording designation by a central reference is executed in a output buffer circuit 90. The picture data read from the output buffer circuit 90 is supplied to an output device 65, the picture is recorded with an externally set magnification and the picture is recorded at an externally set position. Various input data such as the designation of the magnification or the designation of the recording position is inputted and the contents thereof are displayed in an operation display part 75. As a display means, an element such as an LED is used.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention uses data interpolation to enlarge or reduce an original image, and also provides a recording position that can arbitrarily set the recording position on recording paper. The present invention relates to an image processing device that can be specified.

[Background of the Invention] When a photoelectric conversion element such as a CCD is used as a single image reading means in an image recording device capable of enlarging or reducing an original image, the pixel data of the original image read by the photoelectric conversion element is Generally, an enlarged/reduced image signal is obtained by increasing or subtracting appropriate image data by 1 depending on the enlargement ψ/reduction magnification.

Figure 29 shows the magnification and
FIG. 2 is a block diagram of main parts showing an example of a processing system for executing reduction.

In the figure, 40 is a memory for image data, and image data read by an image reading means is supplied to an input terminal 41 after being enlarged/reduced. The output image data obtained at the output terminal 42 is supplied to a recording device or the like to reproduce an enlarged/reduced image.

When enlarging/reducing, the amount of image data stored in the memory 40 is limited by the recording width of the recording device, but in this case, the generation timing of the address generator 47 for the memory 40 is controlled according to the reduction of the enlarged image. be done.

Therefore, the first and second counters 4 can be preset.
3.44 are provided, and respective preset values PI, P2
Clock CLK2 with a predetermined frequency up to (Figure 30C)
, the first and second output pulses CI, C
2 is generated (E in the figure), the first output pulse CI
The flip-flop 45 is set by the second output pulse C2 and reset by the second output pulse C2, thereby forming the window pulse WP shown in FIG. This window pulse WP is supplied to the gate circuit 46 as a gate pulse, and the address generator 4 is supplied with the width W1 of the window pulse WP.
7 is supplied with a clock CLK2. However, this clock CLK2.

This is a clock synchronized with the enlarged/reduced image data.

As a result, address data for the memory 40 is generated for one period W1, so the horizontal effective area signal (
Image data regulated by H-VALID (B in the same figure)
), the image data corresponding to one period W1 is stored in the memory 40.
(G in the same figure).

Therefore, if the preset values PI and P2 are changed according to the enlargement/reduction magnification, the width Wl of the window pulse WP will change accordingly.
The amount of image data written to is limited.

In the case of reduction, the window pulse WP and the horizontal valid area signal (H-VALID) are processed with the same width. On the other hand, in the case of enlargement, the number of data for one image increases, so
Taking this into consideration in advance, the horizontal effective area signal (H-VALI) is
The width of the window pulse WP is made narrower than the width of D) to reduce the number of data.

In addition, in such an image processing company i.

It is also possible to record an image at any position on the recording paper.

When specifying the recording position, as shown in Figure 30,
First, the width Wl is changed according to the magnification and the designated reading area, and recording on the recording paper is designated by one width W2.

[Problems to be Solved by the Invention] By the way, the above-mentioned conventional image processing apparatus causes the following problems.

That is, in the configuration shown in FIG. 29, although the amount of image data to be written to the memory 40 is limited depending on the magnification/reduction ratio, the write address is always the first address (O address) is specified, especially when applied to an image processing device where the reading device or recording device reads or records a document based on the center of the document or recording paper. Depending on the magnification, the image to be recorded may end up outside the transfer area of the recording paper.

For example, as shown in FIG. 31, when W is the maximum reading width of the image reading means, the image data of the original 52 is read based on the center line of the amta stand 51, and the image data is read based on this center line. 32B, when the image is enlarged to the same size, it is recorded as shown in FIG. 32B, but when it is reduced, it is recorded as shown in FIG. 32A.

This is because the first write address in the memory 40, that is, the 0 address, corresponds to the write start position l of the output bag 21 (recording device such as a laser printer). Therefore, when the size of the recording paper 53 to be recorded is small, the image may fall outside the transfer area of the recording paper, and in that case, the reduced image cannot be correctly recorded on the recording paper.

Even when the size of the recording paper 53 is large, there is a drawback that the reduced image is recorded on the edge of the recording paper 53.

Furthermore, during the enlargement process, the margins of the original document are also enlarged, resulting in an enlargement as shown in FIG. 32C. Therefore, there is a possibility that the required range of images cannot be recorded on the predetermined recording paper 53.

Further, some of such image processing apparatuses are configured so that an operator can specify a recording position from the outside. This means.

This image processing apparatus is capable of enlarging an area n of a document 52 shown in FIG. 33A and recording the enlarged image N at a designated position on a recording paper 53 shown in FIG. 33B, for example.

In such an image processing device, memory 4 is
In addition to controlling the write address to 0, the read address is controlled according to the position of the designated recording area, and furthermore, the horizontal effective area signal (H-
It is necessary to control the width of VALID).

Therefore, in the conventional image processing apparatus, as described above, the circuit configuration added to specify the recording position and its control have become extremely complicated.

Therefore, the present invention solves the above-mentioned conventional problems and proposes an image processing apparatus capable of specifying a recording position by simplifying the circuit configuration and control thereof for specifying the recording position.

[Means for Solving the Problems] In order to solve the above-mentioned problems, the present invention provides an image processing device that enlarges or reduces an image using image data obtained by photoelectrically converting image information and reading the image information. It is characterized by extracting only image information within a designated reading area, performing enlargement/reduction processing on the extracted image data, and recording the enlarged/reduced image data at a designated recording position. It is something.

[Operation] Information on the designated recording position is set according to the magnification and reading position information. This recording position designation information is used as data for controlling the write or read start address of the output buffer circuit.

By controlling the read or write start address, the start point of recording an image on the recording paper is controlled thereby, thereby making it possible to record an enlarged or reduced image at a position specified from the outside.

In addition, instead of writing or reading image data to or from the output buffer circuit from its first address, the writing or reading start address is automatically changed depending on the enlargement/reduction ratio, recording paper size, etc. Then, when reducing the image size.

Images are not recorded from the edges of the recording paper, and especially with types that record images based on the center, reduced images can be recorded correctly regardless of the size of the recording paper. .

When enlarging, since the front and back of the enlarged image data are not used as image data for recording, even the margins are not enlarged, so that the necessary image area can be recorded correctly.

[Example] Hereinafter, an image processing bag a according to the present invention in which the recording position can be specified.
An example of the case where this is applied to a type of processing based on a center line sentence will be described in detail with reference to FIG. 1 and subsequent figures.

FIG. 1 shows a schematic configuration of an image processing apparatus according to the present invention.

Image information such as the original 52 is converted into image data of a predetermined number of bits by the image reading device 50, which is subjected to image processing such as enlargement and reduction in the image processing circuit 2, and then processed by the output buffer 7 circuit 90 as described later. Image recording processing using a central reference and processing based on recording specifications are executed.

These processes are accomplished by controlling write or read addresses to the line memory provided in the output buffer circuit. The image data read from the output buffer circuit 90 is supplied to the output device 65,
An image is recorded at an externally set magnification or at an externally set position.

The image reading device 50 is equipped with a drive motor, an exposure lamp, etc. for driving the image reading means, and these are controlled at predetermined timing by control signals obtained from a sequence control circuit (sequence φ driver) 70. Ru. The sequence control circuit 70 receives data from a position sensor (not particularly shown).

In the operation/display section 75, various input data such as magnification designation and recording position designation are inputted, and an element such as an LED is used as a display means for displaying the contents.

The system control circuit 80 performs the above-mentioned various controls, controls the entire image processing device, and manages the state.
controlled by Therefore, microcomputer control using the system control circuit M80 (tcPU) is appropriate.

The figure shows an example of microcomputer control, and necessary image processing data and control data are exchanged between this control circuit 80 and the various circuit systems described above via a system bus 81.

The details will be explained below.

A single image reading start signal, a start signal for shading correction, and the like are supplied to the image reading device 50 via the system bus 81.

The image processing circuit 2 receives magnification data for specifying the magnification specified on the operation/display unit 75, threshold selection data for selecting a threshold for binarizing image data, and further specifies the recording position. Control 1g] i? 380 via the system bus 81. The output buffer circuit 90 is supplied with write or read start address data for the line memory provided therein. The write or read start address data preset in the line memory differs depending on the designated magnification, recording position designation data, etc.

The output device 65 is supplied with a start signal for recording one image, a recording paper size selection signal, and the like.

FIG. 2 shows a specific example of the image reading device ff150. The image information of the original 52 is captured by the image reading device 6 such as COD.
It is read as 0 and converted into an analog image signal. Third
The figure shows the relationship between the upper number of one image and various timing signals, and the horizontal effective area signal (H-VALID) (B in the same figure) is CC
060(7) Corresponding to the maximum original reading width W, the image signal shown in F in the figure is read out in synchronization with the synchronization clock CLK (E in the figure).

In FIG. 2, the top of one image is an A/D converter 61, and, for example, 0 image data, which is converted into image data having 16 gradation levels (0 to F), is subjected to shading correction in a shading correction circuit 62.

This is to correct shading caused by uneven sensitivity of the CCD 60, non-uniformity of the optical system, uneven illuminance of the irradiation lamp, etc. Therefore, before reading the document information, information (for one life) on a uniform density plate (white plate, etc.) provided in the non-image area of the reading device.
is read by the CCD 60, and this data is stored in the memory 63 as non-uniform data.

The non-uniform data for shading correction is supplied to the correction circuit 62 together with the original image data, and shading correction is performed for each pixel.

The shading-corrected image data is sent to the image processing circuit 2.
is supplied to the computer, and enlargement/reduction processing is performed in real time at the specified magnification.

The image data subjected to image processing is sent to the binarization circuit 23,
The rice planting data (for example, dither matrix data) stored in the spy table 69 is referred to and binarized. 2
The image data after the value conversion process is supplied to the output buffer circuit 90.

Note that the image data obtained from the output buffer circuit 90 is supplied to the output waveguide 65 to record the desired image information, but this output device 65 may be a printer using a laser printer, an LED printer, or the like. A recording device may be used.

Further, 66 is a reference clock generation circuit.

The reference clock output from the reference clock generation circuit 66 is supplied to a timing control circuit 67 to form various timing signals necessary for image processing. That is, C
In addition to timing signals for CD driving (transfer lock, etc.), timing signals for driving the address control circuit 68 for the memory 63, timing signals for the image processing circuit 2, and timing signals for the dark value table 69 for binarization. Timing signals etc. are generated.

FIG. 4 is a block diagram showing an example of the image processing circuit 2. As shown in FIG.

In this example, 1.5% between 0.5x and 2.0x
This is a case in which the image can be enlarged or reduced in increments (as an approximation of 17ff4).

Here, also in this invention, in principle, the enlarging process increases the image data, and the m-non-processing is an interpolation process that thins out the image data. The enlargement/reduction in the main scanning direction shown in FIG. I am trying to do this by changing the movement speed of.

Slowing down the movement speed in the sub-scanning direction enlarges the original image,
If you speed it up, it will shrink.

In FIG. 4, a timing signal generation circuit 10 is used to obtain timing signals for controlling the processing timing of the entire image processing circuit 2, and includes a CCD 60.
In the same way as for
-VALID) and a horizontal synchronization signal (H-5YNC).

In addition to the above-mentioned timing signals, the timing signal generation circuit IO outputs a clock CKL2 having twice the frequency of the synchronization clock CLK in order to process in real time a magnification up to 2 times.

A series of image data having 16 gradation levels sent out from the CCD 60 is supplied to two cascade-connected latch circuits 11 and 12 via a switching circuit 25, and two adjacent latch circuits 11 and 12 of the 4-bit image data are Pixel image data Di, DO are latched at the timing of the synchronous clock.

The switching circuit 25 is used, when setting an image area to be read, as shown in FIG. 33, to discard image information outside the set area. Therefore, the switching circuit 25 is controlled so that "0" data (data when the image is white) is latched outside the designated area. The control signal for the switching circuit 25 is generated by the timing signal generation circuit 10 described above, and it goes without saying that this timing signal generation circuit 10 is also controlled based on the reading area designation data supplied via the I10 port 26. .

Image data DI latched by latch circuits 11 and 12,
DO is used as address data for the memory 13 for interpolation data.

The interpolation memory 13 is a data table in which new image data (hereinafter this image data will be referred to as interpolation data) referenced from two adjacent image data is stored.
ROM etc. are used.

In addition to the above-mentioned pair of latch data Do and DI, the address data of the interpolation memory 13 includes a data selection signal S.
D is used.

The data selection signal SD is a pair of latch data DO, DI.
It is used as address data for determining which data from the data table group selected by is to be used as interpolation data.

The data selection signal SD is expanded as described later.

Determined by the set magnification for reduction.

FIG. 5 shows latch data DO, DI and data selection signal S.
An example of interpolation data S selected by D is shown. In the embodiment, data obtained by linearly interpolating DC and 01 data is used as interpolated data.

In FIG. 5, S is interpolated data (4 bits) output with 16 gradation levels, and since the image data Do and DI used as latch data each have 16 gradation levels, the interpolated data S is is 16X16=
It contains 256 data blocks.

The figure shows the theoretical values (5 decimal places) by linear interpolation at each step when Do = O, DI = F,
The values of interpolation data S that are actually stored are shown for each case of positive slope and negative slope.

Actually, interpolated data S is stored in the form shown in FIG. However, this data is DO=4. D+ =
This is an example of Q-F.

In FIG. 6, ADR3 is a base address, and when DO=4, data selection signal SD (data from 0 to F arranged horizontally) when DI takes a level from O to F. )and.

The actual address for the interpolation memory 13 is the sum of the address data ADR3, which indicates the relationship with the output interpolation data S, and the value of the data selection signal SD on the horizontal axis.

The interpolated data S output from the interpolation memory 13 is latched by the latch circuit 14.

On the other hand, 16 is an interpolation data selection memory in which a data selection signal SD is stored. A data table is also used here, and data (referred to as data selection signal SN) used as an address for selecting interpolation data is stored.

FIG. 7 shows part of the data selection signal SD used when enlarging one image. The example data is when the magnification rate M is 124/84, and the magnification can be set at intervals of 1764. Inside, Honda shows invalid data.

In this way, if the magnification can be set at intervals of 1/84, the repetition period will be 64, as shown in Figure 7.
becomes. Also, when the expansion rate is 124/84, the sampling interval is 84/124 (= 0.51813
), so the sampling position for the repetition period is 2
The relationship between 1 (theoretical value) and the data selection signal SD referred to at that time is as shown in the figure.

In the data selection signal SD at the repetition period "0",
For the former data (0), the sampling position l is (o, oo
ooO), and the latter data (8) has a sampling position of (0,51813).
This is the data selection signal SD at the time. These pairs of data selection signals SD differ depending on the value of the repetition period.

Note that when the repetition period is 15.32 and 48, the value of the latter data selection signal SD does not exist, which indicates that only one piece of data exists in that period.

These data are actually stored in the interpolation data selection memory 16 in a state as shown in FIG. In Figure 8, the base address ADRS (vertical axis) and the number of steps (
Of the data selection signal SD referenced by the horizontal axis), the data on the right side indicates data for write clock control (referred to as processing timing signal TD), as will be described later.

When the processing timing signal TD is "L", it becomes a writable state m (write enable), and when it is "O", it becomes a write inhibit state. Therefore, data "00" in the figure indicates invalid data.

Figure 9 shows the interpolation data selection signal SD used during image reduction.
The illustrated data is a case where the reduction rate M is 33784.

In the figure, Honda indicates thinned-out data, and this data selection signal is also stored in the memory in the state shown in FIG. 1O.

Now, the address terminals A7 to A13 of the upper seven bits of the interpolation data selection memory 16 mentioned above have the I10 port 27.
The magnification signal set on the operation/display unit 75 is supplied as address data via the address data. The counter output of the counter circuit 15 is supplied as address data to the lower 7 bits of address terminals AO to A6. Therefore, the counter circuit 15 is supplied with the synchronous clock CLK2.

An interpolation data selection signal S is sent from the interpolation data selection memory 16.
In addition to D, a processing timing signal TD is output.

As described above, the processing timing signal TD is selected to be "1" when interpolated data exists, and "0" when it does not exist or when data is to be thinned out.

The data selection signal SD and the processing timing signal TD are latched by the latch circuit 17. The latch timing is regulated by the synchronous clock CLK2.

The processing timing signal TD controls the timing of the interpolated data S to be latched in the latch circuit 14. Therefore, the processing timing signal TD is once supplied to the latch circuit 18 and is delayed by the access time of the interpolation memory 13. Ru.

The processing timing signal TD delayed by a predetermined time (one period of the synchronous clock CLK2) is supplied to the gate circuit 19 as its gate signal.

The gate circuit 19 is supplied with two synchronized clocks CLK2, and is opened when the processing timing signal TD is "L", and is "O".
It is controlled so that it is closed when it is '1', and a clock is output only when it is '1'.

The write clock output from the gate circuit 19 is used as a latch pulse for the latch circuit 14 to latch only valid data among the interpolated data S output from the interpolation memory 13. The write clock is also used as a write clock for the output buffer circuit 90 at the subsequent stage.

What has been described above is the main configuration of the image processing circuit 2. After the output data obtained from the image processing circuit 2 is once binarized, it is processed by the output buffer circuit 90 (details will be described later).
is supplied to the output device 65 via.

An example of the circuit configuration for binarization processing will be explained with reference to FIG. 4 again.

In the figure, the threshold table 69 includes a main scanning counter 20 that counts write clocks, a sub-scanning counter 21 that counts horizontal synchronization signals, and these counters 20.
．． The dither matrix 22 outputs a dither threshold value based on the count value of 21.

Then, in the z-value converting circuit 23, the image data output from the latch circuit 14 is compared with the dither threshold value from the dither matrix 22, and binarized for each pixel.

Next, the image processing operation of the above-mentioned image processing device 2 will be explained in detail, starting with the enlargement processing operation, with reference to FIG. 11 and subsequent figures. For convenience of explanation, the magnification rate M is 124/84C=
1.94) times.

FIG. 11 is an analog diagram of the relationship between original data and interpolated data, where D indicates the original data and S indicates the output data after interpolation.

The relationship between the image information level and the interpolated data at this time is as shown in FIG. Further, the relationship between the sampling pitch and the data selection signal SD during interpolation at this time is as shown in FIG.

A timing chart of signals in each section during this interpolation process is shown in FIG.

Therefore, the original image data obtained from the CCD 60 are now D0(0), DI(F), and D2(F).

D3(0), D4(0) (the gradation level of each image data is shown in parentheses), DI(F) is output from the latch circuit 11 and Do is output from the latch circuit 12 in synchronization with the synchronous clock. (0) is output.

On the other hand, the data table shown in FIG. 8 is referred to based on the externally set magnification signal and the output of the counter circuit 15, and the data selection signal SD is set as 0.8;0,8.1.
9.1,9. ... (Fig. 12E) is output, and the processing timing signal TD is 1, 1, 1 . ...(FIG. F) is output.

The interpolation memory 13 refers to the interpolation data table using the image data 00.01 and the data selection signal SD, and outputs necessary interpolation data S (G in the figure).

That is, since the data selection signal SD is O and 8 between the image data DO(0) and DI(F), 0 and 8 are output as the interpolation data SO and St.

Since the data selection signal SD is 0 and 8 between the image data DI(F) and D2(F), the interpolated data S2
And as S3, F and F are output.

Since the data selection signal SD is 1 and 9 between image data D2(F) and 03(0), interpolated data S4
And E and 7 are output as S5.

Since the 1 selection means SD is 1 and 9 between the image data D3(0) and 04(0), 0 and 0 are output as the interpolation data S6 and S7.

Subsequent image data D5. Regarding DB, . . . , the interpolated data S is read in the same manner as described above.

Therefore, if the interpolated data is represented by an X mark, it can be seen that image data having a predetermined level between the original image data is interpolated and output as shown in FIG.

In this way, the interpolated data SO to S7 are sequentially read out using the interpolation method for the actual image data DO to D4,
These interpolated data S are sequentially sent to the latch circuit 14 (X in the figure).

On the other hand, the processing timing signal TD output from the latch circuit 17 is sent to the latch circuit 18 for a time t (see FIG. 12). However, as described above, this delay time t is the time required for data access in the interpolated data memory 13, and is the time required for the latch circuit 14 to read the interpolated data S.

Since the on/off of the gate circuit 19 is controlled by the processing timing signal TD from the latch circuit 18, the latch circuit 14 performs the latch operation only when the gate circuit 19 is on, and the latch operation is not performed at other times. Not possible.

Next, the reduction process will be explained.

FIG. 13 is an analog diagram of an image signal in the case of reduction processing, and is image data DO.

D I , D2 , D3 , ----- C 0 mark te, interpolation data 30.31 , . . . are represented by cross marks. Figure 14 shows a timing chart of the signals at that time, the relationship between the original image data D and interpolated data S used at that time is shown in Figure 5, and the relationship between the data selection signal SD is shown in Figure 9. That's right.

Note that the reduction ratio M illustrated here is 33/84 (・0.5
2), and the gradation level of the image data is the same as in the case of the enlargement process described above.

Two adjacent image data (
For example, one image data DI, Do) is supplied to the interpolation memory 13 as an address signal, an externally set reduction magnification (33/84) is supplied to the interpolation data selection memory 16, and a synchronization clock CLK2 is supplied to the counter circuit. 15
The counting is the same as in the case of the enlargement process described above.

As is clear from FIGS. 9 and 10, the 1 selection memory 16 outputs 09 lines; 19 lines: 1 line, E, O, etc. as data selection signals SD, and processes The timing signal TD is 1.0°1.0,0,0,1
．． ... is output. However, since the book is invalid data, 0 data is stored in the interpolation data selection memory 16.

Therefore, interpolated data S as shown in FIG. 14 is read out from the interpolated data memory 13.

That is, since the data selection signal SD is 0 and zero between one image data Do(0) and DI(F), only 0 is output as interpolation data 5 (=SO).

Between the image data DI(F) and 02(F), since the data selection signal SD is F and this, the interpolated data 31
As, F is outputted as 0 image data D 2(F) and 0
Between 3(0) and 04(0), since the data selection signals SD are both real, no interpolation data S is output.0 image data D. Between 3(0) and 04(0), the selection data SD Since E is a book, only 0 is output as interpolation data S2.

Subsequent image data D4. D5. . . . The interpolation data S is read out in the same manner as described above.

In this way, the actual image data no, at.

. . ., the interpolated data so, st, . . . are sequentially read out, and the interpolated data S is sequentially transferred to the latch circuit 14. Ru.

On the other hand, the processing timing signal TD is 0,1,0°0.0.
1... (F in the same figure), the gate circuit 19
Since the write clock output from 1 is as shown in FIG. 14H, certain data are thinned out and the interpolated data
, 31. ...... is output (I in the same figure).

As mentioned above, when reducing the size, new image data is given between the original pixels of the original image information and that image data is output, and some of the image data of the original pixels is thinned out or left as is. These output image data are generally referred to as interpolation data.

In the embodiment described above, if the magnification of enlargement or reduction is changed, the data selection signal SD output from the selection memory 16 for interpolation data changes, and the memory 13 for interpolation data is addressed accordingly to perform the corresponding interpolation. It will be clear that data S is output.

Now, the image data that has been subjected to enlargement/reduction processing and binarized processing is supplied to the output buffer circuit 90, but in this output buffer circuit 90, based on external specified data such as the enlargement/reduction magnification, The starting address for writing or reading data to the line memory provided in the output buffer circuit 90 is controlled.

First 1. The reason why the reading or reading start address is controlled according to the specified magnification will be explained with reference to FIGS. 15 and 16.

For example, if the maximum image reading size of the CCD 60 is 84 format and its resolution is 18 dots/am', the amount of image data for one line is 4096 bits, which is 1 image data considering the 0 magnification is up to 2 times. As a storage line memory, a line memory having a capacity of 8192 bits as shown in FIG. 15 is prepared.

Then, image data is written or read out with the center of the recording paper serving as a reference.

Therefore, when reducing an image to, for example, 1/2, the writing start address of the line memory is 40.
Since the address corresponding to 1/4 of 96 bits (1024th address) will be set, in that case the reduced image data will be written to the line memory in the state shown in Figure 15A. .

On the other hand, the read start address is set to 0 address. Therefore, a reduced image is recorded as shown in FIG. 16A.

This is because the image data from address 0 to address 1023 is "0", so that period is considered white and recorded on the recording paper, and recording based on the reduced image data starts from address 1024. This is because it becomes.

For example, when the reduction ratio is 32/84, reduced image data is written from 1024 addresses. Similarly 33/84
When the reduction rate is , data is written from 992 addresses, and 3
At a reduction rate of 4/84, data will be written starting from 960 addresses.

In this way, if the image data is written so that the result is in the center, and the 0 address is used as the reference for reading, the image will be recorded using the center line current reference of the recording paper 53.

For this reason, the write start address when reducing is
The settings are as follows.

Write start address = (409B-4098X reduction magnification)/2 When enlarging an image, one image data increases, so the read start address is controlled in the opposite manner to when reducing.

If the maximum magnification is 2x, the image data at that time will be twice the image data at the same magnification.

In that case, the area of the recorded image will be quadrupled, so if you are trying to double the size of an 84-size document, but the maximum size of the recording paper is up to 84-size, the entire enlarged image will be printed on the recording paper. cannot be recorded.

Taking this into consideration, it is possible to obtain a more natural enlarged image by limiting the maximum size of the recording paper so that the processing results of the central portion of the document are recorded.

Therefore, when enlarging one image, as shown in FIG. 15B, a total of 4096 bits, 2048 bits before and after 1/2 of the enlarged image data amount (corresponding to the center of the enlarged image and the position of one sentence), are used as a reference. The bit will be read.

Therefore, when the enlargement ratio is 128/84, the data from the first data to the 2047th bit of the enlarged image data is ignored, and reading to the line memory starts from the 2048th bit data, and from this point on, a total of 40
96-bit image data will be read out.

On the other hand, the corruption start address is set to the O address.

Similarly, when the magnification is 127/64, reading starts from the 2016th bit [1, and when the magnification is 124/64, reading starts from the 1984th bit, and from this, a total of 4096 bits of image data is obtained. It will be read out.

Needless to say, even when setting another magnification rate, image data from the readout start address corresponding to the magnification rate is selected.

For this reason, the reading start address during enlargement is set as follows.

Read start address = (4098X enlargement magnification - 4098)/2 or more In summary, the write and read start addresses at the time of enlargement/reduction are set as shown in FIG. 17.

The above is an example of setting a write or read start address when an image is processed with the center as a reference.

Next, only the image data of the specified area is read.

Next, an example of setting a write or read start address necessary for recording an enlarged/reduced image at a designated recording position will be explained.

FIG. 18 is an explanatory diagram of recording position designation, and for convenience of explanation, the diagram is an explanatory diagram when enlarging one image, but it goes without saying that it can also be applied to the case of image reduction.

First, assuming that the image area to be read is n1 to n4 and the recorded image area as a result of enlargement/reduction is Nl-N4, each coordinate located on the diagonal of one image area n1 to n4 is (xi
, yl), (x2, y2).Similarly, among the coordinates located on the diagonal of the recording image area N1-N4, the minimum coordinate is (x3.y3).Also, the readout image area and the recording In the main scanning direction (horizontal scanning direction) and sub-scanning direction (vertical scanning direction) from the reference point in the image area (the edge of the original 52, which refers to the point (x, y) - (0, 0)) As shown in the figure, the number of data or lines up to the above coordinates are IO, II, LO, Ll.
shall be.

When image areas n1 to n4 are specified.

The input image data is controlled by the timing generation circuit 10 so that the data outside the designated area becomes O (white information) by the switch changeover circuit 25 shown in FIG.

FIGS. 18A and 18C are examples of II) IO, and FIGS. 18B and D are examples of It(1,0).

The case will be explained starting from the case where xx>xc.

When the recording density is 1Bdata/ms as mentioned above, IO,It is.

l0=16Xx1 11=16Xx3 Here, if the specified magnification is m.

The image data of IO increases to m・t 0・Meanwhile, 11
As described above, the relationship between them can be illustrated as shown in FIG. 19.

In addition, when trying to record the image area nl, the process 0
As mentioned above, the data is O data (white information),
Further, 11 data in the recording area Nl is O data in which nothing is recorded.

Now, in the example shown in FIG. 19, 11>mlll0, so if the enlarged image data is written as it is to the line memory and read out, the original image data will not be displayed before reaching the recording start point X3 in the horizontal direction. The enlarged image data m·(x2-xl) in the image area n1 will be recorded, and will be recorded off the designated recording start point.

To prevent this from happening, it is necessary to control the writing start point of enlarged image data to the line memory. That is, in such a case, as shown in FIG.
The difference between and ms IO is the amount of deviation of the recording start point, so
The enlarged image data may be written to the line memory from 21A (1) to account for this amount.

In this way, the address AI to which the designated image data is written becomes as shown in FIG. 20.

The number of data up to address AI corresponds to II.

This immediately corresponds to the water motion coordinate x3 in the recording coordinate system.

Therefore, in the case of It)IO and It)m.IO, three enlarged image data are loaded from the AO=II-m.IOth address and are read from the O address. Also.

As described later, the line memory is cleared with O data (white information) during the period when no enlargement/reduction processing is performed, so "O" data is written from O address to AO address. It means that it is included.

It (IO, mIIIQ) 11c7) Sometimes,
As is clear from FIGS. 21 and 22, enlarged image data is written from address 0, whereas image data is read from the address corresponding to AO=m11IO-11. .

By doing this, even in the case of m·10) If, the image will be correctly recorded from the set horizontal coordinate point x3. The same applies to m-IO (II). In this way, by setting the write or read start address for the line memory according to the set magnification and specified coordinates, the horizontal movement of one image recording position is possible. It becomes possible.

The movement of the image recording position t in the vertical direction is realized by controlling the operation timing, such as by advancing the reading start of the image reading device 50 or the writing start of the output device 65.

If only the results are shown, when Ll > LO, TO=
(Ll-m-LO) - Starts the output device 65 earlier than usual by the main scanning time. The main scanning time refers to the time required in the main scanning direction to scan one line.

Ll (when LO.

TO=(LO-m-Ll) The image reading device 50 is started earlier than usual by the main scanning time.

In addition to selecting the operation timing in this way.

By selecting the write and read addresses described above, it is possible to correctly record the enlarged/reduced image in the read area at a preset recording position.

Such addressing data may be stored in a ROM table provided in the system control circuit 80 or the like.

FIG. 18 shows an example of enlarging an image.
Needless to say, the present invention can also be applied to the case where only the recording position is moved and recorded in the can processing, or when the image is recorded after being subjected to reduction processing.

Now, FIG. 23 and subsequent figures are circuit diagrams showing an example for realizing the above-described image recording operation based on the center reference or image recording operation based on recording position designation.

FIG. 23 shows an example of the output buffer circuit 90.

The output eight circuit 90 includes a pair of line memories Zoo,
Lots are provided, and image data for one line is supplied to each Lot. The reason why the pair of line memories ioo and iot is provided is to alternately supply image data for one life so that image data loading and reading can be processed in real time. Line memory 100, 101
As mentioned above, one having a capacity of 8192 bits is used.

When recording an image with the center as a reference, writing and reading to and from the line memories too and tot are controlled as follows.

First, when writing data to the line memory, the write clock (clock generated in the image processing circuit 2)
is used, and the read clock for the output device 65 is used during reading, so these clocks are supplied to the respective address counters 104 and 105 via the first and second switches 102 and 103 for clock selection. .

The first and second switches 102 and 103 are controlled in a complementary manner so that when one line memory is in a write mode, the other line memory is in a read mode. The switch control for this is the control circuit 10.
The water cycle control signal (the 24th
Figure C) is used.

Address data for determining the write start address and read address for the line memories 100, 101 are further supplied to the respective address counters 104', 105 via third and fourth switches 108, 109. Third and fourth switches 108, 10
9 are also complementary controlled so that when one address counter is in the write mode, the other address counter is in the read mode, and these switches 108 and 109 are also controlled as shown in FIG. 24C. A control signal with a horizontal period as shown is supplied.

The write start address or read start address is preset in the address counter 104 or 105 in synchronization with the horizontal synchronizing signal (FIG. 24A). CPU80
The above-mentioned write or read address generated in
8°109.

Outputs from the line memories 100 and 101 are selected by the fifth switch 110 and then supplied to the output device 65 described above. Since the fifth switch 110 is for selecting image data in the read mode, a signal having a phase opposite to that of the control signal shown in FIG. 24C is used.

Now, a sixth switch 140 is provided on the data supply line of the pair of line memories 100 and 101, and the original image data and 0 data (corresponding to own information) are selected. This is data for clearing the line memories 100 and 101, and is selected when no original reading is being performed.

In the case of recording position specification mode, in addition to inputting the coordinate data of coordinates (xi, yl) and (x2, y2) indicating the read image area, the coordinates (x3) specifying the recording position are input.
．． y3) and designated magnification m are input from the operation/display section 75.

Inputting these data can be done by manually inputting the keys directly by the operator as described above, or by placing the document 52 on a pointing device such as a tablet, directly specifying the position, and having the system control circuit 80 input the coordinates. It may also be read.

Even if the keys are manually operated, each coordinate can be specified by inserting the original 52 into a transparent holder with M lines at a predetermined pitch in the vertical and horizontal directions.If such a transparent holder is used, the coordinates can be read. can be done quickly.

Addresses are calculated from each of the above-mentioned input data (a ROM table in which the addresses are stored may be used), and write and read addresses to and from the line memories 100 and 101 are selected in a predetermined manner. At the same time, speed control data is calculated and this is used by the image reading device ff15.
0, the reading speed is regulated to a specified magnification and a one-image reading start signal is supplied.

A recording start signal corresponding to the designated magnification and recording position is also supplied to the output device 65.

Incidentally, in the above description, the invention is applied to an image processing apparatus that reads an image based on the center of the document and records the image based on the center of the recording paper, but the present invention can also be applied to other image processing apparatuses. can do.

First, when both image reading and image recording are processed based on one side of the original (recording paper),
Image reading start position of CCD 60 and recording start position (
with a laser printer.

Since the recording beam start position of the laser beam is the same, the present invention can be applied without any problem.

Second, in an image processing apparatus of the type in which image reading is performed with reference to the center line of the document and one image recording is processed with reference to one side of the recording paper, writing to the output buffer circuit 90 and the start address are It will be like the next one.

In this case, the write start address to the line memories 100 and 101 is always the O address.

On the other hand, the readout start address cannot be determined only by the magnification signal and differs depending on the size of the document.

So this kind of image processing? At t21, a readout start address is determined from the signal indicating the document size and the magnification.

As shown in FIG. 25, the case where the size of the document 52 to be read is A4 size will be described below.

As mentioned above, when L8dotg/Tsuru■, A
What is the number of bits for the width of 4-size paper?

210mm x 113dotg/am = 33
Since it is 80 bits, the maximum document size to be read is 8
If it is 4 size, Ill! in Figure 25. The value obtained by multiplying Y by the magnification becomes the read start address for the line memory.

Therefore, the read start address at the same magnification is (4011
111-3380) / 2 = 388 bits.

The value of the write and start address at any magnification is
As shown in FIG. 6, the original size is A4.

Thirdly, as shown in FIG. 27, in an image processing apparatus of the type in which one image is read based on one side and one image recording is processed based on the center line of the recording paper, the output buffer circuit 90 The writing and start address to is determined as follows.

In this case, the maximum number of bits for A4 size (3360 bits) and the maximum number of bits for 84 size (4096 bits)
The write start address is determined from the bit). That is, write start address=(409B-3360X magnification)/2. At this time, the read start address is the O address.

When the write start address becomes negative (at the time of expansion), that value becomes the value of the read start address. Therefore, the write start address at this time is 0 address.

FIG. 28 shows the values of write and read start addresses at arbitrary magnifications.

In this way, the writing or reading start address can be changed depending on the reading or writing reference position of the document. Further, the writing start address to the line memories 100 and 101 may be changed depending on the paper size of the recording paper.

In addition, in the above-mentioned embodiment, the enlargement/reduction ratio is set to 128/8.
Under the condition that the frequency can be selected from 4 to 33/84 in increments of 1/'1141, the frequency of the synchronization clock CLK2 obtained by the timing generation circuit 10 is twice that of the reference synchronization clock. The frequency is determined by the maximum magnification.

For example, when the maximum enlargement rate is selected to be three times, the frequency of the synchronization clock CLK2 is set to three times the frequency of the reference synchronization clock. Therefore, the frequency of the synchronization clock CLK2 is changed depending on the maximum enlargement ratio used.

The memories 13 and 16 may use RAM instead of ROM, and the memory 13 may use an arithmetic circuit instead.

[Effects of the Invention] As explained above, in the present invention, the output buffer circuit 90 and the like are controlled according to the settings of the designated magnification, designated recording area, etc.
The reduced image can be recorded in real time. Therefore, it has the feature that an image of an area desired by the operator can be recorded at a desired position on the recording paper and an image of a desired size.

Of course, in this invention, since the writing or reading start address to the line memory is controlled according to the magnification, the same effect as when enlarging/reducing is performed based on the center of the reading side can be obtained. , the recording will be performed with the center of the recording paper as a reference.

As a result, there is no risk that the reduced image will be recorded unevenly or that the image will be recorded outside the transfer area of the recording paper, and even when the image is enlarged, there is no risk that it will be enlarged to the margins, so the required image It has characteristics such as being able to record correctly.

Furthermore, since the present invention obtains interpolated data while referring to a data table, it has remarkable effects such as better image quality than conventional methods and high-speed processing in multiple passes.

[Brief explanation of drawings]

FIG. 1 is a system diagram showing an overview of an image processing device that can be enlarged and reduced according to the present invention, FIG. 2 is a system diagram showing an example of an image reading device, and FIG. 3 is a waveform diagram for explaining its operation.
Figure 4 is a system diagram showing an example of an image processing circuit, Figure 5 is a diagram showing an example of interpolation data used when enlarging an image, Figure 6 is a diagram showing an example of interpolation data used at that time, and Figure 7 is a diagram showing an example of interpolation data used at that time.
The figure shows an example of selection data used when enlarging an image.
Figure 8 is a diagram showing the contents of the data table of the data selection signal and processing timing signal at that time, Figure 9 is a diagram showing an example of the data selection signal used during image reduction, and Figure 1O is the data selection at that time. A diagram showing the contents of a data table of signals and processing timing signals, FIG. 11 is a signal waveform diagram for explaining the image enlargement processing operation, FIG. 12 is a timing chart at that time, and FIG. 13 is an explanation of the image reduction processing operation. FIG. 14 is a timing chart at that time, FIG. 15 is a diagram for explaining the line memory, FIG. 16 is an explanatory diagram of recorded images, and FIGS. 17, 26, and 28 are diagrams for explaining the recorded image. FIG. 18 is an explanatory diagram of recording position designation, and FIGS. 19 to 22 each show an example of a write start address, etc.
23 is a system diagram showing an example of the output buffer circuit, FIG. 24 is a waveform diagram explaining the operation, and FIGS. 25 and 27 are for image reading, image recording, etc. FIG. 29 is a system diagram showing an example of the main parts of a conventional image processing device that can be enlarged and reduced.
Figure 0 is a waveform diagram to explain its operation, Figure 31 is an explanatory diagram of the image reading system, Figure 32 is an explanatory diagram of the recorded image, and Figure 3 is an explanatory diagram of the recorded image.
FIG. 3 is an explanatory diagram of image recording by specifying a recording position. 2... Image processing circuit 10... Timing signal generation circuit 11.12, 14, 17.18... Latch circuit 13.
... Interpolation data memory 15 ... Counter circuit 16 ... Interpolation data selection memory 19 ... Gate circuit 22 ... Dither matrix 23 ... Binarization circuit 50 ... Image reading device 60 ... Image reading means (COD) 65...Output device 70...Sequence control circuit 75...Operation φ display section 90...Output buffer circuit 100.101...Line memory 104.105...Address counter 102.103
, 108, 109° 110.140...First to sixth switches D...Image data S...Interpolation data SD...Data selection signal CLK2...Synchronization clock TD...Processing timing signal PE... Control signal Patent applicant Konishi Roku Photo Industry Co., Ltd.''-, Chopsticks! Figure 5 Data selection signal SD 6th Interpolation memory 1 Figure → number of steps +8 +9 +A +B +C+D +E
+F3 content data Koda No. 11 5D Himodo +O+1 +2 +3 +4 +5
+8 +'i data selection memory 16 -' +8 +9 +A +B +C+D
＋E +F 搏晪洓大率124/64增）Figure 12 “O”1 ”: Q S) 3 :84 55 56
57 1C Internal view of data selection memory 16 → Step number of years G Ret rate 33/84 4 I θ 1-11-m・I□) ml□ + Figure 21＼book, )＠, A1. L/Eng. Fig. 26 Fig. 28 Fig. 31°

Claims (4)

[Claims] (1) In an image processing device that enlarges or reduces an image using the image data read by photoelectrically converting image information, only the image information within the designated reading area is extracted and the extracted image data is enlarged. - An image processing device capable of specifying a recording position, characterized in that it performs reduction processing and records the enlarged/reduced image data at a specified recording position. (2) The image processing device capable of specifying a recording position according to claim 1, wherein the enlarged/reduced image data is temporarily stored in an output buffer circuit. (3) The image processing device capable of specifying a recording position as set forth in claim 2, wherein a write or read address for the output buffer circuit is controlled in accordance with a specified magnification. (4) Image processing capable of specifying a recording position according to claim 2, characterized in that the write or read address for the output buffer circuit is controlled according to a specified magnification and a specified recording position. Device.