JPS62245433A - Floating point arithmetic circuit - Google Patents

Abstract

PURPOSE:To easily and surely prevent an overflow from generating at a rounding circuit at the time of subtraction, by providing a rounding overflow detection circuit. CONSTITUTION:An increment circuit constituting a rounding circuit 14 is equipped with a data input terminal DIO, a data output terminal DOO, and a control signal terminal CI, and an increment operation is performed when the control signal terminal CI is at a level '0'. When all of the normalizing shifter input data 90 are at levels '1', each of AND circuits 21-1-21-N outputs '1'. Therefore, the output of an AND circuit 22 which inputs each output of the AN circuits 21-1-21-N, also goes to '1', and the output becomes the input of the control signal terminal CI of the increment circuit constituting the rounding circuit 14. For this reason, the increment operation is prohibited, and it is possible to inhibit the overflow.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to a floating point arithmetic circuit in a digital signal processing processor, etc.
This relates to floating point arithmetic circuits that prevent overflows.

(Prior Art) Some digital signal processors and the like that process digitized signals employ floating point arithmetic circuits as their arithmetic circuits in order to expand the dynamic range.

Conventionally, technologies in this field include TRW Catalog rTDc1022 J (1984) (USA) P.
There was one described in 307-311. The configuration will be explained below using figures.

FIG. 2 is a block diagram showing an example of the configuration of a conventional floating point arithmetic circuit.

Generally, floating point data handled by a digital signal processor etc. consists of a combination of a sign, an exponent part, and a mantissa part, and the mantissa part uses two's complement representation. It is assumed that the mantissa part of the data processed in FIG. 2 has a width of N bits.

The floating point arithmetic circuit shown in FIG. 2 has a data input terminal 1.2 and a data output terminal 3, and the data input terminals 1 and 2 are connected to a mantissa switch circuit 4, an exponent comparison/subtraction circuit 5, and a selector 6. is connected. Mantissa switch circuit 4
Of the two output terminals, one terminal is connected to an arithmetic and logic operation unit (hereinafter referred to as group A) 8 which performs arithmetic operations and logical operations through a digit shifter 7, and the other terminal is directly connected to the ALU 8. It is connected to the. , the output terminal of the ALU 8 is connected to an overflow correction circuit 9.
An output terminal of is connected to an increment circuit (incremental circuit) 10 connected to the selector 6, and also to a normalized shift amount detection circuit 11.

The output terminal of the normalized shift amount detection circuit 11 is connected to an addition circuit 12 connected to an increment circuit 10 and also to a normalization shifter 13 connected to an overflow correction circuit 9. Further, the output terminal of the adder circuit 12 is connected to the data output terminal 3, and the output terminal of the normalization shifter 13 is connected to the data output terminal 3 via the rounding circuit 14.

Next, the operation will be explained.

The input data D1゜D2 inputted from the input terminals 1.2 has its exponent part compared with the exponent part/subtraction circuit 5 and the selector 6.
and the mantissa parts are respectively input to the mantissa switch circuit 4. The exponent comparison/subtraction circuit 5 compares and subtracts the exponent parts of the input data, and the selector 6 and the mantissa switch circuit 4 are selected based on the results. The input data D1 or 02 having the smaller exponent part is sent by the mantissa switch circuit 4 to the mantissa data 61 matching shifter 7 for digit alignment, and is shifted for digit alignment. The ALU 8 performs addition or subtraction of mantissa parts between the data whose digits have been aligned. Since an overflow may occur in the arithmetic processing by the ALU 8, an overflow correction circuit 9 corrects the overflow (scale down), and as a result, an increment circuit 10 corrects the exponent part.

The output of the overflow correction circuit 9 is input to a normalization shift mother detection circuit 11, which detects the shift amount for normalization. The normalization shifter 13 performs normalization processing on the mantissa part using the detected shift 1 to amount values, and the addition circuit 1
In step 2, the exponent part is corrected.

As described above, digit alignment and overflow correction are performed in the floating-point arithmetic circuit, but in order to prevent the precision of the mantissa from deteriorating due to this process, the mantissa is internally divided into the mantissa parts of the input data DI and D2. It is common for the width N hits to be expanded to take a value of (N+1) bits or more. However, when taking out the operation result from the output terminal 3, it is necessary to make the mantissa part N bits again. You need to use one of the methods.

In the case of digital signal processing, truncation processing is a cause of noise and is not desirable; therefore, a rounding circuit 14 is usually provided, and rounding is performed by forcibly adding 1 to the (N→1)th bit from the upper digit of the mantissa data. Process.

(Problems to be Solved by the Invention) However, the circuit with the above configuration has the following problems.

As shown in the explanatory diagram of rounding overflow in FIG. 3, when the maximum negative value is subtracted from the maximum positive value of the mantissa for data that has the same exponent part, an overflow occurs in the rounding circuit 14. It may output meaningless data. Therefore, in conventional floating point arithmetic circuits, it is necessary to inhibit rounding when performing subtraction. Therefore, there is a problem that not only an extra operation is required to prohibit the rounding process, but also the rounding process cannot be performed when the latitude is decreased.

The present invention provides a floating point arithmetic circuit which solves the problem of the prior art, which is that rounding cannot be performed when performing subtraction.

(Means for Solving the Problem) In order to solve the above problem, the present invention converts floating point data whose N-bit mantissa is represented by two's complement into a mantissa (N
+1) In a floating point arithmetic circuit that is equipped with a circuit that performs arithmetic processing in terms of bits or more, and a rounding circuit that rounds the mantissa part to N bits at 3 o'clock, the result of the arithmetic operation by the circuit is a rounding overflow detection circuit that detects in advance an overflow occurring in the rounding circuit based on the above and inhibits rounding processing of the rounding circuit;
8 It was worth it.

(Function) According to the present invention, since the floating point arithmetic circuit is configured as described above, the rounding overflow detection circuit detects in advance an overflow that occurs in the rounding circuit, and uses the detection binding to perform the rounding process of the rounding circuit. move to ban it.

This prevents overflow from occurring in the rounding circuit. Therefore, the above-mentioned problem can be eliminated.

(Embodiment) FIG. 1 is a configuration block diagram of a floating point arithmetic circuit showing an embodiment of the present invention, and the same elements as the conventional elements in FIG. 2 are given the same reference numerals.

The difference between this floating point arithmetic circuit and the conventional one shown in Figure 2 is that
A rounding overflow detection circuit 20 is provided between the output terminal of the overflow correction circuit 9 and the input terminal of the rounding circuit 14. Based on the output data of the overflow correction circuit 9, the rounding overflow detection circuit 20 detects the rounding circuit 1.
The rounding circuit 1 detects in advance the overflow that occurs in the rounding circuit 1.
This is a circuit that prohibits rounding of 4.

The operation of the floating point arithmetic circuit configured as described above will be explained.

In floating point arithmetic, as in the past, input data DI,
The mantissa part of D2 is added or subtracted by ALU 8, the result is normalized and shifted by normalization shifter 13, and rounding circuit 1
4, a predetermined rounding process is performed and the calculation result of the mantissa part is outputted from the data output terminal 3, and the calculation result of the exponent part processed by the adder circuit 12 etc. is also outputted from the data output terminal 3.

Next, when executing the above calculation, the input data DI,
The mantissa part of D2 is N hits, and inside the arithmetic circuit it is (N+1
) The difference from the conventional operation will be explained, assuming that the width of the bit is taken.

If the input data of ALU a is N bits, the ALU
The output of 8 becomes (N+1) bits to prevent overflow. Thereafter, the overflow correction circuit 9 performs overflow correction, but in order to prevent truncation at this time, the number of bits remains (N+1) even after correction.

This result is subjected to normalization processing by the normalization shift amount detection circuit 11 and normalization shifter 13, and further rounding processing is performed by the rounding circuit 14. At this time, since the sign bit is unnecessary, (N+1 > These processes are performed on the lower N bits of the bits.As a result, the input to the rounding circuit 14 also becomes data with a width of N bits.Rounding circuit 14
is realized, for example, by an increment circuit that adds 1 to [S8 (least significant bit) of N-bit data. Therefore, an overflow occurs in this rounding circuit 14 because all the input data bits of the rounding circuit 14 are " There is only a pattern that takes a value of 1''.The input of the rounding circuit 14 is the output from the normalization shifter 13, but when the normalization shifter 13 performs a shift, "Oat" is input from the LSB side. ,
An all-1 pattern is input to the rounding circuit 14 only when the normalization shifter 13 does not perform any shifting.

Moreover, the normalized input data takes an all-one pattern only in the case of positive data.

This means that (N+1) is all 1° for negative data.
This is because there is no such pattern.

In the case of positive data, since it is an all-one pattern, it is normalized data, and normalization shift by the normalization shifter 13 is not performed. Therefore, by determining whether an overflow will occur in the rounding circuit 14 depending on whether or not the input data of the normalization shifter 13 takes all "1" values, measures can be taken to prevent an overflow from occurring. I can do it.

Therefore, by inputting the input data of the normalization shifter 13 to the rounding overflow detection circuit 20, it is detected whether the input data of the normalization shifter 13 takes all values of 1°. At this time, if all "1" is detected,
As a rounding overflow, the rounding circuit 14 is disabled and rounding is prohibited.

FIG. 4 is a diagram showing an example of the circuit configuration of the rounding circuit 14 and the rounding overflow detection circuit 20 in FIG. 1. In FIG. 4, it is composed of a rounding circuit 14 or an increment circuit, and a rounding overflow detection circuit 20i14 manually operated AN
D (logical product) circuits 21-1 to 21-N, 22 are configured. In FIG. 4, 90 is normalized shifter input data, 130 is a rounding circuit input, and 140 is a rounding circuit output.

In the above configuration, the increment circuit constituting the rounding circuit 14 has a data input terminal DIO, a data output terminal 000, and a control signal terminal σT. When all the normalized thick input data 90 are at the level "1", each AND circuit 21-1 to 21-N is "1".
Outputs 1゛. Therefore, each AND circuit 21-1 to 21-2
The output of the AND circuit 22 which inputs the output of 1-j is also "1".
'', and the output becomes the input of the control image @terminal σ of the increment circuit constituting the rounding circuit 14. Therefore,
Increment 1-operation is inhibited to prevent overflow.

The advantages of this embodiment are as follows.

(1) In conventional floating-point arithmetic circuits, rounding could not be performed during subtraction due to concerns about rounding overflow, but in this embodiment, the concern about rounding overflow has been resolved, so rounding can be performed during subtraction as well. I can do it.

(2) Overflow detection is performed by AND circuits 21-1 to 21
-N.

This can be realized using a simple circuit with only 22 connections.

(3) Since overflow detection can be performed in parallel with the normalization shift, the influence of the delay of the floating fault point arithmetic circuit l\ can be removed.

In addition, in the present invention, the overall configuration of the floating point arithmetic circuit, roughly speaking, the rounding circuit 14 and the rounding overflow detection circuit 20
It is possible to make various modifications to the circuit configuration other than that shown in the drawings.

(Effect of Bimei) As described above in detail, according to the present invention, since the rounding overflow detection circuit 20 is provided, overflow occurring in the rounding circuit during subtraction can be easily and accurately prevented.

[Brief explanation of drawings]

FIG. 1 is a configuration block diagram of a floating point arithmetic circuit showing an embodiment of the present invention, FIG. 2 is a configuration block diagram of a conventional floating point arithmetic circuit, and FIG. 3 is an explanatory diagram of rounding overflow in FIG. 2. FIG. 4 is a diagram showing an example of the configuration of the rounding circuit and rounding overflow detection circuit in FIG. 1. 8...ALU, 13...Normalization shifter, 14...Rounding circuit, 20...Rounding overflow detection circuit.

Claims (1)

[Claims] A circuit that performs arithmetic processing on floating point data whose N-bit mantissa is represented as a two's complement number by representing the mantissa with (N+1) bits or more, and a rounding circuit that rounds the mantissa to N bits when outputting the result of the operation by this circuit. A floating point arithmetic circuit comprising: a rounding overflow detection circuit that detects in advance overflow occurring in the rounding circuit based on the calculation results of the circuit and prohibits rounding processing in the rounding circuit. Features a floating point arithmetic circuit.