JPS62237582A - Histogram processor - Google Patents

Abstract

PURPOSE:To simplify access to a memory and to improve the processing speed of analysis by obtaining the optimum constitution of a histogram memory in accordance with its processing function and screen size. CONSTITUTION:When a system processor 3 consists of 16 bits e.g. and the maximum bit width of histogram memories 12, 13 are 24 bits, the histogram memories 12, 13 are constituted of 24 bits respectively by a conversion circuit for making the address and data on the system processor 1 side correspond to that of the histogram memory side. Consequently, one word in the memory can be accessed correspondingly to 2 words of the system processor 3. When the memories 12, 13 are constituted of 16 bits respectively in the same condition, one word of the histogram memory can be accessed correspondingly to one word of the system processor 3.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a histogram processor that calculates density frequency distribution, projection distribution, etc. of an image, and in particular, a histogram processor that flexibly adapts to changes in calculation functions and processing target screen size. The present invention relates to a configuration controllable histogram processor.

[Conventional technology]

The histogram processor is a processing function that executes calculations such as density frequency distribution and projection distribution.

Depending on the screen size to be processed, the bit size of the histogram memory for accumulating results and the table size are shown in Tables 1 and 2.
They differ as shown in the examples shown in the table.

Table 2 Projection distribution (accumulation of binary images on the X and Y axes) In this way, the data structure of the histogram memory changes depending on the processing target and function. I saw that the structure of Histogram 11 memory was fixed.

[Problem that the invention seeks to solve]

For example, the structure of the histogram memory is 16 bits x 256
If it is fixed to a word, data processing in this memory can be easily processed by a 16-bit microcomputer, but in order to obtain the density frequency distribution of an 8-bit image, the target image must be 256 x 256 pixels as shown in 1:A. be restricted by.

Furthermore, in order to eliminate such restrictions, if a 24-bit wide histogram 11 memory is used, for example, if the system processor is a 16-bit microcomputer, it will be necessary to access and analyze one 24-bit data in two operations. be. However, even if a window is applied and the screen size to be processed is set to 256×256 pixels, access will be performed in two operations, resulting in extremely inefficient access. As described above, the conventional fixed histogram memory configuration has the problem of having to restrict functions and screen size, or restrict analysis performance.

SUMMARY OF THE INVENTION An object of the present invention is to provide a histogram processor in which the configuration of a histogram memory can be optimally configured according to its processing function and double-sided size.

[Means for solving problems]

The purpose of the above is to create a register that controls the access method of the histogram memory from the system processor, and a conversion that associates the address and data on the system processor side with the address and data on the histogram memory side according to the contents set in this register. This is achieved by providing a circuit.

[Effect]

For example, if the system processor is 16 bits and the maximum bit width of the histogram memory is 24 bits, if the histogram memory is configured to 24 bits using the above method, one word of this memory will be accessed in association with two words of the system processor. Therefore, if the histogram memory is configured to have a 16-bit width under the same conditions, one word of the histogram memory will be accessed in association with one word of the system processor. In this way, the system processor can always access the hismilgram memory in an optimal configuration.

〔Example〕

The present invention will be explained below with reference to Examples. FIG. 1 is an overall system configuration diagram of an image processing apparatus using a histogram processor 1 of the present invention. The entire system is a general-purpose 16
It is controlled by a system processor 3 consisting of a bit microcomputer. Control commands and data are input and output via the system bus 4. In addition, an image memory and an image processor 2 are installed to store images input from an I'V camera, etc., and perform processing such as smoothing and edge enhancement on the images. F9 screen coordinate addresses X and Y are output. The histogram processor 1 uses these F', X, and Y information to perform calculations for extracting the density frequency distribution and projection distribution.
and system processor: 3 are not directly related to the present invention,
Moreover, since they are well known, detailed explanation thereof will be omitted.

The histogram processor 1 of the present invention is comprised in this embodiment of an interface circuit 11 with the system processor 3, a histogram memory 12.13 (each 12-bit x4 word), and an arithmetic unit 14.15. Arithmetic unit 14゜15 and histogram memory 12
．． The two sets of 13 modules operate independently, and can perform simultaneous parallel extraction processing of, for example, the X-axis projection distribution and the Y-axis projection distribution. Furthermore, it is also possible to use them as a combined set of 24-bit modules to perform extraction processing such as concentration frequency distribution that requires a bit width of 12 bits or more. These functions are performed by programming the arithmetic units 14-15.

As will be described later, this means that the calculation result W of any one of F, By setting the address to A, it is written.

Also, the data in histogram memory 12.13 is as follows.

It can be accessed from the system processor 3 via the interface circuit 11. That is.

The address from the system processor 3 is converted into an address AP according to the settings of the configuration control register 110, which is a feature of the present invention, and data RP or WP is read from or written to this address in the histogram memory 12.13. . The data RP and WP are also converted according to the settings of the configuration control register 110 and transferred to and from the system processor 3.

Figure 2 shows the configuration of the calculation units 14 and 15.
Each unit has the same configuration, and only the arithmetic unit 14 is shown in detail. What is its composition?

Selector 1.40. selects and outputs one of the image data F2 screen coordinate addresses X and Y as address A to the histogram memory 12.13. A selector 1 that selects one of F,
41. and an arithmetic circuit 142. Arithmetic circuit 142
The other calculation data is read data R from the histogram memory, and the calculation result becomes data W written to the same memory. From the arithmetic circuit 142 to the same circuit 15
A carry signal path CAR is provided to 2.
The configuration allows two arithmetic circuits to be combined. The selection command A S E L of the selector 140, the selection command DSEL of the selector 141, and the function command FUN of the arithmetic circuit 142 are the commands (FT number) from the configuration control register 110 in the interface circuit 11, and these are the commands FT from the system processor 3. It is determined by the settings, and various processes can be performed efficiently as described below depending on the contents.

Figure 3 shows the internal configuration of the histogram memory 12 (13 is the same), with 12 bits x 4 and word RAM 1.
20, a selector 121 for switching between address A and write data W from the arithmetic unit and address AP and write data WP from the interface circuit 11;
, 122. It further includes a table size limiter 123.

When the histogram processor is activated, the arithmetic unit side is selected by the FXRC signal and arithmetic operations are executed. Otherwise, the system processor 3 via the interface circuit 11 stores the histogram memory 12.13.
The read data R from the RAM 120 is commonly given to both the arithmetic unit and the interface circuit.

Now, the address A or A I) selected by the selector 21 is sent to the RA via the table size limiter 123.
Converted to M120 address. The table size limiter 123 is given a table size TS and a table number TNO.

Due to these signals, the 4-word RAM 120 is divided into several tables as illustrated in FIG. 4 (1) to (3), and the number of words contained in one table is the table size TS. , the number of the table is given by the table number TNO. For example, in the case of the density frequency distribution of 8-bit image data, the table size 'I'5 = 256 (words) as shown in Fig. 4(a), and in the case of the density frequency distribution of 9-bit image data, the table size is set to 256 (words). The table size TS may be set to 512 (words) as shown in Figure 4 (b). In addition, in the case of a projection distribution that processes a 256 x 256 pixel screen, TS = 256, the same < 4096 x
In the case of 40 o 6 pixels, T S as shown in Figure 4 (c)
=4096 (no division at this time).

When the RAM is divided in this way, which table is accessed is table number TNO=40°#1. ...,
#i, . . . from which the start address of the table is determined. Therefore, in case (a), the address is an 8-bit address that specifies one of the 256 words, (
In the case of b), it becomes a 9-bit address that specifies one of 512 words when accessed from the system processor 3.

This has the advantage of simplifying address calculation. Further, when the image to be processed has a limited screen, it is no longer necessary to map all four word address spaces of the histogram memory to the system processor 3. This means that, for example, when a histogram processor is integrated into an LSI, it is not known what kind of image processing device it will be incorporated into, but it can be used as an optimal configuration depending on the application.

FIG. 5 shows an interface circuit 1-1 that controls input/output between the system processor 3 and the histogram processor.
This shows an example of the configuration. The interface circuit 11 is provided with a configuration control register 11o that can be set by the system processor 3, and the system processor 3 can program the configuration control register 11o to create an arithmetic unit.

The operation of the histogram memory and the interface circuit itself can be defined. That is, ASIEL, DSBl, and FUN shown in the first two lines of the register 110 in FIG. 5 are control circuits for the selector and arithmetic circuit in the arithmetic unit 1-14. EXIEC, T
S, TNO controls the histogram memory in Figure 3;
It is 4%.

Furthermore, the nth AMID in the register 110 is a control command that defines the bit width of one word and the addressing method when the system processor 3 accesses the histogram memory. and 42 are address conversion circuits 31. and 42, respectively.
The data is converted by the data conversion circuit z3.2 and becomes the address conversion circuit read/write data RP/WP to the histogram memory 12.13.For example, an example of the mode when A M OD is 2 bits is as follows. .

(b) 12-bit single address (AMOD=OO) Effective access when each histogram memory 12.13 stores each projection image of X and Y@, for example, XM and Y axis projection distribution. mode. Figure 6 (a)
Addresses O to 4095 are histogram memory 1 as shown in
2, addresses 4096 to 8191 are allocated to the histogram memory 13, and both memories 12 and 13 can be accessed independently by specifying these addresses.

(b) 12-bit alternate address (AMOD=01)
Like X, Y$fi extraction, histogram memory 12.
This is an effective access mode when a pair of data is stored in 13 identical addresses. Addresses 0, 1, . . . of the histogram memory 12 as shown in FIG. 6(b). ... (the entries are XO, Xl, ...) are the access addresses 0, 2, . ..., histogram memory]3 address o, 1. ...(That entry is YO, YIT...)
is assigned to the access address 1.3°...
Consecutive addresses (2j.

2j+1), the pair of data (X,.

YJ) can be read/written.

(c) 1.6 bit l-711X (AMOD= 10
) Like density frequency distribution, histogram 11 memory 12.
In the access mode that is valid when 13 are connected, ],
In the case of 6-bit access, the address is assigned to the 16th
It is the same as figure (b). However, system processor 3:1
The lower 12 bits of the 6-bit data are stored in x4 of the histogram memory 12, and the higher 4 bits are stored in Yj of the histogram memory 13. The top 8 bits of YJ are left over.

If you use this to prevent overflow, 512 x 51
It can also be used when there is a possibility that the data may overflow the 16-bit range, such as the density frequency distribution of a two-pixel screen.

〔Effect of the invention〕

As is clear from the above embodiments, according to the present invention, the histogram memory can be configured optimally according to the processing content and double-sided size, so access to this memory is simplified, and analysis processing is simplified. This has the effect of improving speed.

[Brief explanation of drawings]

FIG. 1 is an overall configuration diagram of a system showing an embodiment of the present invention, and FIG. 2 is a circuit configuration diagram of an arithmetic unit. Figure 3 is a diagram of the circuit configuration of the histogram memory, Figure 4 is an explanatory diagram of the table configuration of the histogram memory, Figure 5 is a diagram of the configuration of the interface circuit, and Figure 6 is a diagram showing examples of memory configurations for various processes. be. 1... Histogram processor, 2... Image memory and image processor, 3... System processor. 11... Interface circuit, 12.13... Histogram memory, 14.15... Arithmetic unit.

Claims (1)

[Claims] 1. A histogram processor consisting of an arithmetic unit that processes data on an image memory and calculates histograms such as density frequency distribution and projection distribution, a histogram memory that stores the arithmetic results of the arithmetic unit, and an interface circuit with a host processor. In the interface circuit, a register for configuration control and an address and data conversion circuit whose operation is determined according to the control command set in the register are provided, and the control command is sent from the upper processor to the register. By setting the address and data on the upper processor side and the address and data on the histogram memory side, the conversion process by the conversion circuit described above is made to correspond, thus creating a histogram memory configuration according to the type of histogram operation and the size of the image to be processed. A histogram processor characterized in that it has a structure that allows it to perform operations.