JPS6223158Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a step waveform signal step reduction circuit that reduces steps in a step waveform signal obtained by a sample and hold circuit, and relates to a step waveform signal step reduction circuit that can be used in a stereo demodulation circuit of an FM tuner, etc.

For example, in a stereo demodulation circuit of an FM tuner, especially a sampling-and-hold type stereo demodulation circuit, the sample-and-hold left and right channel signals have a staircase waveform, and the carrier signal is generated by multiplying the input signal and the sampling pulse. There was a problem that sideband components of the signal were generated.

The present invention has been made in view of the above, and an object of the present invention is to provide a step waveform signal level difference reduction circuit that can be used in a stereo demodulation circuit to alleviate the above-mentioned problems.

The present invention will be explained below with reference to examples.

FIG. 1 is a block diagram of one embodiment of the present invention.

In FIG. 1, 1 is an input terminal to which an input signal is applied, and 2, 7, and 11 are buffer amplifiers with a high slew rate, high input impedance, and low output impedance. 3 is 180 each
This is a two-phase pulse oscillator that generates two sampling pulse trains with a phase difference of 180 degrees. For example, when used as a stereo demodulation circuit, it is phase synchronized with the pilot signal included in the input composite signal, and generates one pulse train with a phase difference of 180 degrees. Generates a paired pulse train. 4 and 8 are switch circuits consisting of CMOS analog switches or field effect transistors, and the switch circuit 4 is a two-phase pulse oscillator 3.
The switch circuit 8 is turned on and off by the sampling pulse of the first sampling pulse train whose phase is advanced and output from the two-phase pulse oscillator 3, and the switch circuit 8 is turned on and off by the sampling pulse of the second sampling pulse train whose phase is delayed and which is output from the two-phase pulse oscillator 3. It will be turned off. The switch circuit 4 together with the capacitor 5 constitutes a staircase wave generation circuit 6 which is a sample and hold circuit that samples and holds an input signal and converts it into a staircase waveform signal whose amplitude changes at regular time intervals. The switch circuit 8 together with the capacitor 9 constitutes a delay circuit 10 which is a sample and hold circuit that samples and holds the staircase waveform signal outputted from the staircase wave generation circuit 6 input through the buffer amplifier 7 and delays it. 12
is an adder which outputs the output signal of the staircase wave generation circuit 6 which has passed through the buffer amplifier 7 and the buffer amplifier 1.
1 and the output signal of the delay circuit 10 is added and output.

The operation of the present embodiment configured as described above will be explained by taking as an example the case where the present embodiment is applied to a sampling-and-hold type stereo demodulation circuit.

The input signal source is converted into a low impedance signal source by the buffer amplifier 2, and the FM composite signal shown in FIG. 2a is input to the staircase wave generation circuit 6 via the buffer amplifier 2. In FIG. 2a, the solid line shows the waveform of the suppressed subcarrier of 38 KHz, the broken line shows one channel component of the stereo audio component, and the dashed line shows the other channel component.

The two-phase pulse oscillator 3 is phase synchronized with the pilot signal included in the input signal, that is, the FM composite signal, and generates the first sampling pulse train shown in FIG. 2b for separating the left channel signal from the FM composite signal, and the right channel signal. 38K with a mutual phase difference of 180 degrees with the second sampling pulse train shown in Figure 2c for separating the signals.
Outputs a pair of Hz sampling pulse trains.

It is assumed that the switch circuits 4 and 8 are turned on when the applied sampling pulse is at a high potential, and turned off when the applied sampling pulse is at a low potential.

Therefore, the switch circuit 4 is applied with the sampling pulses shown in FIG. charged to the level of When the sampling pulse becomes a low potential, the switch circuit 4 is turned off. However, the buffer amplifier 7 connected to the output terminal of the staircase wave generation circuit 6 has a high input impedance, and the buffer amplifier 7 is connected to the output terminal of the staircase wave generation circuit 6.
Since the buffer amplifier 2 and the switch circuit 4 are disconnected from each other, the charge stored in the capacitor 5 at the time when the switch circuit 4 is turned off is held as it is until the next sampling pulse becomes a high potential, and the potential of the capacitor 5 is The signal is transmitted to the subsequent stage via the buffer amplifier 7. In this case, the purpose is to separate the left and right channel signals from the FM composite signal, so the switch circuit 4 is turned on and off.
Although the width of the sampling pulse to be turned off is narrow and the off period is long, as described above, the potential of the capacitor 5 is maintained during the off period, and the output of the staircase wave generation circuit 6 becomes the staircase waveform signal shown in FIG. 2d. This staircase waveform is the same as the output waveform of a sample-and-hold circuit in a sampling-and-hold type stereo demodulation circuit.

The output of the staircase wave generating circuit 6 shown in FIG. 2d is applied to a delay circuit 10 through a puff amplifier 7. The buffer amplifier 7 converts the potential of the capacitor 5 into a low output impedance signal source as an input signal. On the other hand, the switch circuit 8 is turned on and off by the sampling pulse of the second sampling pulse train, that is, the sampling pulse shown in FIG. 2c. Therefore, the capacitor 9 is as shown in Fig. 2c.
2nd at the time of generation of the sampling pulse shown in
The capacitor 9 is charged to the potential of the staircase waveform signal shown in FIG. 2D, and the potential of the capacitor 9 becomes the potential of the staircase waveform signal shown in FIG. However, since the sampling pulse in FIG. 2c has a phase delay of 180 degrees with respect to the sampling pulse in FIG. 2b, the output signal of the delay circuit 10 is as shown in FIG. The staircase waveform signal shown in FIG. 2d is delayed by 1/2 period of the amplitude change period of the staircase waveform signal shown in FIG. 2, that is, 1/2 period of the sampling pulse period.

Further, during this delay, when the switch circuit 8 is off and the capacitor 9 holds charge, the buffer amplifier 11 has a high input impedance, so the charge in the capacitor 9 is not reduced, and the charge in the capacitor 9 is not reduced. When the staircase wave signal applied as an input signal at the time of generation of the applied sampling pulse is lower than the potential at the time of generation of the immediately preceding sampling pulse, the electric charge of the capacitor 9 is transferred to the buffer amplifier 7 through the switch circuit 8.
will be sucked into. Therefore, even if the width of the sampling pulse is narrow, if the on-resistance of the switch circuit 8 is small, the input impedance of the buffer amplifier 7 is high and the output impedance is low, so that the capacitor 9 can be completely charged to the potential of the input staircase waveform signal. In addition, the electric charge in the capacitor 9 can be discharged, and even if the staircase waveform signal applied to the delay circuit 10 is a staircase waveform with steep rises and falls, the waveform of the delayed staircase waveform signal will collapse. be delayed without any delay.

Therefore, the staircase waveform signal shown in FIG. 2d from the staircase wave generation circuit 6 and the staircase waveform signal shown in FIG.
and 11 separately and are added by an adder 12. Therefore, the output signal from adder 12 is
As shown in FIG. f, the step waveform signal becomes a staircase waveform signal with reduced steps.

Therefore, the subcarrier included in the output staircase waveform signal
The 38KHz double sidebands are as shown by curves C and D in Figure 3, and are 30 dB lower than the double sidebands of the conventional sampling-and-hold stereo demodulation circuit shown by curves E and F in Figure 3 at a modulation frequency of 1KHz. or more.

As explained above, according to the present invention, it is possible to reduce the step difference in the staircase waveform signal obtained by sample-holding the input signal, and when used as a stereo demodulation circuit, the sideband of the carrier signal can be reduced. It will be done.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention. Second
Figures a to f are waveform diagrams for explaining the operation of an embodiment of the present invention. FIG. 3 is a characteristic diagram showing the amount of carrier sideband included in the output staircase waveform signal when one embodiment of the present invention is used as a stereo demodulation circuit. 2, 7 and 11... buffer amplifier, 3...
2-phase pulse oscillator, 4 and 8...switch circuit, 6... staircase wave generation circuit consisting of a sample and hold circuit, 10... delay circuit consisting of a sample and hold circuit, 12... adder.

Claims (1)

[Scope of utility model registration request] a staircase wave generation circuit that samples and holds an input signal using a sampling pulse of a constant period and converts it into a staircase waveform signal; and a delay circuit that delays the output staircase waveform signal of the staircase waveform signal by 1/2 period of the sampling pulse. , an adder that adds and outputs the output staircase waveform signal of the staircase wave signal generation circuit and the output staircase waveform signal of the delay circuit.