JPH0421386B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a video clamp circuit that can be applied to a satellite broadcast receiving device using the SHF band.

In the satellite broadcasting system, frequency modulation is performed on the television signal, but in this case it is undesirable if carrier wave energy concentrates. For example, if the television signal has a black level, the carrier wave energy will be concentrated at a frequency corresponding to the black level.
When the concentration of carrier wave energy is large in this way,
When amplifying multiple FM waves, the nonlinearity of the amplifier tends to cause cross-modulation and cause interference to adjacent channels. For this reason, a symmetrical triangular wave (energy spread signal) with a uniform distribution of carrier wave energy within the frequency shift is superimposed on the television signal, and FM modulation is performed to spread the carrier wave energy.
Therefore, on the receiving device side, after demodulating the FM television signal, it is necessary to remove the spread signal and restore the original television signal. Conventionally, there is a circuit shown by a in FIG. 1 as a video clamp circuit for removing a spread signal. Let the voltage on the input side be ei and the voltage on the output side be eo. A capacitor C, a diode D, and a battery with a voltage VR are inserted between the input side and the output side. When a signal in which a _spread signal is superimposed on a television signal as shown in _FIG . , its output side is constant at battery voltage VR. time is t ₂
During _t3 , the diode D is in a non-conducting state and the electric charge charged in the capacitor C is not discharged because the diode D is in the opposite direction. Therefore, the amount of change in the voltage ei on the input side becomes the amount of change in the voltage eo on the output side from VR. Again, between times t ₃ and t ₄ diode D becomes conductive for a short period and the output is clamped to voltage VR. Thereafter, the spread signal is removed by repeating the same process and clamping the peak value of the synchronization signal to a constant level of the voltage VR. However, in such a video clamp circuit, when a TV signal in which an audio signal is superimposed on the horizontal synchronization signal of the TV signal is sent, the audio signal is separated from the TV signal of the satellite broadcast receiver. Since the spread signal is removed by the video clamp circuit beforehand, the following disadvantages arise. In a video clamp circuit that clamps at the peak value of the synchronization signal, there is always a slice level, and if an audio code pulse is superimposed on the horizontal synchronization signal, the audio code pulse will be sliced and distortion will occur in the audio signal. A possible drawback is that the clamp level varies depending on the content of the audio code pulse.

The present invention has been proposed to eliminate such drawbacks, and provides a video clamp circuit that does not distort the audio signal by applying a clamp at a point other than the peak value of the synchronization signal and does not cause fluctuations in the clamp level. With the goal.

The feature is that the separated synchronization signals are integrated and a predetermined threshold value is used to generate a delayed pulse of the horizontal synchronization signal, a delay pulse of the equivalent pulse of the vertical synchronization signal, and a pulse that includes the adjacent notch pulses of the vertical synchronization signal. generates a pulse train consisting of
Block that pulse train with a synchronization signal, create a clamp pulse synchronized with its leading edge from its output,
Clamps are applied at the pedestal level of the back porch portion immediately after the trailing edge of the horizontal synchronizing signal, immediately after the trailing edge of the equivalent pulse, and the cut pulse portion.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 shows a television signal in which a spread signal is superimposed on the television signal input to the video clamp circuit of the present invention. 1' is a horizontal synchronizing signal, and the audio code pulse 2 is superimposed on that portion. The triangular wave of the spread signal is 3, and a vertical synchronization signal (not shown) is present at its bending point 3'. 4 is a back porch (back porch of horizontal sync signal portion) delayed by the horizontal synchronizing signal, 5 is a pedestal level, and 1 is a television signal.

FIG. 3 is a block diagram of the video clamp circuit of the present invention. The input point of the video clamp circuit is ₁ point S, and here the input is branched into two, one is the output side _S10 via the clamping capacitor _C1 , and the input side S10 of the field effect transistor _Tr2 with ₁₁ points. reach. The other one reaches the inversion circuit 7 via the synchronous separation circuit 6, which is synchronous separation means. The inverting circuit 7 is further connected to an inverting circuit 8 that inverts the output signal of the inverting circuit 7, and is further connected to an inverting shaping circuit 10 which is a waveform shaping means via an integrating circuit 9 which is an integrating means. The outputs of the inverting shaping circuit 10 and the inverting circuit 7 are input to a gate circuit 11 which is a gate means, and the outputs are inputted to the inverting circuit 7.
The gate circuit 11 is closed in the synchronizing signal portion by the output of , and a clamping pulse is output. The clamping pulse outputted from the gate circuit 11 is inputted to a differentiating circuit 12 for time adjustment, and its output is inputted to a shaping circuit 13 to obtain a clamping pulse.
Here, the differentiating circuit 12 and the shaping circuit 13 correspond to clamp pulse forming means. The circuit that generates the clamp pulse through the circuit from the sync separation circuit 6 to the shaping circuit 13 in this way is called a clamp pulse generation circuit. The output of the shaping circuit 13 is input to the base of the clamping transistor Tr ₁₁ , and the emitter side of the clamping transistor Tr ₁₁ is connected to a clamp voltage circuit composed of resistors R ₁ and R ₂ and a capacitor C ₂ with one side grounded. be done. The collector side of the clamping transistor _Tr11 is connected to the _S10 point mentioned above. The portion of the video clamp circuit described above excluding the clamp pulse generation circuit is referred to as a clamp circuit 14.

FIG. 4 is a drawing of an embodiment of a detailed circuit that further embodies the block diagram of FIG. 3. On the input side, there is an emitter follower circuit consisting of transistor Tr ₁ and resistor R ₃ . This circuit is included to reduce the impedance of the signal source to a low impedance since if the impedance of the signal source applied to the video clamp circuit is large, the output waveform will be distorted. The emitter side of transistor _Tr1 is point _S1 . One side is connected to capacitor C ₁ , the other is connected to capacitor C ₃ through a low pass filter (LPF),
It is connected to a synchronous separation circuit 6 composed of resistors R ₄ , R ₅ , R ₆ and a transistor Tr ₃ . Its output is connected to capacitor C ₄ , capacitor C ₄ , resistor
R ₇ , R ₈ , R ₉ and the transistor Tr ₄ constitute an inverting circuit 7. One of the outputs of the transistor Tr ₄ is input to the capacitor C ₅ of the inverting circuit 8 consisting of the capacitor C ₅ , resistors R ₁₀ , R ₁₁ , R ₁₂ and the transistor Tr ₅ , and the other is input to the capacitor C ₉ and the resistor R ₁₈ ，
It is input to the capacitor _C9 of the gate circuit 11 which is composed of _R19 , _R20 and the transistor _Tr8 . The output of the inverting circuit 8, ie, the collector side of the transistor _Tr5 , is connected to the resistor _R13 of the integrating circuit 9, which includes resistors _R13 , _R29 and capacitors _C6 , _C7 . The output of the integrating circuit 9 is connected to the capacitor C ₈ , resistors R ₁₄ , R ₁₅ ,
It is input to the capacitor _C8 of the inverting shaping circuit 10, which includes an inverting circuit composed of _R16 and a transistor _Tr6 , and an emitter follower circuit composed of a resistor _R17 and a transistor _Tr7 . Inversion shaping circuit 1
0, that is, the emitter side of the transistor Tr ₇ is input to the resistor R ₂₀ of the gate circuit 11. The output of the gate circuit 11, that is, the collector side of the transistor Tr ₈ , is connected to the capacitor C ₁₀ of the differentiating circuit 12, which is composed of a capacitor C ₁₀ and a resistor R ₂₁ , and the output is connected to the capacitor C ₁₁ , resistors R ₂₂ , R ₂₃ , _R24 ,
It is input to the capacitor C ₁₁ of the shaping circuit 13 consisting of R ₂₅ , R ₂₆ and transistors Tr ₉ and Tr ₁₀ and resists
A clamp pulse is output via _R26 . The rest is the same as the wiring explained in the block diagram of FIG. 3, so a description thereof will be omitted. The voltage waveform in FIG. 5 shows the voltage waveform at each point S ₁ to S ₉ shown in FIGS. 3 and 4. Here, the audio pulse code and video signal superimposed on the horizontal synchronization signal are omitted for simplicity.

Next, the operation of the present invention will be explained in detail with reference to the drawings from FIG. 1 to FIG. 5. A brief explanation of the present invention will be given in comparison with a conventional example. Comparing the block diagrams of the conventional example in FIG. 1a and the embodiment of the present invention in FIG.
are the capacitor C ₁ and transistor in Fig. 3, respectively.
Corresponding to Tr ₁₁ , the battery with voltage VR in Figure 1a is the third
This corresponds to the clamp voltage generation circuit consisting of resistors R ₁ and R ₂ and capacitor C ₂ shown in the figure. In the conventional example, clamping is performed at a peak value, but in the present invention, clamping is performed using a clamp pulse generated by a clamp pulse generation circuit. As shown in Fig. 2, the TV signal in which the spread signal is superimposed on the TV signal is Tr ₁ in Fig. 4.
input to the base side of the Therefore, the signal waveform at the _S1 point is also similar to that shown in FIG. S The signal waveforms of the horizontal synchronization signal and vertical synchronization signal of _one point TV signal are shown in Figure 5.
Denoted by S ₁ . Here, X is the horizontal synchronization signal part, Y
is called the vertical synchronization signal part. However, the vertical synchronization signal portion is shown in a simplified manner. To reduce waveform distortion, capacitor C ₁ is added from the emitter follower circuit of Tr ₁ to the clamp circuit of clamp transistor Tr ₁₁ . The output of the transistor Tr ₁ is input to the sync separation circuit 6 comprising the transistor Tr ₃ and the like through a low-pass filter to remove unnecessary noise and separate only the sync signal. This circuit produces a signal waveform in which the peak value of the horizontal synchronizing signal and the signal component of the vertical synchronizing signal higher than the pedestal are output at a low level. This signal waveform is shown in Figure 5.
Indicated by S ₂ . When the signal synchronously separated by the synchronous separating circuit 6 is input to the inverting circuit 7 composed of a transistor _Tr4 and the like and its polarity is inverted, the signal waveform becomes as shown by _S3 in FIG. The signal output by the inverting circuit 7 is divided into two parts, one is input to the capacitor C ₉ connected to the base side of the transistor Tr ₈ of the gate circuit 11, and the other is input to the transistor Tr ₅ etc. When the signal is input to the constructed inverting circuit 8 and the polarity is inverted, the output becomes a signal waveform like _S4 in FIG. When this signal is input to the integrator circuit 9, it becomes a signal waveform as shown by _S5 in FIG.
The output of 0 has a signal waveform as shown by _S6 in FIG. This output is input to a gate circuit composed of transistor _Tr8 and the like. Now, assuming that the high level of the pulse is high level and the low level is low level, when the signal from inverting circuit 7 is at high level, current flows between the base and emitter of transistor Tr ₈ , so that the collector and emitter are conductive. Since the state is reached, the output of _{the 7} points of gate circuit S becomes low level. Inversion circuit 7
When the input signal from the transistor _Tr8 is at a low level, there is no conduction between the collector and the emitter of the transistor Tr8, so the output of the inverting shaping circuit 10 becomes the output of the gate circuit, that is, the output of the _S7 point. Therefore, the output of the gate circuit has a signal waveform of a clamping pulse as shown by _S7 in FIG. The threshold value of the output of the integrating circuit 9 is set in the part including the cut pulse and the pedestal of the equivalent pulse in the vertical synchronizing signal part Y so that the threshold value is applied to the part of the back porch delayed by the horizontal synchronizing signal (the back porch of the horizontal synchronizing signal part X). Therefore, the pulse of the signal output from the inverting shaping circuit 10 is divided into the vertical synchronizing signal portion Y so that the pulse of the signal output from the inverting shaping circuit 10 partially includes the back porch delayed by the horizontal synchronizing signal.
Then, the cutting pulse and the equivalent pulse are output at the same timing so as to partially include the pedestal. Therefore, the output of the gate circuit is outputted to the back porch portion delayed by the horizontal synchronizing signal, in timing with the cut pulse of the vertical synchronizing signal portion Y and the pedestal of the equivalent pulse. However, the timing of the cutting pulse of the vertical synchronizing signal portion Y is slightly delayed due to the switching time of the transistor, etc., and the clamp is tightened from the pedestal of the vertical synchronizing signal portion Y to the peak value of the synchronizing signal. Vertical sync signal is distorted. In order to obtain a clamp pulse that falls within the cutting pulse period of the vertical synchronization signal portion Y, the output of the gate circuit 11 is input to the differentiating circuit 12, the threshold value is appropriately determined by the transistor Tr ₉ of the shaping circuit 13, and the transistors Tr ₉ and Tr are input. When waveform shaping is performed in _{step 10} , S ₉ in Figure 5
The clamp pulse shown is obtained. Note that S ₈ in FIG. 5 indicates the waveform output from the differentiating circuit 12, and the horizontal dotted line indicates the threshold value of the shaping circuit 13. When the clamp level is set by a clamp voltage circuit consisting of a capacitor C ₂ and resistors R ₁ and R ₂ and a clamp pulse is applied to the base side of the transistor Tr ₁₁ , the horizontal sync signal portion X is delayed to the horizontal sync signal. Vertical synchronization signal part Y on the back pouch
Then, the clamp pulse at the pedestal of the cutting pulse and the equivalent pulse brings conduction between the collector and emitter of the clamping transistor _Tr11 , and the clamp is applied to the set level, so that the spread signal is removed. In addition, in order to maintain a high resistance between the collector and emitter of the clamping transistor Tr ₁₁ during non-conduction and to ensure accurate operation of the clamp circuit, a MOS type with high input impedance is used.
The spread signal removal efficiency is increased by receiving FET and Tr ₂ .

As described above, the present invention eliminates the spread signal by clamping the back porch portion immediately after the trailing edge of the horizontal synchronizing signal, immediately after the trailing edge of the equivalent pulse, and the notch pulse portion at the pedestal level. This has the effect that the audio code pulse superimposed on the signal is not damaged and the clamp level does not fluctuate.

[Brief explanation of drawings]

Figure 1 is a circuit diagram and signal waveform diagram of a conventional video clamp circuit, Figure 2 is a signal waveform diagram in which a spread signal is superimposed on a television signal, and Figure 3 is a block diagram of an embodiment of the video clamp circuit of the present invention. FIG. 4 is a more detailed circuit diagram of an embodiment of FIG. 3, and FIG. 5 is a signal waveform diagram of the video clamp circuit of the present invention. 1; TV signal, 1'; horizontal synchronization signal, 3; spread signal, 4; back porch, 5; pedestal level, 6, 7, 8, 9, 10, 11, 12, 13;
Clamp pulse generation circuit, 14; Clamp circuit,
X: Horizontal synchronization signal part, Y: Vertical synchronization signal part.

Claims (1)

[Claims] 1. In a circuit for removing a spread signal of a television signal in which a spread signal is superimposed on the television signal, a sync separation means for separating a sync signal from the television signal, and an integral for integrating the sync signal separated by the sync separation means. generating a pulse train consisting of a delayed pulse of a horizontal synchronizing signal, a delayed pulse of an equivalent pulse of a vertical synchronizing signal, and a pulse including mutually adjacent notch pulses of the vertical synchronizing signal by using the output of the integrating means with a predetermined threshold; a waveform shaping means for generating a clamp pulse by closing a gate on the pulse train using the output of the synchronization separating means; and a clamp pulse forming means for generating a clamp pulse in synchronization with a leading edge of the clamp pulse. and a clamp circuit that clamps the television signal at a pedestal level in response to a clamp pulse from the clamp pulse generation circuit.