JPS62229966A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE: To make the testing process easier while cutting down the testing time by a method wherein an overall circuit as an LSI system is divided into multiple circuit blocks fulfilling the testing functions and simultaneously provided with a test mode generating part to control respective circuit blocks. CONSTITUTION:An overall circuit is divided into multiple circuit blocks 64-67 fulfilling the testing functions and simultaneously provided with a test mode generating part 68 to control the respective circuit blocks. The test mode generating part 68 is provided with a change-over circuit to change-over and select any input signals from outside of blocks in said respective circuit blocks 64-67 and any test input signals transmitted from inside of blocks for feeding them to inner circuits as well as a comparison circuit to compare any output signals from said inner circuits with any signals to be tested transmitted from the inner blocks so that the resultant comparison signals from the comparison circuit may be outputted to outside of blocks for simultaneously testing respective circuit blocks during the testing process. Furthermore, the respective circuit blocks 64-67 can receive control signals BCON l-BCON n from the circuit block through the test mode generating part 68 so that the respective circuit blocks 64-67 may be tested independently.

Description

Detailed Description of the Invention [Object of the Invention] (Industrial Application Field) The present invention is directed to a custom LSI. Standard cell LSI.
The present invention relates to semiconductor integrated circuits such as gate arrays, and particularly to integrated circuits whose internal circuits are divided into a plurality of blocks so that testing thereof can be easily performed.

(Prior Art) As LSIs become more highly integrated, the problem of test 1 of LSIs becomes more serious. If no consideration is given to the test, test 1 will be performed by sending and receiving signals from the external terminals of the LSI, which will require a large amount of test time and test series, and in severe cases, the test may not be possible. It can occur.

LSI test 1 methods include LSSD, self test.
There is a circuit division method. LSSD is l-evelSen
It is an abbreviation for sitive scan design, and has a structure in which internal memory circuits are connected in series so that the state can be read and captured from the outside, and tests can be performed as a combinational circuit.

As for self-testing, the mainstream method is to incorporate a pseudo-random pattern generator and a device for compressing output signals using a certain rule inside the LSI, and inspect a response string of one output signal during testing.

In the circuit division method, the inside of an LSI is divided into several blocks, and each block is tested at the time of testing.

When LSSD@ is applied, as the internal storage circuits increase, the time for serially inputting and outputting data in order to control them from external serial input/output terminals occupies most of the test time, and the test time increases.

For example, the number of internal memory circuits is N, the number of required test series steps is n, and the test time for one step is 11.

If the serial input/output time is [2], the total test time T is T=n (2N t2+tl), and as N increases, it becomes enormous compared to the essential test time ntl.

Self-Nath 1 method uses a built-in pseudo-random pattern generator to generate a test sequence.As circuits become highly integrated, pattern generators can generate a huge number of tests!・Patterns must be generated, making them large, making them unsuitable for practical use, and increasing test time.

When the circuit division method is applied, the test time is Mt, where M1 is the number of divided blocks and t is the average test time, and is generally shorter than when not divided. However, since the external terminals of the LSI must be used for testing eventually, the LSI is limited by the number of external terminals and cannot be divided into blocks having more input/output signals than the number of external terminals.

(Problems to be Solved by the Invention) The present invention has been made to solve the above-mentioned problems such as long test times, large number of test sequences, and large restrictions on block division. , a semiconductor that can suppress the increase in test time, easily generate test sequences, requires fewer test terminals in divided blocks, and has fewer restrictions on block division! The purpose of this invention is to provide an I product circuit.

[Structure of the Invention] (Means for Solving the Problems) The semiconductor integrated circuit of the present invention is divided into a plurality of circuit blocks each having the ability to test the entire circuit, and a test for controlling each circuit block. A mode generation section is provided, and in each of the circuit blocks, a switching circuit is provided for switching and selecting an input signal from outside the block and a test input signal generated inside the block and supplying the selected signal to the internal circuit,
In addition, a comparison circuit is provided to compare the output signal from the internal circuit and the test expected signal generated inside the block.The comparison result signal of the comparison circuit is configured to be output to the outside of the block. It is characterized by being able to test both at the same time.

(Function) During the performance test, in each circuit block, the input side selects a test input signal and inputs it to each internal circuit, and the output side compares the output signal of each internal circuit with the test expected signal. By calculating the logical sum of each comparison result signal, it becomes possible to easily observe whether the test result of each circuit block is good or bad. In this case, since each circuit block is tested at the same time, the test time is approximately determined by the maximum test time of the circuit block, so the test time can be shortened. In addition, in order to test each circuit block, it is only necessary to add a few terminals in addition to the output terminals, such as for input switching, output switching, and comparison result signal output, so there are fewer restrictions on circuit division. . Furthermore, test patterns can be easily generated by selecting the scale of the circuit block.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

In the LSI shown in FIG. 1, 64 to 67 are circuit blocks in which a circuit as an LSI system is divided into a plurality of parts;
68 is a test mode generator, and 69 to 71 are a plurality of external input terminals, each of which has a corresponding input buffer. 51
-53 to the signal input terminals of each circuit block 64-67. Reference numerals 72 to 74 denote a plurality of external output terminals, to which the output terminals of output buffers 754 to 56 are respectively connected, and the output buffers 754 to 56 are wired to the signal output terminals of each circuit block 64 to 67. ing.

75 is an external input terminal for the clock 1 signal CLOCK1 for controlling the test signal generation timing, and the CLOCK signal of each circuit block 64 to 67 is input via an input buffer 757.
Connected to the 1 input terminal. However, as described later, the CLOCK1 input terminal and CLOCKI output terminal of each circuit block are directly connected, so the CLOCK1 input terminal and CLOCKI output terminal of each circuit block are directly connected.
The CKI output terminal and the CLOCK1 input terminal of another circuit block may be connected. 76 is an external input terminal for the clock 2 signal CLOCK2 for serial output synchronization, and is connected to the CLO of each circuit block 64 to 67 via an input buffer 758
Connected to the CK2 input terminal. In this case, the CLO
CLOCK of one circuit block as well as CK1 manual
2 output terminal and the CLOCK 2 input terminal of another circuit block may be connected. 77 is the system reset signal RESET
It is an external input terminal for the test mode generator 68 and the RES of each circuit block via the input buffer 59.
Connected to the ET input terminal. Since this RESET input terminal is also connected to the RESET output terminal within the circuit block as described later, it may be connected to the RESET output terminal of another circuit block. Reference numerals 78 and 79 are external input terminals for test mode generator control signals C0NT1 and C0NT2, which are respectively connected to the D1 and D1 generators 68 via input buffers 60 and 61, respectively. 80 is an external output terminal for circuit block test result output CHECKI, and 81 is an external output terminal for serial output CHECK2 for input inspection.

In the circuit of FIG. 1, only four circuit blocks 64 to 67 are shown to simplify the illustration, but
Generally, there are n blocks.

Then, the circuit block 64 is a first circuit block, the circuit block 65 is a first circuit block, and the circuit block 66 is a first circuit block.
If we distinguish the circuit block Jl+1> as the circuit block and the circuit block 67 as the n-th circuit block (however, in the timing diagram of FIG. 5, they are indicated as blocks 1 to n), then the CHECK1 signal and the CHECK2 The signals are connected in order from the first circuit block 64 to the n-th circuit block 67. In this case, the input terminals of CHECKl and CHECK2 of the first circuit block 64 are not wired anywhere. , the above CI-IECKI
The input terminal is grounded, and the CHECK2 input terminal may be connected to an external input terminal, may be connected to a power supply, or may be grounded as shown. The CHECK1 input terminal of the n-th circuit block 67 is connected to the CHECK1 output terminal of the (f+1)th circuit block 66 by a dotted line because the CHECK1 input terminal of the n-th circuit block 67 is connected to the CHECK1 output terminal of the (f+1)th circuit block 66 by a dotted line. This means that the CHECKI output terminal of the (f+1)th circuit block 66 is connected to the CHECK1 input terminal of the circuit block 66. In the figure, connections between circuit blocks for other signals are indicated by dotted lines, which have the same meaning as described above. Then, C of the n-th circuit block 67
The HECKI output terminal and the CHECK2 output terminal are connected to the external output terminal 80 for CHECK1 and the external output terminal 81 for CI-(ECK2) via output buffers 62 and 63, respectively.
It is connected to the.

FIG. 2 shows a specific example of the test mode generator 68 in FIG. 1, and 155 is the input buffer 60 in FIG.
is connected to the C0NTl input terminal, into which a clock signal for the test mode generation counter 152 is input.

154 is C0 to which the input buffer 61 in FIG. 1 is connected.
N72 input terminal, and is connected to the mode control signal MODE3 output terminal 157 via the buffer 153.

156 is an RE to which the input buffer 59 in FIG. 1 is connected.
SET input terminal, RES for the counter 152
ET signal is input. Counter outputs Q1 to Qx of the counter 152 are input to a decoder 151, which outputs the block control signals -coN1. BOCON
2. . . . BOCONn is connected to output terminals 160, 161 .・
162, the mode control signal MODE1゜MO
DE2 is output from output terminals 158 and 159.

Therefore, the test mode occurrence 81168 is the first
The above-mentioned MODE1. M
ODE2.8CONI.

BOCON2. -BOCOMn (1) Generates each control signal and outputs the C0NT2 signal (clock signal) from the external input terminal 79 in FIG. 1 as it is as the MODE signal. Above 8C (lJl, 8CON2゜...BCONn
Each output terminal of the signal is connected correspondingly to each circuit block in FIG. MODE31M
(F) Each output mt is connected to each corresponding input terminal of the circuit block of the first EW. In this case, in each circuit block, as described later, the MODE1 signal, the output terminals mutually, the MODE2 signal terminals, the output terminals mutually, the M
Since the output ends of the ODE3 signal are connected to each other,
Connect the MODE1 output terminal of the test mode generator 68 to the MODE1 output terminal of the circuit block Lr, JIJ:<,
The same applies to the MODE2 output terminal and the MODE3 output terminal.

The circuit blocks 64 to 67 have the same configuration, and are each configured as, for example, BLOCK↓(1-1 to 0) shown in FIG. That is, the plurality of signal input terminals 22 to
24 (three are shown for simplicity of illustration) correspond to input signals BINI.

BIN2.8INa is input, and multiple signal output terminals 25~
Reference numerals 27 (three for simplicity of illustration) output corresponding output signals BOUTI, BOUT2°BOUTb, and are connected to signal input terminals and signal output terminals of other circuit blocks.

28 to 30.36.40.43G, tLS 1 System common control signal input terminal, corresponding output terminals 32 to 34 to enable connection with the circuit block.
, 37, 41.44. in this case,
28.32 is for input (IN) and output (OUT) of CLOCK2 signal for serial output synchronization, 29.33 is for input and output of MODE3 signal for series switching control, 30.34 is MODE1 for input switching For signal input and output, 36°37
is for input and output of MODE 2 signal for output switching,
40.41 is for RESET signal input and output, 43.4
4 is for inputting and outputting the CLOCK signal. Reference numeral 35 denotes a test serial input terminal to which the test serial output CHECK2 signal from another circuit block is input, and 31 indicates a test serial output terminal to output the test serial output CHECK2 signal to the other circuit block. 39 is the test result signal CHECK1 of this circuit block and CHE from other circuit blocks.
Test result signal CH input through CK1 input terminal
Output terminal for ECK1 and CH of other circuit blocks
Connected to the ECKI input terminal.

Reference numeral 42 denotes an input terminal for receiving the control signal BCON of this circuit block, and the BCON signal is applied from the test mode generation FA 68 in FIG.

The signal input terminals 22-24 correspond to input circuits 8-1.
0, and output circuits 16 to 18 are connected to the signal output terminals 25 to 27 in correspondence with each other. Reference numeral 11 denotes a test signal generator, the details of which will be described later, but the CLOC
It is connected to the KI input terminal 43, the BCONL input terminal 42, the RESET input terminal 4o, and the respective input circuits 8 to 10.
It is connected to each output circuit 16-18. Numeral 19 is a multi-input OR gate which calculates the logical sum of the comparison result signals C0UT1 to C0UTb from the output circuits 16 to 18. Reference numeral 20 denotes a memory circuit (for example, a D-type flip 7
It consists of a 0-tube circuit, and CLOC is used as its clock input.
Kl is used). 46 is a two-person OR gate, and the comparison results of this circuit block, that is, internal des1~
The result (Q output of the flip-flop circuit) and the test result (comparison result) input from another circuit block through the CHECKI terminal are logically summed.

4 shows a specific example of the test signal generation section 11 in FIG. 3, which includes a test signal generation block 101, a test signal generation block control counter 102, and a decoder 1.
03, and a group of inverters (only some of them 104 to 106 are shown). Basically, it is a BCONj signal.

Counter 10 is activated by RESET signal and CLOCK1 signal.
2 is controlled, and according to the state, the decoder 103,
The operation of the test signal generation block 101 generates output state control signals CC1 to ccb and test expectation signals TOUT1 to TOUT.
OUTb, test input signals TlN1 to TlNa are output. A detailed explanation of the operation will be replaced with an explanation of the operation of the LSI system described later.

On the other hand, the input circuits 8 to 1o have the same configuration,
The input circuit 8 will be described in detail as a representative example.

That is, this human circuit 8 is connected to the corresponding B of this circuit block.
Input signals BIN1 and M input from IN1 input terminal 22
a two-person AND gate 1 that performs an AND with the ODE1 signal; a two-person AND gate 2 that performs the negative OR of the MODE1 signal and the corresponding test person signal TIN1 from the test signal generator 11; Above two gates 1.2
a two-person gate 3 to which each output of is input and outputs an internal input signal 5YSIN1 to be supplied to the internal circuit of this circuit block; a two-person gate 4 to which the 5YSIN1 signal and MODE3 signal are input; MODE3
an inverter 45 that inverts the signal, and this inverter 45
The output of the AND gate 5 and the CHECK2 signal are input to the two-person gate 5, the output of the two AND gates 4 and 5 is input to the two-person gate 6, and the output of this NOR gate 6 is input to the D input terminal. It consists of a D-type flip-flop (FF) circuit 7 which inputs a CLOCK2 signal to a clock input terminal GK and outputs a Q output as a CHECK2 signal. Note that other input circuits 9. ...10, -81N 2 instead of the input signal BIN1 (7)
．．・F31 Na is input, test input signal TlN1
TlN2°...TlNa are input instead of , and the internal input signals are 5YSIN2,...5YSINa. In addition, the input circuits 8 to 10 are connected to the CHECK2 signal in series, and the input circuit 8 receives the CHECK2 signal from the CHECK2 input terminal 35 of this circuit block, and its C)-IEcK2 signal output is connected to the next stage. input to the input circuit 9 of. This becomes the CHECK2 signal input to the input circuit 9, and the same process is repeated thereafter.

Next, the functions of the input circuits 8 to 10 having the above configuration will be explained. The input signals BIN1-8INa and the test input signals TIN1-TlNa from the test signal generation section 11 are MO
Internal input signals SYS I N 1 to SYS I N are switched and selected by the DEI signal to the internal circuit of the circuit block.
Supplied as a.

However, in FIG. 2, when the input signals BINI to BINa are selected, they are supplied internally with opposite polarity, but there is no problem if the internal circuit of the circuit block is designed accordingly. Then, in the input circuit 8, the CH
The ECK2 signal is switched and selected by the MODE3 signal, guided to the FF circuit 7, inputted and stored at the timing of the CLOCK2 signal. The Q output of this FF circuit 7 is input to the input circuit 9 at the next stage, and this input and the 5YSIN2 signal are switched and selected by the MODE3 signal and stored in the FF circuit 7 of the input circuit 9.

The same operation as above is performed from this input circuit 9 to the input circuit 10 at the final stage, and the output of the FF circuit 7 of the input circuit 10 at the final stage is outputted from the ECK2 output terminal 31, and the other circuit blocks are Input to CHECK2 input terminal 35.

That is, each of the input circuits 8 to 10 receives the internal input signal SY.
It has a function of storing S I N 1 to SYS I Na at a timing that can be determined arbitrarily by the MODE3 signal and outputting it serially to the outside of the circuit block, and at that time, it is possible to input the ia PI ratio output from other circuit blocks. . Therefore, in an LSI system having a plurality of circuit blocks, it is possible to take out the internal input signals of all the circuit blocks in series from one external output terminal (81 in FIG. 1) and observe them.

Further, the output circuits 16 to 18 have the same configuration, and the output circuit 16 will be described in detail as a representative. That is, this output circuit 16 includes a two-man AND gate 12 into which the internal output signal 5YSOLITI outputted from the internal circuit of this circuit block and the MODE2 signal are input, and the corresponding output from the MODE2 signal and the test signal generator 11. A two-person gate 13 to which the state control signal CC1 is input, and the two gates 1
2. A two-person gate 14 which receives each output of 13 and outputs an output signal BOtJT1 to the corresponding BOtJT1 output terminal 25 of this circuit block, and a corresponding output from the output of the NOR game 1-14 and the test signal generator 11. It consists of an exclusive OR gate 15 that performs an exclusive OR with the test expectation signal TOUTI and outputs a comparison result signal C0LJTI. Note that other output circuits 17. ...In 18,
Instead of the internal output signal 5YSOIJTI (C8YS
OtJT2.・5YSOtJTb is input, CC2,...CCb is input instead of the output state control signal CCI, and TOtJT is input instead of the test expectation signal TOUT1.
2. ...TOUTb is input, output signal is BOtJT
2. ...BOIJTb.

Next, the functions of the output circuits 16 to 18 having the above configuration will be explained. Internal output signal 5 from the internal circuit of the circuit block
YSOtJT1-5YSOUTb and test signal generator 1
The output state control signals CGI to CCb from MOD
Switching is selected by E2 signal and BO1JT1 corresponds to each
~BOIJTI output terminal ~BO1J as BOUTb signal
It is output to the Tb output terminal. At this time, 5YSOUT1~
When 5YSOtJTb is selected, it is output with the opposite polarity, but internal comparison is performed by an exclusive OR gate 15 to obtain the desired output polarity, and the comparison result signal C0tJT
1 is obtained. Similarly, the BOUT2, ·BOLJTb signals and each corresponding LTTOUT2° · · · TOIJTb are compared, and the comparison result signal C0tJT2. ...C0tJT
b is obtained.

That is, each of the output circuits 16 to 18 has a function of switching and selecting the circuit block internal output signals 5YSOUTI to 5YSOLJTb and output state control signals CC1 to CCb and outputting the selected signals to the outside of the circuit block, and outputting the selected signals and test signals to the outside of the circuit block. Expected signal TOUTI~T
Compare the comparison result signal cou”ri to C0 with OUTb.
It has the function of outputting UTb.

Then, the comparison result signals cou"ri to C0UTb are logically summed by the OR gate 19, and when the output of one of the OR gates becomes stable, they are stored in the storage circuit 20,
The output of this memory circuit 20 and the CH from other circuit blocks
An OR gate 46 performs a logical OR difference with the CHECK1 signal input through the EK1 input terminal 38. Therefore, by sequentially connecting all circuit blocks so that the CHECK1 output terminal is connected to the CHECK1 input terminal of other circuit blocks, the test results of all circuit blocks can be transmitted from one external output terminal (80 in Fig. 1). Take it out and take it out! measurements can be made.

Next, the test sequence operation of the entire LSI system shown in FIG. 1 will be explained with reference to the timing chart shown in FIG.

When the RESET signal input from the external input terminal 77 is at low level "L II", all the circuits are reset.
ODE1~MODE3. TOU71~ in each signal of BCON1~BCONn and all circuit blocks
Each signal of TOIJTb and CCI to CCb becomes L°'. The test mode generator 68 has external input terminals 78 and 79.
C0NTl from.

When the C0NT2 signal is input, BCON1 to BCONn
, MODE1 to MODE3 (7) are generated as shown in the timing diagram. In this timing diagram, C
The above control signal is generated at the falling timing of the LOCK1 signal, but the CLOCK1 signal is generated at the external input terminal 7.
It is sufficient that each control signal is determined by the rising edge of the CLOCK1 signal. Also, in this case,
The decoder 151 in the test mode generating section 68 shown in FIG. 2 may be designed to generate each of the above control signals according to the state of the counter 152. In addition,
In the timing diagram, the CLOCKI signal
K 2 <M No. Lt Same L; ') Although they are drawn with timing, since the mounting surfaces are completely different, they may be asynchronous, and these will be explained separately below.

First, medical functions using the CLOCK1 signal will be explained. The RESET signal is at high level "°H'.

Therefore, MODE2 signal and BCON1 to BCONn
When the CLOCKI signal is inputted once (pulse) while the signal is in the L' state, the output states of all the circuit blocks 64 to 67 (CC1 to ccb <the number of b has a unique value for each block) are all “L”, test expectation signal T
Since all the OUTI to TOUTb signals are "L II", the output of the exclusive OR gate 15 in all output circuits 16 to 18 is "L", the output of one OR gate is °゛L'°, and the memory circuit 20 output becomes ゛Lpa,
The CHECK1 output of each circuit block is L°', so the CHECK1 output of the circuit block 67 is “L°”.
It becomes II. Next, when the BCON1 signal is set to HIGH,
Only the counter 102 in the test signal generation section 11 of the first circuit block 64 becomes movable, and when six more CLOCK1 signals (pulses) are input, it changes from TOUTI to TOI.
It is designed so that up to JTb it becomes "H'°. Now, all the output circuits 1 in the first circuit block 64
The comparison test output of the exclusive OR circuits 15 (comparison circuits) among the exclusive OR circuits 6 to 18 is output to CHECK39. By sequentially setting the BCONI signal to the BCONn signal to "H11", it is possible to test the comparison circuits of all circuit blocks.

Next, when the value of the counter 102 in the test signal generating section 11 in each circuit block is (b+1), CC1 to C
Set all Cb signals to “H”, and
If the design is designed so that all Tb signals are set to "H", after one CLOCK1 signal is input to the n-th circuit block 67, all of the 8CON1 to BCONn signals are set to "H".
When the CLOCKI signal is input once with the input voltage set to "H", all the CC1 to CC signals of all circuit blocks become H". Then, if only the BCON1 signal is kept high and all the BCON2 to BCONn signals are set to 4 ``l'', only the first circuit block 64 becomes movable.

If you input one more CLOCKI signal (pulse),
If you design it so that it is L°' in order from TOUTI to TOUTb, all blocks cc will be
i~ccb signal is H'', TOtJT1~TOUTb signal is ``H'' - c-Alnorr Coincidence output 11 due to coincidence at the opposite level to the above L IT is CHECK1 output terminal 39
The comparison circuit test output ii Hn in the output circuit at the opposite level is output to CHECK1 by the following pulse.
It is output to the output terminal 39. In this case, as described above, the H'
', the comparison circuit test is performed for all circuit blocks. When the comparison circuit test of the n-th circuit block 67 is completed, all the BCON1 to BCONn signals are
'1-1', and set the MODEI and MODE2 signals to 'H' to test all circuit blocks at the same time,
The test result is output to the external output terminal 8o for CHEKI. That is, the test signal generation unit 11 of each block generates the test expected signals TOUT1 to TOUTb and TlN1 of the block from the state where the value of the counter 102 is r2b+2J.
- Designed to generate TlNa. If the counter 102 is designed to stop operating after the necessary test pattern is generated, the comparison output of that circuit block will be fixed at "L", so it will be the largest test stop of all the circuit blocks. The test is completed by inputting the number of pulses until the counter 102 of the circuit block having the number stops operating.

Also, when testing the comparison circuit of each circuit block, the BOtJT1 to BOLITb output terminals 25 to 2 of each circuit block
7, CG1~ccbi@ are all “LIT” or “H”
11, so similarly it becomes °゛L'' or II HIt, so finally the external output terminals 72 to 74 of the LSI
All outputs "L" Matc "H" (!: Nari, it is possible to test output D6 (DC) at the same time. Roughly speaking, since the input signals of each circuit block are not used at this time,
Finally, the external input terminals 69 to 71 of the LSI become free, and input DC testing is also possible.

However, the use of the above input terminals is limited to MODE as described later.
3 is somewhat restricted in the timing of using the signal.

Note that the time required for the previous comparison circuit test is shorter than the time required for the simultaneous functional test of each circuit block described above.

Next, functions using the CLOCK2 signal will be explained. This function is for testing input signals of each circuit block, and serial output signals for testing of each circuit block are outputted in series from the CHECK output terminal 31, respectively. Therefore, the inputs of all circuit blocks are driven at arbitrary timing during testing.

The RESET signal changes from °゛[pa to ゛Hpa, and CLOC
Until two K1 signals are input, the MODE2 signal is "
L”, CG1 to CCb signal 1 are all “shi”, so
Output signals of all circuit blocks BOtJT1 to BOtJTt
l becomes °゛L''. Therefore, if all the external input terminals 69 to 71 of the LSI are set to L'', the input signals to the signal input terminals 22 to 24 of all circuit blocks become LII. Therefore, if the MOED1 signal is set to L'', For example, input circuits 8 to 10 of all circuit blocks select the LSI system input signal, and at this time, the MODE3 signal is set to "H" and the CL
If one OCE2 signal is input, all input circuits 8 to 1
The output of the memory circuit (FF circuit 7) in 0 becomes L''. Then, if the MODE3 signal is set to L and the pulse input of the CLOCK2 signal is continued, L'' is output from the CHECK2 output terminal 31, and the circuit block It becomes possible to check the connection between

Next, when the MODEI signal is set to H'', the input circuits 8 to 10 of all circuit blocks are connected to test input signals TlN1 to TlN.
If you select a and prepare a signal with a pattern of, for example, 1010... in TlN1 to TlNa, MODE
If the 3 signals are inputted once to HH and CLOCK2 signals, the memory circuit (FF circuit 7) in the input circuit will receive the above 10 signals.
10... patterns of data are stored, and then MO
If the pulse input of the CLOCK2 signal is continued with the DE3 signal set to L°', the serial register operation of these memory circuits (FF circuit 7) is performed.

Roughly speaking, when all the circuit block CC7 to ccb signals of Zenren are all "H" and the MODE2 signal is "L II", CC1
~ Similarly to when all the ccb signals are low, the memory circuit (FF circuit 7) in the input circuit of all circuit blocks is set to MODE.
If the CLOCK 3 signal is set to "H" and one CLOCK2 signal is input, the signal becomes "H". Then, change the MODE3 signal to °゛L°
°, continue inputting pulses of CLOCK2 signal and CHE
By checking the “H” output of the CK2 output terminal 31,
Enables connection inspection between circuit blocks. MODEL
, MODE2 (ijl “H”)

I am going to do a simultaneous reform test of all the name blocks, ~l
O[) Set the E3 signal to “H” and set the rCLOCK2 signal to 1.
When the output is input, the test input signal TIN1~
TlNa is input to the memory circuit (FF circuit 7) in the input circuit of all blocks, and then the MODE3 signal is "L"
1. : L, T CL OCK If you continue to input the pulse of the 2 signals, CHECK will be output from the nth circuit block 67.
Test input signals TlN1 to Tl are applied to the external output terminal 81 for
Na is output in series.

Note that the test time before that is short compared to the time for the above-mentioned simultaneous functional test.

Moreover, although the function of simultaneous testing of all circuit blocks has been described above, in the present invention, the control signal BC of the circuit block
Since ONI to BCONn are independently applied to each circuit block from the test mode generator 68, independent testing of each circuit block is also possible. That is, to add an independent test for each block after the simultaneous functional test of all circuit blocks shown in the timing diagram, it is sufficient to add a test signal generation block for the independent test in the test mode generator 68. This can be easily achieved. Such independent testing of each circuit block is effective for block evaluation and failure analysis during the LSI development stage.

According to the LSI of the above embodiment, the test time is only the maximum test FR of the divided circuit blocks, so if the test time of each circuit block is the same and the number of blocks is n,
The test time will be about 1/n. Generally, if the test sequence before system division is m, the test sequence after n divisions will be approximately n-mn. In addition, in the conventional circuit division method, circuit division is greatly restricted by the number of external terminals, but in the LSI system of this embodiment, in addition to the original input and output terminals, the divided circuit blocks have CHECK terminals, output terminals, and CHECK2 terminals.
It is only necessary to add seven terminals: input terminal, output terminal, RESET terminal, output terminal, and BCON input terminal, and restrictions on division are small.

Furthermore, the conventional self-test method of incorporating a pseudo-random pattern generator and output compression device into an LSI cannot be achieved by dividing the LSI system and cannot be applied when the LSI system is highly integrated. No matter how high the level of integration becomes, if the basic circuit block is designed on a small scale, it is easy to design test patterns that are far superior to pseudo-random patterns.
It becomes easier to generate test series. In addition, conventional LSSD
When applying the method, the number of internal memory circuits increases as LSIs become highly integrated, and the time required to input and output data serially is ignored due to the constraint that they must be connected to serial input/output terminals outside the LSI. The higher the degree of integration, the greater the test time. but,
In the LSI of this embodiment, the test time can be suppressed to about the maximum test time of the divided circuit blocks. Roughly this example S! If you develop a test series for the basic circuit blocks, you can use the test series as is for LSI systems designed using it.
It can greatly contribute to the short period of the M generation period, and is particularly suitable for logic LSIs.

In the above embodiment, an external output terminal was provided for observing the test result output CHECKI, but this CH
If ECKl is to be observed only in an inspection step in the manufacturing process prior to product testing, pads provided on the chip or wafer may be used. The same applies to the external output terminal for CHECK2.

[Effects of the Invention] As described above, according to Komei's semiconductor integrated circuit, it is possible to suppress an increase in test time, to easily generate sequences, and to reduce the number of test terminals of divided blocks. Since there are few restrictions on block division, it is extremely effective when applied to, for example, a logic LSI and tested during its development and FFI production.

[Brief explanation of drawings]

FIG. 1 is a configuration explanatory diagram schematically showing an LSI that is an embodiment of the present invention, FIG. 2 is a block diagram showing a specific example of the test mode generating section in FIG. 1, and FIG. A configuration explanatory diagram representatively showing circuit block 11 [1i1 in the figure, No. 4
This figure is a block diagram showing a specific example of the test signal generation section in FIG. 3, and FIG. 5 is a timing chart showing an example of the test sequence of the LSI shown in FIG. 1. 1.2.3...First switching goo 1~. 4.5.6゜45... Second switching circuit gate, 7... Memory circuit (FF circuit), 8-10... Input circuit, 11... Test signal generation section, 12, 13 .14... Output switching circuit gate, 15... Comparison circuit, 16-18... Output circuit, 19.46... OR gate, 22-24...
Signal input terminal, 25-27...Signal output terminal, 31...
Serial output terminal for inspection, 35...Series input terminal for inspection, 38
...Comparison result input terminal, 39...Comparison result output terminal, 6
4-67...Circuit block, 68...Test mode generation section, 69-71...External input terminal, 72-74...
...External output terminal, 80...External terminal for outputting test results, 81...External terminal for serial output for inspection. Applicant's agent Patent attorney Takehiko Suzue Procedural amendment 1986 [5.109 days]

Claims (4)

[Claims] (1) It has a group of circuit blocks divided into a plurality of blocks and a test mode generation section for supplying a common test control signal to these blocks, and each circuit block has an input circuit corresponding to a plurality of signal input terminals. At the same time, an output circuit is provided corresponding to each of the plurality of signal output terminals, and a test signal generating section is provided for supplying a test signal to each of these input circuit groups and output circuit groups, and in each of the above input circuits, The input signal from the signal input terminal and the test input signal from the test signal generation section are switched and selected by the test control signal MODE1 from the test mode generation section, and the selected output is input to the internal circuit of the circuit block. A first switching circuit is provided for supplying the signal as a signal, and each of the output circuits is provided with a comparison circuit that compares the output signal of the internal circuit and the test expected signal from the test signal generation section and outputs a comparison result signal. , in each of the circuit blocks, the comparison result signal of each output circuit is logically summed with the comparison result OR output from the other circuit block inputted through the comparison result input terminal, and the comparison result OR signal is outputted to the comparison result output terminal. The paths between the comparison result input terminal and the comparison result output terminal in each of the circuit blocks are connected in series, and the comparison result output terminal of the final stage circuit block is connected to the outside of one integrated circuit. A semiconductor integrated circuit characterized by being connected to a terminal. (2) In each of the output circuits, the output signal of the internal circuit and the output state control signal from the test signal generation section are connected to the test control signal MODE from the test mode generation section.
2, and outputs the selected output to the corresponding signal output terminal of the circuit block, and also serves as one input of the comparison circuit. A semiconductor integrated circuit according to claim 1. (3) In each of the input circuits, a second switching circuit is provided which switches and selects the selected output of the switching circuit and a separately input test serial input using the test control signal MODE3 from the test mode generator; A memory circuit is provided that stores the selected output of the switching circuit No. 2 and uses the stored output as a serial output for testing, and in each of the circuit blocks, a storage circuit is provided between one serial input terminal for testing and one output terminal for testing. The paths between the serial input for testing and the serial output for testing of each of the input circuits are connected in series, and further between the one serial input terminal for testing and one output terminal for testing in each circuit block. The circuit blocks are connected in series as a whole, and the test serial output terminal of the circuit block at the final stage is connected to an external terminal of one integrated circuit. Semiconductor integrated circuit described in Section 1. (4) The test mode generating section has a mode in which the circuit blocks are simultaneously driven and controlled and a mode in which each circuit block is independently driven and controlled, and the mode can be switched. A semiconductor integrated circuit according to scope 1.