JPS62217287A - Image signal format conversion - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] A single frame memory is used to convert digital data after image processing, which is in a non-interlace format, to an interlace format for the purpose of outputting to a television monitor, etc. , reads/writes to the memory using the same address, and determines the line address according to the address of the line stored in the previous frame.

[Industrial application field]

The present invention relates to an image signal format conversion method.

Generally, non-interlace data is output as sequence data after image processing, and in order to display the sequence data on a television monitor, it must be converted into an interlace format. The present invention attempts to continuously perform this non-interlace/interlace conversion using a single frame memory.

[Conventional technology]

FIG. 4 shows an outline of a conventional video rate non-interlace format conversion device. As shown in this figure, the conventional device has two frame memories, each of which can write non-interlace data, and the address is set to switch 1.
2 from the read address generation circuit 10 or the write address generation circuit 11, and read (read) data is outputted via the selector 15. Frame memory 13
When the address of the frame memory 14 is given from the circuit 10, the address of the frame memory 14 is given from the circuit 11, and at this time, the selector 15 inter-interlaces the read output of the frame memory 13 (non-interlaced data written in the previous cycle). The data is output as race data, and the non-interlace data currently being input is written into the frame memory 14.

Since the write side is non-interlaced, the write address generation circuit 11 generates 0, 1, 2, 3, .・・・・・・
...(2N-1) and generates addresses (line addresses) that are sequentially increased by 1. Since the read side is interlaced, the read address generation circuit 10 generates 0, 2, 4, . . . for even fields. ......(2N-2), 1, 3.5 for odd fields.・・・・・・(2N-1
) is generated (line address).

In this way, in this device, while writing to one memory in a non-interlaced manner, reading from the other memory is performed in an interlaced manner, and when writing/reading for one frame is completed, switching is performed so that the above one becomes the reading side and the above The other side is set as the writing side, and this process is repeated thereafter to perform continuous writing/continuous writing and non-interlace/interlace conversion.

[Problem that the invention seeks to solve]

However, in this conventional device, since the frame memory for reading and the frame memory for writing are separate, there is a problem in that two frame memories of the same capacity are required.

The present invention attempts to improve this point and perform the same continuous writing/successive writing and non-interlace/interlace conversion as described above in one frame memory.

[Means for solving problems]

As shown in FIG. 1, in the present invention, the frame memory is one of the memories (RAM) 8. In a semiconductor memory, when a word line is selected, the stored data of the memory cells belonging to the selected word line appears on each bit line all at once, and if the data is taken out through the data bus, it means that reading has been performed. Once the potential of the data bus is determined, it is transmitted to the memory cell through the bit line, and writing has been performed to the memory cell. In this way, by reading the first half of one memory cycle and writing the second half, it is possible to simultaneously read and write to the memory. However, the read address and write address will be the same.

Assuming that the read address and write address are the same, and the write is non-interlaced and the read is interlaced,
Generating memory access addresses requires some ingenuity. The cyclic upper address generation circuit 6 is an address generation circuit with this design.

The intra-line lower address generation circuit 7 generates an address for each pixel on the line. When one line corresponds to one word line, circuit 6 is a word line address generation circuit, and circuit 7 is a bit line address generation circuit. These circuits 6
, 7, if the memory 8 is accessed using the combination of upper and lower addresses (word line and bit line addresses), interlaced reading and non-interlaced writing can be performed simultaneously and continuously in pixel units. It can be done.

[Operation] In the present invention, certain pixel data is successively output from the memory, and the pixel data input at that time is written to the same address in the memory. An image is divided into lines in the Y (vertical) direction, and each line is divided into pixels in the X (horizontal) direction, but the number of lines in one frame (one image) is 2N (N is the number of lines in one field). The first line, second line, . . . (2N-1)th line, 2Nth line of the image are in the same order 1, 2, . . . in the non-interlaced signal.・・・・・・
...(2N-1), 2N is output, and the interlaced signal is 1.3, 5.・・・・・・(2N-1), 2,4
．． ....They are output in the order of 2N. Therefore, in a certain frame, if we write the data of the pixel of the line at a certain address in the memory, and then read it in the next frame and corrupt the data of the pixel of the l line, the correspondence between k and β is is as above, i.e. k 1. 2. 3. 4. ...2N-1
,2Ne 4 , N+1.2.8+2s-・-N
, 2N.゛That is, for k and l, if r is odd, then = (J+1)/2, and if l is even, then = N-11! /2
(7) There is a relationship. In this relationship, if the memory write address of each pixel in a frame is determined, the write address of each pixel in the next frame is determined, and the write address of the next frame is determined from the write address of Makito's frame, and the following frames The write address of is determined in the same way. The write addresses of each frame are not all different, but have periodicity, and are repeated after one cycle.

The maximum value of the period is (2N-2). For example, if one frame has 6 lines (actually, it is a large number such as 512), the period will be 4 frames as shown in the following table. This is Fl, F
2.・・・・・・ is the first frame, second frame, etc.
... is shown, LL, F2. . . . indicates 1st line, 2nd line, . . .

Table 1 PI F2 F3 F4 F5 AI LI LI LI LI LI LI A2 F2 F4 F5 F3 F2 A3 F3 F2 F4 F5 F3 A4 F4 F5 F3 F2 F4 A5 F5 F3 F2 F4 F5 A6 F6 F6 F6 F 6 L6 F1=F5, and F5 After that, F1 to F4 are repeated. Note that the sharpness in Table 1 is as follows. In the first frame F1, line Ll is output in a non-interlaced manner.
, L2. ......F6 is the memory address Al, A
2. ...I wrote them on A6 paper in order. If you write like this, reading is interlaced, so AI,
A3. A5. A2. They must be written in the order of A4, A6, and since non-interlaced writing is performed at this time, Ll is written to A1, F2 . A5 and F3. A
F4 to 2, F5 to A4. F6 is written to A6. This is the F2 column. Next, since δ selling must be done in interlaced format, At, A5. A4, A3.
A2. 'The order is A6, so AI is Ll, A5 is F2. F3 on A4. F4 to A3, F5 to A2. A6 to F
6 is written. This is the F3 column. The following shall apply accordingly.

As shown in Table 1, the frame numbers Fl, F2 . If . . . is known, the order of addresses to access the memory (higher addresses as they correspond to lines) is determined, and in-line addresses (lower addresses, which do not change for each line) are generated. This allows interlace reading of memory written in non-interlace. The address generation circuit 6 in FIG. 1 corresponds to the former, and the same circuit 7 corresponds to the latter.

(Example) An example is shown in Fig. 2.The signals input to this memory device are non-interlaced data output from an image processing device (not shown) and a frame synchronization pulse FS generated once between each frame. and a line that occurs once between each line (
(horizontal) synchronization pulse LS1 and a clock CLK that is generated once for each read/write of one pixel. In this case, a memory device for an image of one frame and six lines will be described. As mentioned above, since the period of the upper address is four frames, the counter 1 for counting the frame synchronization pulse FS is assumed to have two bits. The counter for counting the line synchronization pulses LS has 3 bits, and is reset by the frame synchronization pulse FS to generate a line number.

The address A4. in the table below is stored in ROM4. A2.・・・・・・
Write it down.

Table 2 This Table 2 corresponds to the above Table 1, and in the first frame, lines 0, 1...・・・・・・5 to address A4゜A2
．． AO,... After writing to A1, in the next first frame, A4. AO, A5.・・・・・・Read/write with A1, 9 tastes. If the ROM 4 is accessed using the output of counter 1 as the upper address UA and the output of counter 2 as the lower address LA, A4. A2. ... can be read.

A pixel counter 3 counts the clock CLK, is reset by the line synchronization pulse LS, and outputs the pixel number in the line. Non-interlaced data is input to the RAM 5 and read/written using the output of the ROM 4 as the upper address and the output of the counter 3 as the lower address.

FIG. 3 shows the output state of the ROM 4. When the count value of counter l is O, the count value of counter 2 is 0.1, 2, .・
..., the output tJA of ROM4 becomes 4,
2. O,... becomes. When UA=4, the 0th line is written to the upper address 4 of the memory 8 (which can be considered as the memory cell group belonging to the 4th word line), and the
The line is written to the upper address 2 of the memory (memory cell group belonging to the second word line), and...
The following shall apply accordingly. After the last line is written, a frame synchronization pulse FS is output, counter 1 is plus 1, counter 2 is reset, and counter 2 becomes 0,
As 1°2, . . . is output, the output of ROM 4 becomes 4°0.5. ······become. Since writing has been done above, if UA=4, the Oth line will be read, and if UA=0.5. ...then the second. 4th...
...The line is read and the output is in interlaced format.

Writing is also performed at this time.

〔Effect of the invention〕

As explained above, according to the present invention, non-interlaced sequence data after image processing can be continuously converted into an interlaced signal, which is a video signal former, using a single frame memory. , is extremely effective.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing the principle of the present invention, Fig. 2 is a block diagram showing an embodiment of the invention, Fig. 3 is an explanatory diagram of upper addresses given to memory, and Fig. 4 is a block diagram showing a conventional example. be. In FIGS. 1 and 2, 8 is a frame memory, and 6.4 is an upper address generation circuit.

Claims (1)

[Claims] An image signal format conversion method for writing a non-interlaced image signal into a frame memory, reading it out, and converting it into an interlaced image signal, using a single frame memory, generating an upper address for the data of each line of the first frame of the signal so that the line and the memory upper address correspond one-to-one, and storing the data in the memory at the address; next, in the second frame; reading the memory address storing the first line of the first frame and then writing the first line of the second frame to that address, where k, l
assumes that writing is non-interlaced and reading is interlaced, and the number of lines in one frame is 2N, and varies within 1 to 2N. Similarly, in the m-th frame, the m-1th frame is l
An image signal format conversion method comprising the steps of: reading a memory address in which the line is stored, and then storing the kth line of the mth frame in the memory address.