JP3104001B2 - Line buffer and image processing apparatus using the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus for performing a two-dimensional filter process on a progressively scanned image obtained by an ITV camera or the like to perform feature extraction, image quality conversion, and label processing.

[0002]

2. Description of the Related Art Conventionally, an image of the same size as a two-dimensional filter is cut out from a progressively scanned image obtained by an ITV camera or the like, and feature extraction, image quality conversion, label processing, and the like are performed. For example, as an apparatus for cutting out an image of 3 rows and 3 columns, there is an image processing apparatus of Japanese Patent Publication No. 61-62187. This image processing device has three one-port RAMs, two
One selector and a plurality of image latch circuits.

In this image processing apparatus, two successively scanned images of two lines temporally continuous are stored in two RAMs, and two lines of sequentially scanned images are read out from the two RAMs, and the remaining one RAM is read. In a write state to record the next scanned image.

Next, the RAM that stores the temporally oldest sequentially scanned image among the three RAMs is put into a write state to store the latest sequentially scanned image, and to sequentially read two rows of data from the remaining two RAMs. Read the scanned image. Then, an image of three rows and three columns is cut out from the sequentially scanned image by using a plurality of image latch circuits from the sequentially scanned image of two rows read from the two RAMs and the latest progressively scanned image not passing through any RAM. ing.

[0005]

In the conventional image processing apparatus described above, one line of RAM is added to the number of lines of the image to be stored.
There is a problem that a large capacity is required, which hinders the integration of the image processing apparatus.

Some image processing, such as temporary labeling processing, processes the next pixel while updating a part of the cut-out image based on the processing result. This is called update type processing. In the sequential update type processing, it is necessary to write the processing result of the cut-out image to the RAM again. In a conventional image processing apparatus, for example, two R
One of the RAMs is in a read state and the other R
RAM in read state when AM is in write state
After reading the last label data for one scanning line from the RAM, it is necessary to wait until the writing of the label data for one scanning line to the RAM is completed in order to read the label data from the RAM which is currently in a write state. There is a problem that the speeding up of the operation is hindered.

[0007] The present invention has been made in view of such circumstances, and aims to reduce the capacity of the RAM, and to continue the processing without providing a waiting time for each scanning line even in the case of the successive update type processing. It is an object of the present invention to provide an image processing apparatus provided with a line buffer unit capable of performing the following.

[0008]

A line buffer according to the present invention comprises a first address generating circuit for generating a read address.
And the read address generated by the first address generation circuit.
One cycle from the read address in synchronization with the
Generates a write address delayed by a plurality of cycles.
Said address generating circuit, with respect to a different address first
By the read address generated by the address generation circuit of
And the write address generated by the second address generation circuit.
One or two or more 2-port RAs in which image data of pixels of a scanning line length capable of simultaneously writing by a dress is stored.
M and a plurality of image latch circuits for temporarily holding image data read from the two-port RAM based on the read address output from the first address generation circuit.

The line buffer according to the present invention comprises one or two or more image data of pixels of a scanning line length capable of simultaneously performing read and write for different addresses.
A port RAM, an address generation circuit for generating a read address of the two-port RAM, and an address generated by the address generation circuit temporarily stored in the two-port RAM as a write address. And a plurality of image latch circuits for temporarily holding image data read from the two-port RAM based on a read address output from the address generation circuit. .

Further, the line buffer of the present invention is a two-port RAM for storing image data of pixels of a scanning line length with a bit width twice or more as large as the bit width of one pixel of image data.
An address generating circuit for generating a read address of the two-port RAM; an address latch for temporarily storing an address generated by the address generating circuit and then supplying it as a write address to the two-port RAM And a plurality of image latch circuits for temporarily holding image data read from the two-port RAM based on a read address output from the address generation circuit.

Further, the line buffer of the present invention has a RAM having a number of words equal to or greater than the number of pixels on all the scanning lines to be held and having the same number of ports as the number of all the scanning lines to be held. An address generating circuit for generating addresses corresponding to the number of words, an address latch circuit for temporarily storing the address generated by the address generating circuit and then supplying the address to the RAM as a write address; An address conversion circuit for converting an address into a read address for one scanning line; and a read circuit generated by the address conversion circuit.
Address offset circuit for generating a read address with an offset of one scan line with respect to the read address, and a selector for counting the address or the number of cycles and switching the output destination of image data read from the RAM for each scan line. And a plurality of image latch circuits for temporarily holding image data output from the selector.

Further, the line buffer of the present invention has a RAM having a number of words equal to or greater than the number of pixels on all the scanning lines to be held and having the same number of ports as the number of all the scanning lines to be held. A first address generating circuit for periodically generating addresses corresponding to the number of words as a read address, and a second address for generating an address delayed by one scanning line with respect to the address generated by the first address generating circuit. A second address generating circuit which periodically generates as a read address of the first address generating circuit, and a read address generated by the first address generating circuit or the second address generating circuit.
An address latch circuit for temporarily holding a write address and then supplying the write address to the RAM as a write address;
And a plurality of image latch circuits for temporarily holding the image data read from M.

An image processing apparatus according to the present invention is characterized by including the above-mentioned line buffer.

[0014]

In the information processing apparatus having the above configuration, image data for one scanning line or a plurality of scanning lines of a sequentially scanned image or an image of a processing result is held in, for example, a 2-port RAM, and the 2-port RAM is used. Desired image data is read from the RAM and used for image processing.

At the same time, after the image data on the scanning lines other than the oldest scanning line is temporarily held in the image latch circuit, the image data is referred to on the 2-port RAM together with new sequential scanning image data or processing results. Is overwritten on the area holding the image data of the pixels that have already been processed.

Therefore, by reducing the memory capacity of the RAM, the circuit can be integrated and high-speed processing can be performed without providing a waiting time for erroneous scanning lines even when performing sequential update type image processing. Can do it.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. Prior to the description of embodiments of the present invention, a conventional image processing apparatus will be described. FIG. 17 shows a configuration of a conventional image processing apparatus. As shown in FIG.
Three one-port RAMs 1700 to 1702, two selectors 1703 and 1704, and an image latch circuit 1705
To 1713. The operation of this image processing device is as follows. In other words, two successively scanned images in time are stored in two of the three RAMs, and the two sequentially scanned images are read out from the two RAMs, and the remaining one RAM is read out. The next scanning image is recorded in the write state.

Next, the RAM that stores the temporally oldest progressively scanned image among the three RAMs is put into a write state to store the latest progressively scanned image and to store the remaining two sequentially scanned images.
Two rows of sequentially scanned images are read from one RAM. Then, the two rows of progressively scanned images read out from the two RAMs and the latest progressively scanned image that does not pass through any of the RAMs are converted into three rows and three columns from the progressively scanned image using a plurality of image latch circuits 1705 to 1713. The image has been cropped. FIG.
Is an eight-row progressively scanned image 18 by a conventional image processing apparatus.
FIG. 4 is a diagram showing a state in which an image 1802 of three rows and three columns is cut out from 00, and an arrow 1801 indicates a scanning direction, and a sequentially scanned image is transmitted in the order of a k-th row, an r-th row, an m-th row, and an n-th row. Come. Here, k1 to k8, r1 to r8, and m1
To m8 and n1 to n8 are k rows, r rows, m rows, n
The values of the pixels in the row are shown.

FIG. 17 shows a case where the conventional image processing apparatus uses image 1.
8 shows a storage state of the RAM in a cycle obtained by cutting out 802. That is, the RAM 1700 and the RAM 17
02 have already been written with the images on the m-th and r-th rows, respectively.
Is accessed, but RAM 1700 and RAM
Reference numeral 1702 denotes a read state, and RAM 1701 denotes a write state. In this state, RAM 1700 and R
The image data m5 and r5 are read from the AM 1702, and the image data n5 is written into the RAM 1701.

In the above-described conventional image processing apparatus, a RAM capacity for one row is required in addition to the number of rows of an image to be stored, which hinders the integration of the apparatus.

FIG. 9A shows a progressive scan image processed by the sequential update type image processing apparatus, and FIG. 9B shows label data of the processing result. In the label data, in order to calculate the label value N3 in the n-th row and the third column, the values in the second to sixth columns in the n-th row of the progressively scanned image and the second column to the m-th row in the label data of the processing result are obtained. Refer to the values in column 6. Since the cutout frame 90 and the cutout frame 91 are shifted to the right, in the state shown in FIG. 9, the third and subsequent columns of the mth row of the label data need to be held in the line buffer unit of this image processing apparatus. . FIG. 19 shows an access state of the line buffer when the conventional image processing apparatus is used for the successive update type processing. In FIG. 19, the line buffer unit shows a state in which label values M2 to M6 of the cutout frame 91 are generated, and the RAM 1900 is in a write state.
RAM 1901 is in a read state. Here RAM19
01 outputs M7 and is input to the image latch circuit 1903 via the selector 1902. And 1903-19
07, label values M2 to M6 are cut out. At the same time, the label value N2 of the processing result is input to this line buffer, so that it is written to the word 1 of the RAM 1900 in a write state. Hereinafter, similarly, RAM 1901
.., N1, N2,... Are sequentially read from the RAM 1900, but since the RAM 1900 cannot be simultaneously put into the write state and the read state, the RAM 1900 is not read.
After reading M8 from 1901, it is necessary to wait until writing for one scan to the RAM 1900 is completed before reading N1.

As described above, the conventional image processing apparatus cannot perform the sequential update type processing at high speed.

Next, an embodiment of the present invention will be described. FIG. 1 shows the configuration of an embodiment of the image processing apparatus according to the present invention. In this embodiment, an example in which an image of three rows and three columns is cut out from a sequentially scanned image will be described. As shown in FIG. 1, the image processing apparatus according to the present embodiment includes a memory control circuit 12, two-port RAMs 15, 16, image latch circuits 17 to 19, and a line constituted by image latch circuits 110 to 113. Buffer unit 11 and image latch circuit 11
5, 116 and an arithmetic unit 114.

Further, the memory control circuit 12 comprises an address generation circuit 13 and an address latch circuit 14. The image latch circuits in this embodiment all operate in synchronization with a clock. FIG. 2 shows progressively scanned images 20 and 3
FIG. 1 shows the cut-out image 21 in the row 3 column, and a, b, c, d, e, f, g, h, and i of the cut-out image 21 are shown in FIG.
Signals a, b, c, d, e,
Positionally coincides with f, g, h, and i. Hereinafter, the operation of the present embodiment will be described using an image of eight columns as an example. FIG.
The image 30 in a column is shown, and a cutout image 31 in three rows of r, m, and n and three rows and three columns is shown. In this embodiment, the progressively scanned images are stored in the 2-port RAMs 15 and 2 for each scanning line.
It is stored in the port RAM 16. For example, 2-port RAM
Assuming that the image of the r-th row is stored in the memory 16 and the image of the m-th row is stored in the 2-port RAM 15, the 2-port RAM 15 and the 2-port RA are operated by the address generation circuit 13.
At the same time when the pixels in the same column in the m-th row and the r-th row are read out from the same address
The pixel of the m-th row temporarily held in the 2-port RA
The corresponding column of M16 is overwritten.

At the same time, the image of the nth row is newly taken in and overwritten on the corresponding column of the 2-port RAM 15. Here, the image latch circuit 113 holds the image data for one cycle or a plurality of cycles, and the address latch circuit 14 uses the address held in the same cycle as the image latch circuit 113 as a write address as a two-port RAM 1.
5 and 16 are supplied, so that read and write do not overlap for the same address. After the above operation is repeated for one scanning line, the two-port RAM 16 and the two-port RA
M15 stores an image on the m-th row and the n-th row, respectively.

FIG. 4 shows the storage state of the sequentially scanned image when the line buffer unit 11 is outputting the cut-out image 31, and the numbers of the constituent elements are the same as those in FIG. In the figure, the 2-port RAM 16 and the 2-port RAM 15 initially store the image on the r-th row and the m-th row, but the data is read out in order from word 0, and is currently -Code 5 has been read. That is, the two-port RAM 16 and the two-port RAM
The data r6 and m6 are read from the RAM 15 respectively. At the same time, two-port RAM 16 and two-port RAM 1
Numeral 5 is a state in which the data is written in the word 4, the data m5 held in the data latch circuit 113 is written in the 2-port RAM 16, and n is written in the 2-port RAM 15.
Data n5 on the line is written. Data m5 is 1
It is read out from word 4 of 2-port RAM 15 before the cycle. 2-port RAM 15 and 2-port RA
The data read from M16 and the data in the n-th row are image latch circuits 17 to 19 and 110 to 112, 113, 1
The image is converted into a cut-out image 31 by 15 and 116.

FIG. 5 is a time chart showing the operation of the memory control circuit 12 when processing eight columns of images. In the figure, a clock defines a cycle, and a write address 118 is generated one or more cycles later than a read address 117. FIG. 5A shows a case where the write is delayed by one cycle from the read.
(2) is a case where the write is delayed by two cycles from the read. Further, the memory control circuit 12 can be constituted by two synchronous address generating circuits to generate a read address and a write address. The configuration described above cuts out an image of three rows and three columns, but it is easy to extend the configuration to cut out a larger image. For example, to enlarge an image in the column direction, an image latch circuit 19,
A new image latch circuit may be added to each output of 112 and 116, and a circuit similar to the configuration of the two-port RAM 16 and the image latch circuits 110 to 112 may be prepared for enlargement in the row direction. The two-port RAMs may be connected in series via an image latch circuit.

The image processing apparatus constructed as described above has an effect that the circuit can be integrated by reducing the RAM for one scanning line as compared with the conventional one.

FIG. 6 shows the configuration of another embodiment of the line buffer section in the image processing apparatus according to the present invention. In the figure, a two-port RAM 60 having a bit width equal to or more than the number of scanning lines to be held, a memory control circuit 61, and image latch circuits 62 to 67 are provided. Each image latch circuit is synchronized with a clock. Work. The memory control circuit 61 has the same configuration as the memory control circuit 12 shown in FIG.

In this embodiment, a case where an image of 3 rows and 3 columns is cut out from an image of 8 columns will be described as an example. In this embodiment, two pixels in the same column in the image data on adjacent scanning lines are taken as one word, and a two-port RAM 60 stores sequentially scanned images for two scanning lines. For example, if the pixels in the r-th row and the m-th row are stored in the two-port RAM 60, the operation of the address generation circuit 611 causes the two-port RAM 6 to operate.
Pixels in the same column of the r-th row and the m-th row are read from 0, and the image of the m-th row which is temporally new is latched by the image latch circuit 62. At the same time, the data in the m-th row, which has been latched by the image latch circuit 62, is overwritten in the 2-port RAM 60 together with the pixels in the same column of the n-th row image which is newly input as a sequentially scanned image. You. Here, the image latch circuit 62 holds one cycle or a plurality of cycles of image data, and the address latch circuit 612 supplies the address held in the same cycle as the image latch circuit 62 to the two-port RAM 60 as the write address 118. There is no overlap between read and write for the same address. After the above operation is repeated for one scanning line, the images of the m-th row and the n-th row are stored in the 2-port RAM 60.

Next, FIG. 7 shows the storage state of the progressively scanned image when the line buffer unit is outputting the cut-out image 31. The numbers of the components in the figure are the same as those in FIGS. In FIG. 7, the 2-port RAM 60 initially stores the images of the r-th row and the m-th row, but the data is read out in order from word 0, and now word 5 is read out. Have been. That is, data r6 and m6 are read from the 2-port RAM 60 as upper bits and lower bits. At the same time, the word 4 of the two-port RAM 60 is in the write state, and the data m5 held in the data latch circuit 62 and the newly input data n5 on the nth row are the upper bit and the lower bit. Written as bits. The data m5 is read from the word 4 of the two-port RAM 60 one cycle before. The data read from the 2-port RAM 60 and the data in the n-th row are stored in the image latch circuits 62-6.
7 and 115 to 116 are converted into the cut-out image 31.

Although the above-described configuration cuts out an image of three rows and three columns, it is easy to extend the configuration to cut out a larger image. For example, to enlarge an image in the column direction, a new image latch circuit may be added to each output of the image latch circuits 64, 67, and 116.

In the row direction, generally, p (≧ 2)
In order to cut out the row image, the bit width of the 2-port RAM 60 is set to (p-1) times the bit width of the image data, and the images on the (p-1) successive scanning lines successive in time are read. Hold. Then, an image for (p-1) rows and one column is read out from the address specified by the address generation circuit 611 as one word, and is temporarily stored in the image latch circuit 62.
However, each of the image latch circuits 62 to 64 requires a bit width of (p-2) image data. The image latched by the image latch circuit 62 is used for arithmetic processing, and at the same time, an image obtained by new scanning is added to an image other than the oldest scanning line in the image, and (p-1) row 1
The image of the column is written to the address specified by the address latch circuit 612. With the above configuration and operation, an image of p rows can be easily cut out.

The image processing apparatus configured as described above has an effect that the circuit can be integrated by reducing the RAM capacity for one scanning line as compared with the related art.

Next, the configuration of another embodiment of the image processing apparatus according to the present invention is shown in FIG. FIG. 8 is a configuration diagram of an image processing apparatus that performs the sequential update type processing. FIG. 9A shows a progressively scanned image input to the image processing apparatus.
(2) shows the label data of the processing result.
Three rows, m and n, are shown.

For example, when calculating the n-th row and the third column of the label data, the image processing apparatus of this embodiment refers to the cut-out image 90 of the progressive scan image and the cut-out image 91 of the label data, and the calculated value is The data is written into the line buffer unit 81 for reference of the operation in the next row after the n-th row.

As shown in FIG. 8, the image processing apparatus according to the present embodiment has a memory control circuit 82 and a two-port RAM 85.
And a line buffer unit 81 including image latch circuits 86 to 89 and 810, and image latch circuits 811 to 816.
And an arithmetic unit 817.

The memory control circuit 82 has the same configuration as that shown in FIG. In this embodiment, one scanning line of label data is stored in the two-port RAM 85. For example, the label values M1 to M8 in the m-th row are two-port RA
If it is stored in M85, the memory control circuit 82
The label data of the m-th row is read out from the 2-port RAM 85 by the operation of (1), and at the same time, the label data temporarily held in the image latch circuit 816 is read from the 2-port RAM 85.
Will be overwritten.

At the same time, a sequentially scanned image on the n-th row is newly captured and input to the image latch circuit 811. Here, due to the operation of the memory control circuit 82, read and write do not overlap with respect to the same address.

After the above operation is repeated for one scanning line, the label data of the n-th row is stored in the 2-port RAM 85. The above operation will be described with an example of an image of eight columns. FIG. 10A is a time chart showing the operation of the memory control circuit 82 when processing eight columns of images.
FIG. 10 (2) is a diagram showing the storage state of the 2-port RAM 85 when the line buffer unit 81 is outputting the cut-out image 91 of FIG. 9, and the component numbers are the same as those of FIG. I do. The label data of the m-th line is initially recorded in the 2-port RAM 85, but the data is read out in order from word 0, and word 6 or M7 is currently read. . At the same time, the cut-out image 91 of the label data is input to the arithmetic unit 817 by the operation of the image latch circuits 86 to 89 and 810, and the cut-out image 90 is input to the arithmetic unit 817 by the operation of the image latch circuits 811 to 815.

At the same time, the label data N2 held by the latch circuit 816 is stored in the word 1 of the 2-port RAM 85.
Is written to. As shown in FIG. 10A, a write address 8 is set to enable such memory access.
19 is 6 cycles behind the read address 818. Further, the read operation and the write operation can be continued without providing a one-cycle rest period between the word 7 and the word 0.

As described above, in the image processing apparatus of the present invention, the capacity of the RAM is greatly reduced as compared with the conventional image processing apparatus, and a pause cycle is provided even when the RAM access extends between scanning lines. This has the effect that the sequential update process can be performed at high speed without the need.

Next, another embodiment of the line buffer section in the image processing apparatus of the present invention will be described. FIG. 11 shows another configuration of the line buffer unit. In the figure, a RAM 1105, a memory control circuit 1100, a counter 1114, and an image latch circuit 11081113 having a word number equal to or greater than the number of pixels on all the scanning lines to be held and having a port number greater than the scanning line number by one. , And each image latch circuit operates in synchronization with a clock.

The memory control circuit 1100 includes an address generation circuit 1101, an address latch circuit 1102,
It comprises an address conversion circuit 1103 and an address offset circuit 1104.

In this embodiment, a case where an image of 3 rows and 3 columns is cut out from an image of 8 columns will be described as an example. In this embodiment, the image data on two adjacent scanning lines is connected to form one.
It is stored as a book in the 3-port RAM 1105. For example, assuming that the pixels in the r-th row and the m-th row are stored in the 3-port RAM 1105, the output port O1 and the output port O2 of the 3-port RAM 1105 are operated by the memory control circuit 1100, respectively. Pixels in the same column in the r-th row and the m-th row are read out and passed through the selector 1107 to the image latch circuit 1108
Is input to the image latch circuit 1111. The image latch circuits 1108 to 1113 and the image latch circuits 115 and 116 in FIG. 1 cut out the image 31 in 3 rows and 3 columns in FIG. Here, output port O1 and output port O2
Is designated by the read address input to RA1 and RA2, respectively.

The WA designates a write address, but a new sequential scan image is overwritten on a reference image on a scan line which is the earliest in the images held in the 3-port RAM 1105.

In the memory control circuit 1100, an address generation circuit 1101 counts up from word 0 to words for pixels on two scanning lines, and repeats this periodically. During this time, the read address RA1 accesses the address corresponding to the image on one scanning line twice by the operation of the address conversion circuit 1103, and the read address R2 is another scan by the operation of the address offset circuit 1104. Access the image on the line twice. The write address WA is obtained by holding the address generated by the address generation circuit 1101 for one cycle or a plurality of cycles by the address latch circuit 1102, so that the read address RA1 is always stored.
Unlike the read address RA2, the read and write do not overlap for the same address.

After the above operation is repeated for one scanning line, the images of the m-th row and the n-th row are stored in the 3-port RAM 1105. The counter 1114 counts RA1 or a clock and selects the selector 1 for each scanning line.
The control of 107 is switched. With this operation, the selector 1107
Switches the output O1 and the output O2 for each scanning line, and supplies the image on the old scanning line to the image latch circuit 1111 and the image on the new scanning line to the image latch circuit 1108.

FIG. 12 is a diagram showing the storage state of the sequentially scanned image when the line buffer unit is outputting the cut-out image 31 of FIG. 3, and the numbers of the constituent elements are the same as those of FIGS. The 3-port RAM 1105 initially stores the image on the r-th row and the m-th row, but the data is read out in order from word 0 and word 8 by RA1 and RA2, respectively. Word 5 and word 13 have been read.
Here, the image in the r-th row is supplied to the image latch circuit 1111 and the image in the m-th row is supplied to the image latch circuit 1108 by the selector 1107. Simultaneously 3-port RAM 1105
Is written, and n5 in the nth row is written.

FIG. 13 is a time chart showing an operation state of the memory control circuit 1100 for performing the above access.

In FIG. 13, a clock defines a cycle, and an address generation circuit 1101 sets addresses to 0, 1,.
2,..., 15, 0, 1,. The address conversion circuit 1103 periodically generates RA1 between 0 and 7, and the address offset circuit 1104 periodically generates 8 through 15 with an offset of one scanning line with respect to RA1.

On the other hand, the address latch circuit 1102 periodically generates the write address WA from 0 to 15 one or more cycles later than the address generation circuit 1101. Also, the memory control circuit 1100 can be configured with three synchronous address generating circuits to generate the read addresses RA1, RA2 and the write address WA.

The image processing apparatus constructed as described above has an effect that the circuit can be integrated by reducing the RAM for one scanning line as compared with the conventional one.

Next, another embodiment of the line buffer section in the image processing apparatus of the present invention will be described. FIG. 14 shows another configuration of another embodiment of the line buffer section. In the figure, the line buffer section has a word number equal to or larger than the number of pixels on all the scanning lines to be held, and has one more port than the number of scanning lines.
RAM 1404 and memory control circuit 1400
, And image latch circuits 1405 to 1410, and each image latch circuit operates in synchronization with a clock.

The memory control circuit 1400 includes an address generation circuit 1401, an address generation circuit 1402, and an address latch circuit 1403.

In this embodiment, a case where an image of 3 rows and 3 columns is cut out from an image of 8 columns will be described as an example. In this embodiment, the image data on two adjacent scanning lines is connected to form one.
The book is stored in the 3-port RAM 1404. For example, assuming that the pixels in the r-th row and the m-th row are stored in the 3-port RAM 1404, the operation of the memory control circuit 1400 causes the output port O1 and the output port O2 of the 3-port RAM 1404 to return to r. The pixels in the same column in the row and the m-th row are read out,
The data is input to the image latch circuit 1405 and the image latch circuit 1408. Then, the image 31 of three rows and three columns in FIG. 3 is cut out by the image latch circuits 1405 to 1410 and the image latch circuits 115 and 116 shown in FIG. Here, the output data of the output ports O1 and O2 are designated by the read addresses input to RA1 and RA2, respectively. Also, the WA specifies a write address, but a new progressively scanned image is overwritten on a referenced image on a scan line that is the oldest temporally in the image held in the 3-port RAM 1404.

In the memory control circuit 1400, the address generation circuits 1401 and 1402 count up from the word 0 and the word 8 to the word for the pixels on the two scanning lines, respectively, and repeat this periodically. . During this time,
The address RA1 accesses the address corresponding to the image on the two scanning lines once, and the read address R2 is RA1.
An image on two scanning lines is accessed once, one scanning line later than the other. The write address WA is stored in the address generation circuit 14.
02 generated by the address latch circuit 1403
Are stored for one cycle or a plurality of cycles, so that the read address RA1 or the read address RA
Unlike FIG. 2, read and write do not overlap for the same address.

After the above operation is repeated for one scanning line, the images of the m-th row and the n-th row are stored in the 3-port RAM 1404.

FIG. 15 is an explanatory diagram showing the storage state of the progressively scanned image when the line buffer section is outputting the cut-out image 31 of FIG. 3, and the component numbers are the same as those in FIGS.

The 3-port RAM 1404 stores the r-th row and m
The image of the row is stored, but words 5 and 13 are read by RA1 and RA2, respectively.
At the same time, word 4 of the 3-port RAM 1404 is in a write state, and n5 in the n-th row is written.

FIG. 16 is a time chart showing an operation state of memory control circuit 1400 for performing the above access. In FIG. 16, a clock defines a cycle, and an address generation circuit 1401 sets an address RA1 to 0,
1, 2,..., 7, 8, 9,..., 15, 0, 1,. The address generation circuit 1402 stores the address RA2 in 8, 9, 10,..., 15, 0, 1,.
7, 8, 9,... Occur periodically.

On the other hand, the address latch circuit 1403 periodically generates the write address WA from 0 to 15 one or more cycles later than the address generation circuit 1402.

The memory control circuit 1400 is composed of three synchronous address generation circuits to form a read address RA.
1, RA2 and write address WA can also be generated.

The image processing apparatus configured as described above has an effect that the circuit can be integrated by reducing the RAM for one scanning line as compared with the conventional one.

[0065]

As described above, in the image processing apparatus of the present invention, the RAM capacity for one scanning line can be reduced as compared with the conventional apparatus, and the apparatus can be integrated. Therefore, the reduction effect is greater for a device that processes a large screen.

In the sequential update type processing, the read address and the write address of the RAM are necessarily different in order to write the processing result to the line buffer. However, in the image processing apparatus of the present invention, the write operation on one scanning line is completed. Since it is possible to shift to the read operation on the next scanning line before, there is an effect that high-speed processing can be performed without a pause cycle.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an embodiment of an image processing apparatus according to the present invention.

FIG. 2 is an explanatory diagram showing an image cut out from a sequentially scanned image by the image processing apparatus of the present invention.

FIG. 3 is an explanatory diagram showing a 3-row, 3-column image cut out from an 8-column progressively scanned image by the image processing apparatus of the present invention.

FIG. 4 is an explanatory diagram illustrating a storage state of an image in a line buffer unit of the image processing apparatus illustrated in FIG. 1;

FIG. 5 is a time chart showing an operation state of a memory control circuit of the image processing apparatus shown in FIG. 1;

FIG. 6 is a block diagram showing a configuration of another embodiment of the line buffer unit in the image processing apparatus according to the present invention.

FIG. 7 is an explanatory diagram illustrating a storage state of an image in a line buffer unit illustrated in FIG. 6;

FIG. 8 is a block diagram showing a configuration of another embodiment of the image processing apparatus according to the present invention.

FIG. 9 is an explanatory diagram showing a relationship between an input image and a processing result by the successive update type image processing.

10 is a diagram illustrating an operation state of a memory control circuit of the image processing apparatus illustrated in FIG. 8 and a storage state of a line buffer unit.

FIG. 11 is a block diagram illustrating a configuration of another embodiment of the line buffer unit in the image processing apparatus according to the present invention.

FIG. 12 is an explanatory diagram illustrating a storage state of an image in the line buffer unit illustrated in FIG. 11;

FIG. 13 is a time chart showing an operation state of a memory control circuit in the line buffer unit shown in FIG. 11;

FIG. 14 is a block diagram illustrating a configuration of another embodiment of the line buffer unit in the image processing apparatus according to the present invention.

FIG. 15 is an explanatory diagram illustrating a storage state of an image in the line buffer unit illustrated in FIG. 14;

16 is a time chart showing an operation state of a memory control circuit in the line buffer unit shown in FIG.

FIG. 17 is an explanatory diagram showing a storage state of an image in a line buffer unit of a conventional image processing apparatus.

FIG. 18 is an explanatory diagram showing a 3-row, 3-column image cut out from an 8-column progressively scanned image by a conventional image processing apparatus.

FIG. 19 is an explanatory diagram showing a storage state of an image in a line buffer unit of a conventional sequential update type image processing apparatus.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Line buffer part 12 Memory control circuit 13 Address generation circuit 14 Address latch circuit 15 2 port RAM 16 2 port RAM 17 Image latch circuit 18 Image latch circuit 19 Image latch circuit 110 Image latch circuit 111 Image latch circuit 112 Image Latch circuit 113 Image latch circuit 114 Operation unit 115 Image latch circuit 116 Image latch circuit

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Waka Asada 5-2-1 Omikacho, Hitachi City, Ibaraki Prefecture Inside the Hitachi, Ltd. Omika Plant (72) Inventor Waki Fujiwara 5-chome Omikacho, Hitachi City, Ibaraki Prefecture No. 1 Hitachi, Ltd. Omika Factory (56) References JP-A-1-284980 (JP, A) JP-A-2-28781 (JP, A) JP-A-61-79385 (JP, A) Hei 2-284271 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06T 1/60 G06F 12/00 580 G06T 5/20

Claims (9)

(57) [Claims] A first address for generating a read address;
And a resource generated by the first address generation circuit.
One address from the read address in synchronization with the read address.
Generates a write address delayed by one cycle or multiple cycles
And a read address generated by the first address generation circuit for a different address.
And the second address generation circuit generates
1 or 2 or more 2 in which image data of pixels of a scanning line length capable of simultaneously writing by the written write address is stored.
A port RAM; and a plurality of image latch circuits for temporarily holding image data read from the two-port RAM based on a read address output from the first address generation circuit. Line buffer to be. 2. A RAM having a number of words equal to or greater than the number of pixels on all the scanning lines to be held and having the same number of ports as the number of all the scanning lines to be held. An address generation circuit for generating an address; an address latch circuit for temporarily storing an address generated by the address generation circuit and supplying the write address to the RAM; and an address generated by the address generation circuit for one scan line. An address conversion circuit for converting the read address to a read address, an address offset circuit for generating a read address with an offset of one scanning line with respect to the read address generated by the address conversion circuit, And counting the RAM
What is claimed is: 1. A line buffer comprising: a selector for switching an output destination of image data read out for each scanning line; and a plurality of image latch circuits for temporarily holding image data output from the selector. 3. A RAM having a number of words equal to or greater than the number of pixels on all scanning lines to be held and having the same number of ports as the number of scanning lines to be held, and a RAM for the number of words. A first address generating circuit for periodically generating an address as a read address, and an address delayed by one scanning line from an address generated by the first address generating circuit as a second read address. A second address generation circuit which is periodically generated, and an address which is temporarily stored in the first address generation circuit or the read address generated by the second address generation circuit and is supplied to the RAM as a write address. A line buffer comprising: a latch circuit; and a plurality of image latch circuits for temporarily holding image data read from the RAM. 4. A line buffer unit for storing an image signal on a scanning line read by sequential scanning, one or more image latch circuits for temporarily holding image data input by sequential scanning, and the line buffer And p pixels in a direction perpendicular to the scanning line cut out by the section and the image latch circuit, and q pixels (p and q are integers of 2 or more) in the scanning line direction (p row q
And an arithmetic unit for performing an arithmetic operation on the image of the column.
One or more two-port RAMs for storing image data of pixels of a scanning line length capable of simultaneously performing read and write, and a first address generation for generating a read address of the two-port RAM A second address generating circuit for generating an address delayed by one or more cycles from the read address as a write address in synchronization with the first address generating circuit; and an output from the first address generating circuit. And a plurality of image latch circuits for temporarily holding image data read from the two-port RAM according to the read address. 5. A line buffer for storing an image signal on a scanning line read by sequential scanning, one or more image latch circuits for temporarily holding image data input by sequential scanning, and the line buffer And an arithmetic unit for performing an arithmetic operation on an image of p rows and q columns (where p and q are integers of 2 or more) extracted by the image latch circuit. A two-port RAM for storing image data of pixels of a scanning line length having a bit width of at least twice the bit width of the data, and an address generating circuit for generating a read address of the two-port RAM An address latch circuit for temporarily storing an address generated by the address generation circuit and then supplying it as a write address to the two-port RAM; And a plurality of image latch circuits for temporarily holding image data read from the two-port RAM according to the read address. 6. A line buffer unit for storing image signals on scanning lines read by sequential scanning, one or more image latch circuits for temporarily holding image data input by sequential scanning, and the line buffer And an arithmetic unit for performing arithmetic processing on the image of p rows and q columns cut out by the image latch circuit, and the line buffer unit has a word number equal to or greater than the number of pixels on all the scanning lines to be held. A RAM having the same number of ports as the total number of scanning lines to be held, an address generating circuit for generating addresses for the number of words, and temporarily storing addresses generated by the address generating circuits. An address latch circuit for supplying the RAM as a post-write address, and an address for converting an address generated by the address generation circuit into a read address for one scanning line. Address conversion circuit, an address offset circuit for generating a read address with an offset of one scanning line with respect to the read address generated by the address conversion circuit, and counting the number of addresses or cycles to the RAM.
An image processing apparatus, comprising: a selector for switching an output destination of image data read out for each scanning line; and a plurality of image latch circuits for temporarily holding image data output from the selector. 7. A line buffer unit for storing image signals on scanning lines read by sequential scanning, one or more image latch circuits for temporarily holding image data input by sequential scanning, and the line buffer And an arithmetic unit for performing arithmetic processing on the image of p rows and q columns cut out by the image latch circuit, and the line buffer unit has a word number equal to or greater than the number of pixels on all the scanning lines to be held. A RAM having the same number of ports as the total number of scanning lines to be held, a first address generating circuit for periodically generating addresses corresponding to the number of words as read addresses, A second address generating circuit for periodically generating an address delayed by one scanning line with respect to the address generated by the address generating circuit as a second read address; An address latch circuit for temporarily holding a read address generated by a raw circuit or a second address generation circuit and then supplying the read address to the RAM as a write address; and temporarily holding image data read from the RAM. And a plurality of image latch circuits. 8. A processing result of an image signal on a scanning line read by sequential scanning is stored, and an image of p rows and q columns (however,
a line buffer section for cutting out as p and q are integers of 2 or more), one or more image latch circuits for temporarily holding image data input by sequential scanning, and an image and an image latch for the p rows and q columns An arithmetic unit for performing arithmetic processing on the image of p rows and q columns cut out by the circuit, wherein the line buffer unit is configured to read out a different address.
One or two or more 2-port RAMs for storing image data of pixels of a scanning line length capable of simultaneously performing read and write; an address generation circuit for generating a read address of the 2-port RAM; An address latch circuit for temporarily storing an address generated by the address generation circuit and then supplying the address as a write address to the 2-port RAM; and a read address output from the address generation circuit to read from the 2-port RAM. An image processing apparatus, comprising: a plurality of image latch circuits that temporarily hold read image data. 9. A processing result of an image signal on a scanning line read by sequential scanning is stored and an image of p rows and q columns (however,
a line buffer section for cutting out as p and q are integers of 2 or more), one or more image latch circuits for temporarily holding image data input by sequential scanning, and an image and an image latch for the p rows and q columns An arithmetic unit for performing arithmetic processing on the image of p rows and q columns cut out by the circuit, wherein the line buffer unit has a number of words equal to or greater than the number of pixels on all the scanning lines to be held, and A RAM having the same number of ports as the number of scanning lines, an address generating circuit for generating addresses corresponding to the number of words, and an address generated by the address generating circuit being temporarily stored as a write address. An address latch circuit for supplying to the RAM; an address conversion circuit for converting an address generated by the address generation circuit into a read address for one scanning line; An address offset circuit for generating a read address with an offset of one scan line with respect to the generated read address;
An image processing apparatus, comprising: a selector for switching an output destination of image data read out for each scanning line; and a plurality of image latch circuits for temporarily holding image data output from the selector.