JPS62213488A - Muting circuit - Google Patents

Abstract

PURPOSE:To facilitate integration of titled circuit, to reduce costs of parts and packaging, and to make a television set small in size by constituting all or most of the circuits of logical elements. CONSTITUTION:When a synchronous separation signal 107 is inputted, a pattern matching circuit 103 measures the width of the pulse. In case of judging the said signal as normal, the circuit 103 outputs a pulse 111. Meanwhile, a horizontal self-start running circuit 101 is made operate, by the pulse 111, in synchronization with the horizontal synchronization of a composite video signal as long as a normal horizontal synchronizing signal is present in the composite video signal. When the pulse 111 lacks during a noise period, the circuit 101 outputs a one's own reset pulse 108 so as not to lose the synchronization with the composite video signal of its horizontal synchronization. The pulse 108 is supplied to a counter latch circuit 102, too, to hold the counter-output 109 in a high level. The muting is executed by this output 109.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a muting circuit for a television set, and more particularly to an audio muting circuit using a digital circuit.

[Conventional technology]

A block diagram of an example of a conventional meeting circuit is shown in FIG. In FIG. 2, 201 is a composite video signal, 202
203 is a synchronization separation circuit into which the composite video signal 201 is input;
204 is a synchronous separation signal, 204 is a bandpass filter that inputs the synchronous separation signal 2060, 205 is the output of the bandpass filter 204, 206 is an integration circuit, 207 is the output of the integration circuit 206, 208 is a control signal output section, 209 is a control signal This is the output, the arrow indicates the direction in which the signal travels, and the square area indicates the circuit block. In FIG. 2, when the composite video signal 201 is correctly input, the synchronization signal component is converted into the synchronization separation signal 206 by the synchronization separation circuit 202, and the fundamental frequency component of 15.7 KHz of the synchronization separation signal 206 is extracted by the bandpass filter 204. Then, based on the voltage output 207 obtained by smoothing the output 205 by the integrating circuit 206, the control signal output section 208 outputs a control signal 209 indicating that it is OK to continue outputting the audio. - In the power tube 2 diagram, the reception condition etc. has deteriorated and the composite video signal 2 is incorrect.
If 01 is not input, the waveform of the synchronization separation signal 203 is distorted, and the potential of the output 207 of the integrating circuit 206 is lowered due to a decrease in the component at the fundamental frequency of 15.7 I (Hz). A control signal 209 is output to cut off the output.

[Problem that the invention seeks to solve]

However, in the example shown in Fig. 2, the pantone filter 204 requires a coil and a capacitor, and the integrating circuit 206 requires a capacitor of several microfarads, which cannot be integrated into an IC. Therefore, the entire circuit is constructed from individual components. This has disadvantages in that it increases the component cost and mounting cost, and also increases the circuit volume, which hinders miniaturization of the device.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and provide a low-cost, compact muting circuit.

[Means for solving problems]

The configuration of the present invention includes a pattern matching circuit that discriminates a horizontal synchronization signal from a synchronization separation signal of a composite video signal, a horizontal free-running circuit that operates in synchronization with the horizontal period of the composite video signal, and a self-control circuit of the horizontal free-running circuit. It is characterized in that it has a counter latch circuit to which the reset pulse and the output of the pattern matching circuit are input, and an integrating circuit to which the output of the counter latch circuit is input, and the integrating circuit outputs a control signal.

〔Example〕

The present invention will be explained using examples. FIG. 1 is a block diagram of a muting circuit according to an embodiment of the present invention. In FIG. 1, 101 is a horizontal free-running circuit that operates in synchronization with the horizontal period of the composite video signal and receives the clock, the output of the pattern matching circuit, and a self-reset pulse, and 102 is the output of the horizontal free-running circuit 101. a counter latch circuit that counts self-reset pulses, is reset by the output of the pattern matching circuit 106, and changes its output state when a set value is exceeded; 106 is a pattern matching circuit that discriminates the horizontal synchronization signal from the synchronization separation signal; 104; is the output of the counter launch circuit 102 after removing components that change in a short time (
Integrating circuits, 105 and 106 are horizontal free-running circuits 10, respectively.
1 and a clock that is input to the pattern matching circuit 106 to operate the circuit, 107 is a synchronous separation signal, 108 is a self-reset pulse, 109 is the output of the counter latch circuit,
110 is a control signal output from the integrating circuit 104; 11
1 is the output of the pattern matching circuit 106, the arrow indicates the direction in which the signal advances, and the square area indicates the circuit block.

A digital synchronous signal processing system may have the pattern matching circuit 106 and horizontal free-running circuit 101 shown in FIG. 1, and in this case, they can be used in the muting circuit of the present invention.

The operations of the pattern matching circuit 106 and the horizontal free-running circuit 101 shown in FIG. 1 will be explained using FIG. 3.

In FIG. 3, (A) is the composite video signal, (B) is the synchronization separation signal 107 in FIG. 1, (C) is the output 111 of the pattern matching circuit 106 in FIG. 3 is a timing chart showing the self-reset pulse output 108 of the horizontal free-running circuit 101. FIG.

In FIG. 3, 601 is a horizontal synchronizing signal in the composite video signal, 602 is a luminance signal, and 606 is a period in which the horizontal synchronizing signal and the luminance signal disappear due to noise. In FIG. 3, the synchronization separation signal (B) has a pulse at the horizontal synchronization signal 6010 of the composite video signal (A), but the horizontal synchronization signal of the composite video signal (A) disappears during the noise period 606. The pulse is missing because it was put away.

The pattern matching circuit 106 in FIG. 1 is shown in FIG. 3(B).
When a synchronization separation signal is input, if it is determined that a regular horizontal synchronization signal exists by measuring the pulse width, etc., the output shown by the pulse in FIG. 3(C) is performed. On the other hand, the horizontal free-running circuit 101 in FIG. 1 is synchronized with the horizontal period of the composite video signal by the output 111 of the pattern matching circuit in FIG. However, the noise period 606
If the pattern matching output 111 is missing in Figure 3 (
D) Self-resetting pulse 1 to reset its own circuit
08 to avoid losing synchronization with the horizontal period of the composite video signal.

FIG. 4 is a circuit diagram showing the counter launch circuit of the embodiment shown in FIG. 1, in which the same numbers as in FIG. 1 indicate the same signals;
01 to 409 are 1/2 frequency dividers, φ is a clock input terminal, R is a reset input terminal, Q is connected in series to the output to form a binary counter, 410 is an AND, and 411 is a It is an inverter. In FIG. 4, when the reception condition is good, the pattern matching circuit can distinguish almost all the horizontal synchronization signals of the synchronization separation signal obtained from the composite video signal, and the pattern matching circuit output 11
Since 1 is output every time, the frequency divider 409 maintains the low level.

On the other hand, if the reception condition is poor (or the synchronization separation signal is disturbed and the pattern matching circuit cannot distinguish the horizontal synchronization signal),
The self-reset pulse 108 passes through an AND 410 and is input to the frequency divider 401, and 256 self-reset pulses 1 are generated.
When 08 is input, the output 109 of the frequency divider 409 goes to high level, and the output of the inverter 411 goes to low level, so the self-reset pulse 108 cannot pass through AND 410 from now on, and this state becomes a pattern. It is held until there is an output 111 from the matching circuit.

In this way, when the counter latch circuit determines that it is necessary to execute muting, the output is 1 in the example shown in Figure 4.
09 became a high level, but if the pattern matching output 111 was accidentally input due to noise etc., the output of the counter latch circuit became a low level, and the sound was not output from the TV set until the next time it became a high level. Therefore, to prevent this, it is necessary to ignore instantaneous motion.

Therefore, the component that changes in a short time of the output 109 of the counter latch circuit is removed (a circuit example is shown in FIG. 5. FIG. 5 is a circuit diagram showing an example of the integration circuit 1040 of the embodiment of FIG. , (A) is an example composed of a resistor and a capacitor,
(B) is an example configured with digital elements. In Fig. 5, 501 is a resistor, 502 is a capacitor, 506-5
05 is data type clip flock (hereinafter D-FF)
), 506 to 516 constitute a binary counter with a 1/2 frequency divider, and Dl φ, R, and Q indicate a data input terminal, a clock input terminal, a reset input terminal, and an output terminal, respectively. 514 is exclusive or, 51
5 is an AND, and 516 is a clock that runs the system.

In FIG. 5(A), a resistor 501 and a capacitor 50
If the time constant given by 2 is made several times the time set in the counter launch circuit 102 of the embodiment shown in FIG.
The operation is stabilized because the output 1090 of the counter latch circuit is inverted about once during the set time period, and this does not affect the control signal output 110 of the integrating circuit.

In FIG. 5(B), the exclusive OR 514 resets the frequency dividers 506 to 516 each time the output 109 of the counter launch circuit of the embodiment of FIG. When the condition is stable and maintained for about 12-8 shots of clock 516, AND51
A clock is input to the D-FF 505 through 5, the output 109 of the counter latch circuit is taken in, and a control signal 110 is output. Here, as in FIG. 5(A), 128
By making the starting clock time several times the time set in the counter latch circuit 102 of the embodiment shown in FIG. 1, the control signal output will not change frequently and the circuit operation will be stabilized.

Also, to configure an integrating circuit with digital elements, see Figure 5 (
Instead of using a counter as in B), a shift register can also be used.

Further, in order to stabilize the circuit operation, it is possible to easily make it unnecessary to perform muting on the output 109 of the counter latch circuit only when the output of the pattern matching circuit that is equal to or greater than a set value is input for a certain period of time.

〔effect〕

As is clear from the above description, the circuit of the present invention is entirely composed of
Alternatively, since it can be constructed mostly from logic elements, it is easy to integrate it into an IC, which reduces component costs and mounting costs, and also allows for miniaturization of the television set.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a muting circuit according to an embodiment of the present invention, Fig. 2 is a block diagram of a conventional muting circuit, and Fig. 3 shows (A) a synthesized video signal and (B) synchronous separation. Signals, (C) and (D) are timing charts showing the outputs of the pattern matching circuit and horizontal free-running circuit of the embodiment shown in FIG. 1, respectively, and FIG. 4 is the counter latch of the embodiment shown in FIG. FIG. 5 is a circuit diagram showing the circuit. FIG. 5 is a circuit diagram of the integrating circuit of the embodiment shown in FIG. 1, in which (A) is an analog circuit and (B) is a digital circuit. 101...Horizontal free running circuit, 102...Counter latch circuit, 103...
...Pattern matching circuit, 104...
Integration circuit, 108...Self-reset pulse, 109...
... Counter latch circuit output, 110...
- Control signal, 111...Output of the pattern matching circuit. Figure 1 Figure 3

Claims (1)

[Claims] A muting circuit that controls audio output using a control signal includes a pattern matching circuit that determines a horizontal synchronization signal from a synchronization separation signal of a composite video signal, and a horizontal free-running circuit that operates in synchronization with the horizontal period of the composite video signal. It has a counter latch circuit to which the self-resetting pulse of the horizontal free-running circuit and the output of the pattern matching circuit are input, and an integrating circuit to which the output of the counter latch circuit is input, and the integrating circuit outputs a control signal. Features a muting circuit.