JPS62206977A - High definition digital television receiver - Google Patents

Abstract

PURPOSE:To reduce a circuit scale and to decrease a cost by changing over an address signal to control the address of an image memory in a receiver in accordance with respective transmitting system and sharing the image memory. CONSTITUTION:Into a terminal 1, the MUSE signal of the high definition television signal of a base band is inputted and a signal 3, which comes to be digital data by an A/D converter 2, is inputted to a selector circuit 61. In the same way, an NTSC signal is inputted to a terminal 41 and inputted through an A/D converter 42 to a selector circuit 61. When the MUSE signal is selected by an M/N signal 69 to change over the MUSE signal and the NTSC signal, an address generating circuit 67 generates an address signal 66 suitable to the MUSE signal, and when the NTSC signal is selected, an address generating device 67 generates the address signal 66 suitable to the NTSC signal. Thus, common image memories 6 and 8 are controlled.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field to Which the Invention Pertains] The present invention relates to a high-definition digital television receiver capable of receiving two types of television signals.

[Background technology of the invention]

In recent years, there has been an increasing demand for higher quality television images, and in response to this demand, high-definition televisions are attracting attention.

The image quality of this high-definition television is comparable to that of 35-inch film, but its luminance signal band is about 20 MHz, which is about five times that of the current NTSC system (4.2 MHz). For this reason, transmission using current wireless transmission channels is impossible, so a method has been proposed in which the signal band is compressed and transmitted on the transmitting side. In this case, the receiving side requires a function to decode the compressed signal, but this function is generally achieved by digital signal processing including an image memory.

One of the above compression methods is the MUSE method (NHK
In the MUSE system, the frame period is 3QHz and the number of scanning lines is 1.
125 pieces/frame. Ink-race (interlaced scanning) of two fields per frame is performed, and an offset sub-sampling method as shown in FIG. 6 is adopted. That is, in the nth field, sample data marked with a circle in the figure is transmitted, and in each of the n+1st, n+2nd, and n+3rd fields, sample data marked with 0, -, and - is transmitted, respectively. Therefore, after 4 fields, the position of the sample data in the n+4° field is again marked with a circle. In this case, if it is a still image on the receiving side.

It becomes possible to reproduce an image using all the sample data in FIG.

Next, FIG. 7 shows a simple configuration of the MUSE signal receiving aircraft. A baseband MUSE signal is input to an input terminal 1, digitized by an A/D converter 2 having a sample rate of 16.2 MHz, and input as a digital signal 3 to a selector circuit 4. When this digital signal 3 has a sample phase marked with ○ in FIG. It is obtained by alternately accumulating and interpolating the sample data of

twice the sample rate of A/D converter 2, i.e. 32.4
A digital signal 9 (hereinafter this signal will be referred to as a 2Fi-1-4Fi signal) having a sample rate of MHz is also input.

In the selector circuit 4, among the sample data of No. 12 No. 4,
The data 4 fields ago and the sample data of digital signal 3 (data of the current field) are exchanged and output. Therefore, the output signal 5 of the selector circuit 4 is a signal having a sample rate of 32.4 MHz (hereinafter referred to as oFi +
2F'i signal). This digital signal 5 is delayed by one field by the image memory 6 and outputted, and the output signal 7 is further delayed by one field by the image memory 8 and outputted. In this way, digital/
The I/signal 7 is a signal in which data from one field before and data from three fields before are alternately accumulated and interpolated (hereinafter, this signal will be referred to as an IFi 4-3Fi signal).

The digital signal 9 becomes a ZFi +4Fi signal in which data from two fields before and four fields before are accumulated and interpolated.

The Qll't + 2Fi signal 5 and IFi + 3F
i' signal 7 is.

The signal is input to the still image signal processing circuit 12, where, as described above, the signal is processed and output using all the sample data three fields before, starting from the sample data of the current field. However, of course, the movement part of the 6 images (
When this is applied to videos (hereinafter referred to as moving images), multi-line blurring occurs. Therefore, for moving images, it is necessary to reproduce the image using only the sample data of the current field, and to detect moving parts to determine whether the image is a still image or a moving image. Therefore, in FIG. 2, the data of the current field is extracted from the output signal 5 of the selector circuit 4 by the sub-sampling circuit 16, and the output signal 32 is supplied to the moving image signal processing circuit 14.

Interpolate and output data. That is, each processing circuit 12
．． The output signals 13 and 15 of 14 are led to a selector circuit 29, and outputted by switching with an output signal (referred to as a motion signal) 19 of a moving portion detection circuit 18.

The motion signal 19 is determined by the absolute value of the difference between seven frames. However, in the MUSE method.

If you take the difference between frames, the positions of the sample data marked with O and marks are different, even if it is a still image.

There is a possibility that a difference value may appear. However, in the case of 4 fields, the positions of the sample data coincide once, and the above-mentioned phenomenon does not occur. Therefore, the motion detection circuit 18 in FIG. 7 generates a motion partial signal based on the difference between two frames. . That is, the detection circuit 18 receives the OF+2Fi signal 5 and the 2Fi+4Fi signal 9.

The MUSE signal is obtained by time-division multiplexing the luminance signal Y and the color difference signal C. Even if the output signal 20 of the selector circuit 29 has three signals, it is a one-time division multiplexed signal, so it is decoded by the temporary coding circuit 21 into digital data of GH.

R signal 22 . which is the output of the decoding circuit 21 . G signal Z3.
The B signals 24 are converted into analog data by D converters δ, 26 and 27, respectively, and input to a part of the monitor.

This is convenient for MUSg signal receivers.

Memory is required to store images for 4 fields.
This capacity is 8.6Mbit (16,2MH2X 47
4-k)"X8bit ÷60Hz) (Equivalent to 256K RAM 34 chips)1
The capacity of image memory 6 and image memory 8 is 4.3 Mb each.
It becomes it.

On the other hand, even in the current NTSC system, one image memory is used to separate the luminance signal Y and one color difference signal C (hereinafter referred to as YC separation), thereby achieving cross color.

It is known that it is possible to reproduce images without cross-luminance. In the NTSC system.

Since the color subcarrier is inverted every frame, Y+C in one frame and y/c/ in the next frame.
A composite signal is being transmitted. In a still image, y=
Since y', c=c', the luminance signal is obtained by the sum of frames, and the color difference signal is obtained by the difference between frames.

FIG. 9 shows a simple configuration of an NTSC television receiver equipped with such a one-image memory. A baseband NTSC analog signal is input to the input terminal 41, and converted to digital data by the A/D converter string.1 image memory 4
Enter 41 items. This image memory has a capacity to store one frame of NTSC signals, and outputs a signal 45 delayed by one frame. This capacity is A/D
When the sampling rate is four times the color subcarrier (14.3M output) and 8-bit quantization is performed by the converter 42,
14.3÷60 (Hz) x 2 (field)
×8 #3.8 (Mbi, 256KR, λ
Equivalent to M15 chip. The digital signals 43 and 6 are
The signal is input to the NTSC signal processing circuit 46, and YC separation adapted to the movement of one image is performed. That is, by performing moving part detection.

If it is a still image, YC separation is performed using the method described above, and if it is a moving image, YC separation is performed within the frame, and the resulting luminance signal Y and color difference signal C are used.

It is converted into an RGB signal and output.

Each signal 47, 48, 49 of the above GB is D
The data is converted into analog data by the /A converters 50 , 51 , and 52 and input to the monitor 53 . This method of separating input video signals into luminance signals and chrominance signals based on the sum and difference is limited to still images, and the Y
An ideal Y without mutual leakage of luminance signals and color difference signals (cross color, cross luminance), which cannot be solved by C separation or YC separation using a comb filter.
C separation method.

[Problems with background technology]

As mentioned above, high-definition television provides a rich sense of reality that conventional televisions do not have.

By equipping an NTSC signal receiver with a single image memory, it becomes possible to reproduce images of even higher quality. In the near future, high-definition television signals such as the MU8113 system will be broadcast.

A receiver capable of receiving both television signals is required. Moreover, it would be costly to simply install each signal processing circuit, ie, the circuit shown in FIG. 7 and the circuit shown in FIG. 8, independently in such a receiver.

This will lead to an increase in circuit scale.

[Purpose of the invention]

The present invention has been made to meet the above-mentioned requirements and provides a television receiver capable of receiving pre-visit signals of a plurality of different transmission systems.

To provide a television receiver having a small circuit scale and low cost.

[Summary of the invention]

The present invention provides an address signal for controlling the address of an image memory in the receiver in a television receiver capable of receiving television signals of a plurality of different transmission methods.
By switching according to each transmission method and sharing the image memory for television signal numbers of various transmission methods, it is possible to reduce the size of one circuit and reduce costs.

[Embodiments of the invention]

Embodiments of the television receiver according to the present invention will be described in detail below with reference to the two drawings. In the description, a MUSB signal is used as an example of a high-definition television signal, and an NTSC signal is used as an example of a current television signal. First, a first embodiment will be described using FIG. 1. In the figure, a baseband MUSE signal is input to a terminal 1, and a signal 3 converted into digital data by an A/D converter 2 is input to a selector circuit 61. Similarly, an NTSC signal is input to the terminal 41 and input to the selector circuit 61 via the A/D converter 42. Also, terminal 6
A signal (M/'N signal) for switching between the MUSE signal and the NTSC signal is input to the selector circuit 61.
/N signal 69, MUSB signal 3 and NTSC
The signal 43 is switched and output. Below, M/N signal 69
The configuration of FIG. 4 will be explained separately for cases in which the signal selected by is a MULB signal and an NTSC signal.

When the MUSE signal is selected by the M/N signal 69, the selector circuit 70 selects the MUSE signal according to the M/N signal 69.

The timing signal 71 output from the MU8E timing generation circuit 73 is selected. In the address generation circuit 67, the output signal 68 of the selector circuit 70 causes the MUSE
It generates an address signal group suitable for the signal and controls the 1-picture memory 6 and the 1-picture memory 8. Therefore.

The operation of each image memory 6.8 in this case is exactly the same as the conventional example shown in FIG. Also.

Similarly to the conventional example, the selector circuit 4 also performs an operation of exchanging the sample data of four fields before with the input sample data of the current field.

In this way, the MUSB signal processing circuit 30 in FIG. 1 receives the OFi + 2Fi signal 64 and xFi + 3F
i signal 65 and.

A 2Fi+4Fi signal 75 is input. The configuration of the MUSE signal processing circuit is the same as that of the broken line block blade in FIG. 7, and outputs RGB digital data. K
Each of the GB digital data is converted into an analog signal by a DA converter 5.26.27 and input to the monitor column.

Next, when the NTSC signal is selected by the M/N signal 69, the selector circuit 70 outputs the output signal 72 of the NTSC timing generation circuit 74 according to the M/N signal 69.
Select. In the address generator 67, the selector circuit 7
An output signal 68 of 0 generates an address signal 66 suitable for NTSC signals.

MUSE signal 3 is converted to 16.2MHz by AD converter 2
The output of the selector circuit 4 is □Fi +2 because it is interpolated alternately with the sample data two fields before by the selector circuit 4.
The Fi signal has a sampling rate of 32.4 M) Iz. Therefore, when stored in image memory 6.8, 1
The number of samples in the horizontal period is 960 (32,4(Mlh
) ÷ (1125X 30 [:out])) sample, 1 field period is 540000 (960X 11
25÷2) becomes a sample. However, if the NT8C signal is sampled by the A/D converter 42 at four times the color subcarrier rac.

As will be described later, the selector circuit 4 interpolates the data alternately with sample data two fields before.

It has a sample rate of 8 times fsc, or 28.6 MHz. Therefore, when stored in 0 image memory 6.8, the number of samples in one horizontal period is 1820 (2B, 6C
MHz) +15.75 (KHz) ) f yp/
l/, l 7 e, Q/ period is 504000 (
1820X 525÷2) becomes a sample. in this way.

The number of samples is different for both one horizontal period and one field period. According to MULE signal, NTSC signal.

This is the reason why the address control signal 66 of the address generator 67 is controlled by the timing signal 68 which is the output of the selector circuit 70.

The operation of the selector circuit 4 is the same as the operation of the same circuit 4 when the MUSE signal is input.
2F with sample data before the field interpolated alternately
i'-)-4Fi' (2Fi+4F with MULB signal
Corresponding to the i notation, in NT8C it is 2F1 +
It will be written as 4Ft. ) Of the signal 4, the sample data of four fields before is replaced with the sample data OFi signal 63 of the current field, which is the output of the selector circuit 61, and is output. The image memory 6 outputs the output QFt + 2F1 signal B of the selector circuit 4 with a delay of one field, and the 1 image memory 8 outputs the output IF of the image memory 6.
The k'+3Fi' signal 65 is further delayed by one field and output. Therefore, the signal 75 is 2Fi' +
This becomes a 4Fi' signal.

Here, the storage capacity of the image memory 6.8 may be exactly the same as that of the image memory 6.8 shown in FIG.

When an NTSC signal is sampled at 4 fsa, the sample data for 4 fields is 955,500 (3,5
8 (MHz) x 4 ÷ 60 (Hz) x 4 [field cosample.

For MUSB signal, 1080000 (16,2(M
Hz) -4-60 (Hz) x 4 [field]) samples. The sum of the storage capacities of image memories 6 and 8 is M
Because it is possible to store 4 fields of ULB signals 4
NT8 sampled with fat and quantized with 8 bits
It is naturally possible to store the C signal for four fields. Also, the operating speed of 1 image memory 6.8 is MUS
In the case of E signal, as mentioned above, 32.4MHz, N
In the case of the TSC signal, the frequency is 28.6 MHz, so there is no problem considering the operating speed.

Next, the □Ft +2Ft signal 64 is sent to the 1 separation circuit 76
As a result, a signal 77 of only the current field and a signal 78 of two fields before, ie, one frame before, are separated and output.

In this way, if we look at the broken line block 79 in Figure K1 as one function, when the NTSC signal is selected by the M/N signal 69, it will perform a completely fine operation as in the broken line block 79 in Figure 8. . In addition.

The operations after the NTSC signal processing circuit 46 are the same as those shown in FIG. 8, so the explanation will be omitted.

FIG. 2 shows a second embodiment. The difference from FIG. 1 is only in the broken block 84, so this part will be explained and the rest will be omitted.

The separation circuit 76 receives an NTSC signal (
OFi'+2Fi') 64 is input, and the same circuit 76
Each is separated and output. Therefore, the signal 77 is the sample data of the current field, and the signal 78 is the sample data of the previous field, that is, the previous frame. On the other hand, sub-sample circuit 81! Here, an NTSC signal (2F!+4Fi) 75 in which each sample data of 2 fields before and 4 fields before is interpolated alternately is input, and in the same circuit 81, the sample data of 4 fields before and 4 fields before are interpolated alternately.
Output only the sample data before the frame. Therefore,
In the NT8C@ processing circuit 83, the current frame and
Signal processing can be performed using not only sample data from one frame before, but also sample data from two frames before.

Here, the significance of being able to use sample data two frames before will be explained. As mentioned in the technical background, the ideal Y
C separation can be carried out. However, this only applies to still images and not to moving images. Therefore, means for detecting moving parts is required. The motion signal that is the output of this means is basically obtained from the absolute value signal of the difference between frames, but if you simply take the difference between each frame, errors will occur due to the inversion of the subcarrier of one color for each frame. arise. This will be explained below using a formula. The luminance signal is written as Y9, and the color signal is written as C. In a certain frame, Y, + CG signals are transmitted, part 1
Assume that the previous frame was Y, -C1. Here, if the true movement is +ΔY and +ΔC for Y and C, respectively, y0
=y, +Δy, C, ==C1+ΔC0, so it is the absolute value signal of the difference between one frame.

lYt Ct (Yo Co) l is as follows.

IYs et (Yo 'o)I=lΔY+2C
0+ΔC1...(1) The required signal is 1ΔY+ΔC1, but in equation 1 (1), there is no movement, that is, ΔY=ΔC=0
Even so, a difference value of 2co will appear. However, the one-color subcarrier has the same phase between two frames. The signal 2 frames ago is Y! + Ct,
Assuming that the movement between two frames is ΔY[ΔC', use the same formula as in equation (1).

I y, -4-c, -(Y6+CO] = lΔY'+Δc/ + ......(2), and 1 equation (1)
An extra term such as 2C0 is not included.

From the above, if we detect moving parts using the difference between two frames, we can achieve highly accurate detection.
Being able to use sample data from two frames ago is very effective for the NT8C signal processing circuit 83.

A third embodiment is shown in FIG. In this figure, only the broken line block 79 in FIG. 1 is shown, and the configuration of other parts is completely the same as that in FIG. 1, and therefore will be omitted.

The terminal 91 receives the output signal 63 of the selector circuit 61 shown in FIG.
enters. The signal 63 is the capacity J or 1 of the image memory 94.
．． Equal to the sum of the capacities of image memories 6 and 8 shown in Figure 1.

As shown in the address map shown in Figure 4, each
It is divided into four parts each having a capacity of one field (approximately 2.2 Mbtt = 270 bytes). This operation will be explained using FIG. 5.

FIG. 5 is a time chart of the image memory 94.

n from top, n+1. fl+2. n+3 indicates the field number, QFi -4Fi is the input data, that is, the currently input sample data is OFi,
2F if the sample data is 2 fields earlier than that
Indicates i. Also, AR is reading from part A, and BW is reading from part A.
Indicates writing to the part. Now, if data is written in the part A of FIG. 4, the data of four fields before is stored in the part for one person. Therefore, this data is first read (AR), and the input data is written at the next timing (Aw). After that, data is read from the part D where the data of one field before is stored (DB), and then the data of the previous field is read.

Data from three fields ago is stored. Data is read from portions C and B (CR, BR). In the next field, write data in part B (Fig. 5 n+
1). In the next field, data is written in C1, and in the next field, data is written in D (n+2 in Figure 8).
．． n+3). Then, in the next field, return to n and repeat this process.

As described above, when one sample data is input to the image memory 94, four sample data 1 to 4 fields before that sample data are serially output. The distributor 95 receives this serial data signal 109
is converted in parallel to sample data for each shift 1 to 4 fields earlier.

Therefore, the output signal % is the sample data of one field before,
The output signal 97 is the sample data of two fields before, the output signal 98 is the sample data of three fields before, and the output signal 99 is the sample data of four fields before. The selector circuit 100 receives a signal θ which is sample data of the current field, and sample data two fields before.

A signal 97 is input to the selector circuit 100.

Two sample data are interpolated and output alternately.

Therefore, the output signal - of selector circuit 100 becomes the OPi + 2Fi signal, which is equal to signal 64 in FIG. Similarly, in the selector circuit 101, the signal 96 from one field before and the signal 98 from three fields before are input, and are alternately interpolated and output (lFi -) - 3Fi signal). Signal 97 in front.

Alternately interpolates and outputs the signal part before 4 fields (2
Fi+4F1 signal). Therefore, terminals 103, 104.1
Each signal appearing at terminals 106, 107, and 108 is a signal equivalent to the signal with the same number in FIG. This becomes the sample data of the claim, 1 frame before, and 27 frames before, and becomes a signal to the NTSC (No. 1 processing circuit 83).

The input signal θ of the address generator 93 is a MUSE signal.

Regardless of the NTSC signal, the address of the one-image memory 94 is basically controlled at the timing shown in FIG. Related to this idea. MUSE signal.

Address control corresponding to the NTSC signal is performed by switching the timing signal section input to the address generator 93, just as in the first embodiment and the 1g2 embodiment, and the structure of the block 110 shown by the broken line is as follows.

It is exactly the same as Fig. 1 and Fig. #2.

In each of the embodiments described above, the television signals of a plurality of different transmission systems are MUSE signals and NTSC signals. TVSILON signal (IEICE 2 communication system study group material C88
4-7), the current system PAL signal, SEC
AM (also about issue I etc.)

It is clear that the present invention can be effectively applied.

〔Effect of the invention〕

As explained above, the transmission TV Chiron signal.

In the case of a subsampled high-definition television signal,
By controlling the address of the image memory provided in the television receiver according to the case of interlaced standard television signals, the conventionally independent image memory can be used for one television signal. It becomes possible to share the circuit, and as a result, the cost is low and the scale of one circuit is small.

It is possible to obtain a high-quality digital television receiver capable of receiving television signals of an image transmission system.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a television receiver according to a first embodiment of the invention, and FIG. 2 is a circuit diagram of a television receiver according to a second embodiment of the invention. FIG. 3 is a circuit configuration diagram of a television receiver according to a third embodiment of the present invention, FIG. 4 is a schematic diagram showing an address map of an image memory forming a part of the above g3 embodiment, and FIG. The figure is also a schematic diagram showing the time chart of the address of the image memory, FIG. 6 is a schematic diagram showing the sample pattern in the offset sub-sample transmission method, and FIG.
FIG. 8 is a simplified configuration diagram of a television signal receiver according to the NTSC system equipped with an image memory. 6.8.94... Image memory. 30...MUSF) signal processing circuit. 46.83...NTSC signal processing circuit. 61...Selector circuit. 67, 93...Address generator. 69...Switching selection signal (M/N signal). 70...Selector circuit. 73...MUSB timing generation circuit. 74...NTSC timing generation circuit. Agent Patent Attorney Nori Ken Chika Hiroshi Ujiji Figure 3 Figure 5-11-Moo--) ---D-----)--I]-
−−−−１−−−−W−−−−O−−−Kaiichi convex−+−−
--Figure 6

Claims (1)

[Claims] a selector circuit that receives a subsampled first digital television signal and an interlaced second digital television signal and selectively outputs them according to a switching selection signal; and an output of the selector circuit. an image memory for accumulating and interpolating an image, and an address signal for controlling the first and second image memories suitable for each of the first and second digital television signals, the image memory being switched in response to the switching selection signal. a first video signal processing circuit for processing each of the first and second digital television signals to which the interpolation output of the image memory is supplied; A high-definition digital television receiver comprising a second video signal processing circuit.