JPS62185177A - Test system - Google Patents

Abstract

PURPOSE:To facilitate the composing of a program by a user, by decoding a condition branching order to a pattern generator to generate a dummy cycle. CONSTITUTION:When a control signal CT4 is applied to a clock control circuit 19, a control signal CT5 ordering the generation of a dummy rate signal PATE is outputted to a timing generator 1 and a control signal CT6 holding output data is outputted to a formatter 4 and, further, a control signal CT7 prohibiting comparing operation is outputted to a comparator 7. The circuit 19 prohibits the sending-out of signals CLK0, 1 to pipeline registers 8, 17 during a dummy cycle and sends out a signal CLK2 to a fail memory 14. The pattern generator takes the comparing data C-OUT from the comparator 7 in the memory 14 during the dummy cycle to judge the comparing result and generates the next address according to said result. Therefore, the timings of the signal F-CLK and signal STRB from the generator 1 are set on the basis of a program but, because it is unnecessary to consider the necessary time carrying out a condition branching order, a program can be easily composed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an improvement in a test system driven by a program including conditional branch instructions.

[Prior Art] FIG. 3 is a block diagram showing an example of a main part of a conventional LSI destination device. In Fig. 3, &N, 1 is a timing generator (hereinafter referred to as TG), and a signal RATE of a predetermined period, which is the basic period of a series of measurements, is applied to the test object (hereinafter referred to as DUT) 2. Inlet cover turn D-
It generates various timing signals such as a format clock F-CLK synchronized with the rate signal RATE for creating the timing of IN, and a strobe 5TRB for capturing the response pattern D-OUT output from DLIT2. 3 is a pattern generator (hereinafter referred to as PG), which is programmed by the user and generates a predetermined test pattern PAT, ? for measuring the DUT'2 synchronized with the signal RATE. j and an expected pattern EXPI- corresponding to the test pattern FAT. 4 is a formatter (hereinafter referred to as FMT), which changes the test pattern PAT applied from PO2 by the format clock F-CLK applied from TGl. Test pattern PAT 7 modulated by this FMT4
is converted to a predetermined voltage level by the driver 5 and applied to the CUT 2 as a post-input cover turn D-IN. D
U"2 outputs a response pattern D-OUT corresponding to the added input cover turn DIN. This response pattern D
-OLJT is converted into a digital signal by an analog comparator 6. The converted digital signal is passed through a digital comparator (
(hereinafter referred to as CMP) 7. CMP7 is P
The expected pattern EXPT applied from O2 is compared with the digital signal corresponding to the response pattern D-OUT, and comparison data C-0UT is output to PO2. Note that the expected pattern EXPT is applied to the CMP7 via a delay circuit DLA that provides a predetermined delay time to match the timing at which the response pattern D-OLIT corresponding to the test pattern FAT is latched by the CMP7, and is applied to the strobe 5TR.
B is the response pattern D-OUT and the expected pattern EX
It is added to CMP7 via a delay circuit DLB which provides a predetermined delay time to match the timing of PT.

FIG. 4 is a block diagram showing a specific example of the conventional PO2. In FIG. 4, 8 is a vibe line register (hereinafter referred to as PLR). 9 is a micro memory (hereinafter referred to as MM) in which a micro program programmed by Needy is stored.
The instruction INS read from TGl
are sequentially captured according to the rate signal RATE applied to the data. The instruction INS taken into this PLR8 is processed by an instruction decoder (hereinafter referred to as I
(referred to as D)10. Address multiplexer (hereinafter referred to as AMU)
X) 112 is added to other circuits (not shown).

The decode signal of ID10 is processed by condition multiplexer 1 (hereinafter referred to as CMUX) 12 and selection logic (
(hereinafter referred to as SL) 13, control signals CTI and CT, respectively.
Added as 2. A plurality of condition data including the output data F-OUT of the fail memory (hereinafter referred to as FM) 14 are added to the CMUX 12, and predetermined condition data is sent to 5L1 according to the control signal CT1.
Selectively output to 3. 5L13 selects pits of condition data selectively added from CMUX12 according to control signal CT2, and then is added to AMLJXll as a control signal CT3. AMUXll is 5L
The pattern address data P-AD is selectively outputted in accordance with the control signal CT3 applied from 13. AMtJ
Xll has instructions INS from PI R8.
At the same time, the output of the address incrementer 15 that increments the address of the pattern address data P-AD of the eight MLJX11 by 1 is also added. The pattern address data P-AD is MM9. F,,Ml
4. It is added to an address incrementer 15 and a pattern memory (hereinafter referred to as PM) 16. The MM9 outputs a predetermined instruction INS to be executed in the next step according to the pattern address data P-AD.
Output to R8. FM14 converts the output data C-0UT of CMP7 into corresponding pattern address data P-AD according to the rate signal RA-rE applied from Q1.
CMP7 at that time.
output data C-0LJT to the CMUX12.

PM16 outputs a predetermined test pattern FAT and expected pattern EX according to pattern address data P-AD.
The pattern data PD with the PT integrated is output to the PLR 17.

The pattern data PD read out from PM16 is applied to PLR17 from rate signal RA received from TG1.
'T' is captured sequentially according to E. This PLR17
A part of the pattern data PD taken in is outputted to the FMT4 as a test pattern PAT, and the other part is outputted to the CMP7 as an expected pattern EXPT. Reference numeral 18 denotes an initial address register in which address data for setting each part to an initial state when the power is turned on is stored.

By the way, in such a groove formation, the response pattern D-OUT output from DLJT2 is the same as the Akira Samurai pattern EXP.
The pattern program may have to be branched depending on whether T matches (pass) or does not match (fail).

It is desirable to branch such a program in the same way as the pattern comparison in order to output without dummy cycles, but in this case, the following restrictions will be imposed on the test: .

In other words, the test pattern PA' output from PO2
r is FMT4. The strobe 5TRB, which is the timing to capture data, must be delayed according to the time Ta until it is applied to the DUT 2 via the driver 5 and the time Tb until the response pattern D-OUT output from the DLJT 2 is captured into the CMP 7. Must be. In addition, the comparison data C-0UT of CMP7, which is output after passing the time Tc shuttle after strobe ST R13 is applied, is
2(7)FM 14. CMUX 12.8113+t
lJ: A time Td is required until the data is established as data latched in the PM 16 via the AMUx11.

As is clear from this 1, in order to perform program branching and pattern comparison in the same cycle, the strobe S
These times (Ta + T b + - TC
-1-Td).

FIG. 5 is a timing chart for explaining the operation of the circuit configured in this manner. In Figure 5, (
(a) shows the rate signal RA TE output from TGl, (b) shows the pattern data PD output from PM16, (c) shows the format clock F-CLK output from TGl, (d ) indicates strobe 5TRB output from TG't, (l is 0UT2
(f) shows the input cover turn D-IN, and (f) shows the input cover turn D-IN.
-2 response pattern D-OUT, (9) shows CMP
The response pattern D-OUT” is latched to 7, and (
h) shows the strobe STRB' applied to CMP7 via the delay circuit DLB, and (+> shows comparison data C-0LJT applied from CMP7 to PO2.

In FIG. 5, time 1. rate signal RA from TGl at
At the same time as TE is output, pattern data PD such as P G a frs is output. After that, TGI at time t2
A format clock F-CLK is output from. Then, at time 1, when time Ta has elapsed from time t2. An input cover turn D-IN corresponding to the lever format clock F-CLK is applied from the FMT 4 to the CUT 2 via the driver 5.

Here, the time Ta is the test pattern FAT in CUT2.
It corresponds to the driver system delay time that adds . Response time T of 0UT2 after input cover turn D-IN is applied
At time t4 when r has elapsed, response pattern D- is sent from DUT2.
OUT is output.

Subsequently, at time t5 when response pattern D-0 (JT is output), strobe 5TRB is output from TGl.

On the other hand, the response pattern D-OUT output from DUT2
CMP7 at time t6 when time tb has elapsed from time t4.
is radiated to. Here, the time Tb is D U 1'
This corresponds to the delay time of the comparator system that adds the response pattern D-OUT from 2 to CMP7. And time t
5 to the time set by the delay circuit DLB (Ta+T
At time t7 when b) has elapsed, strobe 5TR is applied to CMP7.
B' is added. Comparison data C-0U'l- from CMP7 is the time when time TO has passed since time t7.
is output to PO2. Here, the time TO is the comparison data c-our after the strobe 5TRB' is added.
This corresponds to the delay time until it is added to PO2.

Furthermore, the next rate signal RATE rises at time 1g when the time Td required for processing a predetermined branch instruction at PO2 has elapsed from time t8 according to comparison data C-0UT.

Here, knee is the format clock [nee CL
K J5 and STL]-B5TRB timing
Set by 1 gram. At this point, the user calculates the above-mentioned time (T) required to execute the program's conditional branch instruction.
a −+−T b 1 T c + T d ) must be carefully set each time, which makes it complicated.

[Problems to be Solved by the Invention] The present invention has been made with attention to these points, and its purpose is to reduce the time constraints associated with the execution of conditional branch instructions in a program by the user's program settings. Our goal is to provide a test system that can solve problems without causing problems.

Means for Solving the Problems] The present invention achieves the above object by adding a test pattern to a test pattern from a pattern generator according to a program including a conditional branch instruction, and thereby generating a response pattern and a test pattern. The expected pattern output from the pattern generator corresponding to the test pattern is added to the comparator, these response patterns and the expected pattern are compared, and the program's conditional branch instructions are selectively executed depending on the comparison result. The constructed test system is characterized in that a part of the pattern generator is provided with means for decoding a conditional branch instruction of a program to generate a dummy cycle.

[Example] Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing essential parts of an embodiment of the present invention, and the same parts as in FIGS. 3 and 4 are given the same reference numerals. In FIG. 1, one is a clock control circuit (hereinafter referred to as CCTL).

This CCTL19 has a TG1 power daily 5 rate signal RAT.
E is added, and a control signal CT4 indicating that a conditional branch instruction has been decoded from ID10 is added. When the control (ffi Q CT 4 is applied), the CCTL 19 outputs a control signal CT5 that instructs the TGl to generate a dummy rate signal RATE, and outputs a control rn signal C1' 6 for holding the output data to the FMT 4. , outputs a control l signal CT7 to CMP7 to prohibit the comparison operation. Also, CCTL19 outputs P during the dummy cycle.
Sending of clock CLKO to LR8 and sending of clock CLK1 to PLR17 is prohibited, and clock CLK2 is sent only to FM14.

As a result, PO2 takes in the comparison gate C-0UT outputted from CMP7 during the dummy cycle into FM14, determines the comparison unity, and generates the next address according to the result.

Such an operation will be explained using the timing chart of FIG. 2.

In FIG. 2, (a) shows the rate signal RATE output from TGl, (b) shows the instruction data INS decoded by IDl0, and (c) shows 1
CT4 output from D10 to CCTL19 is shown, (
d) is the format clock F- output from TGl.
CLK, (e) shows the strobe 5TRB output from G1, (f) shows the input cover turn D-IN of DLJT2, and (9) shows the response pattern D of DUT2.
-OUT, (il) shows the response pattern D-OUT' latched by CMP7, and (1) shows the delay circuit DL.
Strobe 5TRB- added to CMP7 via B
, and (j) shows comparison data C-0UT added to PO2 from CMP7.

In FIG. 2, the rate signal RA is transmitted from TGl at time t1.
TE is output, and the format clock F-CLK is output from TGl at time t2.

The input pattern [)-1N corresponding to the format clock F-CLK is applied from the FMT 4 to the CUT 2 via the driver 5 at time t4, and the response pattern D is applied from the DUT 2 at time t6 when the response time Tr of the DUT 2 has elapsed.
-OUT is output.

This response pattern D-OtJT is latched into CMP7 at time t7. Subsequently, at time ts after the response pattern D-OUT is output, slope 1-slope 5TRB is sent from TGI.
is output. On the other hand, after the conditional branch instructor INS is decoded by ID10 at time t3, control signal CT4 is output from ID10 to CCTL 19 at time t5. CCTL19 receives T according to control signal CT4.
Control signal TG5 is output to Gl, and 1-01 is control signal T.
At time t9 after strobe 5TRB is output according to G5, a dummy rate signal RATElj is applied to generate a dummy cycle of one cycle. Here, time t, 3 and t9
The time 1-e is the strobe setting disabled time during which strobe 5TRB cannot be set systemically. Time t when the time (Ta+Tb) set by DLB has passed from 2+1 t 8 when strobe 5TRB is output,
. Strobe 5TRB' is added to CMP7. At time tll, when the delay time TC has elapsed from when strobe 5TRB'' is added to comparison data C-(llTtfiPG3 from time tI'O), CMP is performed.
Comparison data C-0UT is output from 7 to PG3. Furthermore, at time t12, when the time Td required for processing a predetermined branch instruction in PG3 has elapsed from time 1++ according to comparison data C-0UT, the next rate signal RATE rises, and E
This will result in The dummy cycle rate Tf set in this way is (Ta+Tb+Tc+-Td)-
It becomes 7e. Note that during this dummy cycle, format clock F-CLK and strobe 5TRB are not output.

With this configuration, the execution cycle of the conditional branch instruction is determined by the dummy 1, which has no relation to the measurement of 0UT2.
Becomes Naikul. The user then formats the clock F-CLKJ3 and strobe 5TR as before.
The timing of B is set by the program, but at this time, there is no need to consider the time required to execute the program's conditional branch instruction each time as in the past, and the programs can be combined relatively easily. .

In the above embodiment, the branch line A1 is the comparison data C-0.
Although the example of UT has been explained, the data is not limited to this, data may be from other modules, or data from DI
It may also be a numerical result from JT.

Further, the number of dummy cycles for executing a conditional branch instruction is not limited to one cycle, but may be two or more cycles.

Also, if the PG is controlled by a multi-stage PLR,
The 8Ii calculation may be executed in a dummy cycle, and a branch may be made based on the result.

Further, although an example of an LSI test device has been described, the present invention can also be applied to other test devices using a pattern generator driven according to a program including a conditional branch instruction.

[Effects of the Invention] As explained above, according to the present invention, it is possible to realize a test system that can eliminate the time constraints associated with the execution of conditional branch instructions in a program without changing the user's program settings, and has practical effects. is big.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing essential parts of an embodiment of the present invention, FIG. 2 is a time chart for explaining the operation of FIG. 1,
FIG. 3 is a block diagram showing an example of the main parts of a conventional device, FIG. 4 is a circuit diagram showing a specific example of the pattern generator used in FIG. 3, and FIG. 5 is for explaining the operation of FIG. 4. This is a time chart. 1...Timing generator (TO), 2...Test object (DLJT), 3...Pattern generator (PG)
), 4... Formatter (FMT), 5... Driver, 6... Analog comparator, 7... Digital comparator (CMP), 8.17... Vibration line register (PLR), 9...・Micro memory (MM)
, 10... instruction decoder (N)), 1
1... Address multiplexer (AMUX>, 12...
・・Condition multiplexer (CMUX), 1
3...Selection logic (SL), 14...Fail memory (FM), 15...Address incrementer, 1
6... Pattern memory (PM), 18... Initial address register (IAR), 19... Clock control circuit (CCTL).

Claims (1)

[Claims] A response pattern obtained by adding a test pattern to the test object from a pattern generator according to a program including a conditional branch instruction and an expected pattern output from the pattern generator corresponding to the test pattern are added to a comparator. In a test system configured to compare a response pattern with an expected pattern and selectively execute a program conditional branch instruction according to the comparison result, a part of the pattern generator is configured to decode the program conditional branch instruction. A test system characterized in that a means for generating a dummy cycle is provided.