JPS62180475A - Picture processor - Google Patents

Abstract

PURPOSE:To always ensure satisfactory smoothing operation with a small-sized or prescribed-sized digital filter, by performing the smoothing processing of pictures, for example, after reduction or before magnification of pictures. CONSTITUTION:A picture magnification processing means 15 is provided together with a picture reduction processing means 13 and a picture processing means 14 which performs various filtering processes of pictures. In case an original picture magnified partially, for example, the input picture is first reduced by the means 13 to be coincident with the characteristics (size) of a smoothing filter. Then the output of the reduced picture is smoothed by the means through a smoothing filter. The output of the smoothed picture is magnified by the means 15 to obtain a smoothed picture having the same size as the original picture.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing apparatus, and particularly to an image processing apparatus that performs enlargement, reduction, and filtering processing on an input image.

[Prior Art] In recent years, digital processing of images has been actively performed, and various digital filtering processes such as not only image enlargement and reduction but also edge enhancement and smoothing are performed. However, conventionally, image enlargement/reduction processing and filtering processing were performed separately and independently. Therefore, when the spatial frequency characteristics of the input image and the spatial frequency characteristics of the filter do not match well, edge enhancement may be insufficient, moiré may occur, or smoothing may be adversely affected.

[Problems to be Solved by the Invention] The present invention has been made in view of the above-mentioned drawbacks of the prior art, and its purpose is to associate image filtering processing with image enlargement and reduction processing. By this,
The goal is always to maximize the filter effect.

[Means for Solving the Problem] As a means for solving this problem, for example, the image processing apparatus of the embodiment shown in FIG. It includes an image reduction processing means 13 that performs image reduction processing, and an image processing means 14 that performs various filtering processing on images.

[Function] In the configuration shown in FIG. 1, when smoothing a partially enlarged original image, for example, the image reduction processing means 13 first performs reduction processing on the input image and converts the image into the characteristics (size) of the smoothing filter. ). Next, the image processing means 14 smoothes the reduced image output using the smoothing filter. Next, the output smoothed image is enlarged by the image enlargement processing means 15 into a smoothed image having the same size as the original image.

[Examples] Examples of the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 1 is a block diagram of an image processing apparatus according to an embodiment. In the figure, 11 is an image reading sensor (CCD line sensor) that reads a document image, 12 is an A/D converter that converts the read image signal VDA of the image reading sensor 11 into A/D, and 1
3 is an image enlarging/reducing means capable of enlarging and reducing the A/D converted digital image VDB; 14 is an image processing means that performs various filtering processes on the enlarged or reduced image VDC;
15 is an image enlarging/reducing means capable of enlarging and reducing the filtered image VDD; 16 is a dither processing means for dithering the enlarged or reduced image VDE; 17
18 is an image output device that outputs the dither-converted image VDF as a visible image, and 18 is a control unit that provides control signals of timing signals to each of the above-mentioned constituent blocks.

FIG. 6 is a configuration diagram of the document reading mechanism section including the image reading sensor 11. As shown in FIG. In the figure, 1 is a document table on which the document to be read is placed, 2 is a light source that illuminates the document, 3 is a reflective shade for the light source, and 4 is a short focus lens that guides the scattered light reflected on the document surface to the CCD line sensor 11. . These light source 2, reflective shade 3, short focal length lens 4, and CCD line sensor 11 are constituted as one unit, and perform sub-scanning under the document table 1 at a predetermined speed.

In such a configuration, an image manually input to the CCD line sensor 11 is converted into an electrical signal VDA in main scanning, and is further converted into an A/
The D converter 12 converts the data into digital data VDB.

According to one aspect of image processing, the image data VDB is subjected to image reduction processing in the main scanning direction (line sensor scanning direction) by the image enlargement/reduction means 13, and further subjected to moire removal, edge enhancement, etc. by the image processing means 14. After various filtering processes are performed, the image enlarging/reducing means 15 performs image enlarging processing in the main scanning direction. This image data VDE is dither-converted by the dither processing means 16 and output as a visible image by the image output device 17.

The image enlargement and reduction processing in the sub-scanning direction is performed using the CCD shown in Fig. 6.
This is done by changing the sub-scanning speed of the line sensor 11. In other words, if the sub-scanning speed is set to twice the original magnification, the read image will be reduced by 1/2 in the sub-scanning direction;
If it is doubled, the read image will be enlarged twice in the sub-scanning direction.

Furthermore, when enlarging or reducing in the sub-scanning direction is performed after various filtering processes are performed, this is performed, for example, by overlapping reading or thinning out of main-scanning lines.

FIG. 2 is a block diagram of the image enlargement/reduction means 13.15. The embodiment shows a case where it is configured by hardware, and the frequencies of the write clock and read clock to the line memory are changed to perform enlargement/reduction. In the figure, image clock signal CLK is input to rate multiplier 19 and selectors 20 and 21. The clock signal CLK is synchronized with the image signal V D B/V D D, etc. The rate multiplier 19 changes the frequency f of the clock signal CLK according to the image enlargement/reduction ratio n. That is,
If the frequency at the same magnification is f/1, the frequency at the time of enlargement/reduction is f/n. The control unit 18 controls enlargement or reduction.
It is determined by the control signal C from. That is, the control signal C
When the control signal C is at a LOW (logical 0) level, it is an expansion, and when the control signal C is at a HIGH (logical 1) level, it is a reduction. The clock signal f/n converted by the rate multiplier 19 is input to the selector 20.21 together with the clock signal CLK(f).

An operation timing chart for reduction is shown in FIG. Since the control signal C is a logic level, the selector 20 outputs the clock signal f/n (for example, f/2), and the selector 21 outputs the clock signal CLK (
f) is output. Therefore, the address counter 22 counts the clock signal f/2, and the address counter 23 counts the clock signal f. Each count output is input to selectors 26 and 27, respectively.

On the other hand, the horizontal synchronizing signal (main scanning 1
A selection signal H that repeats the level of logic 1→O→1→0 for each line) is input, and the selector 26 outputs the count output (count f/2) of the address counter 22 when the selection signal H is a logic level. When the selection signal H is at logic O level, the count output (count f) of the address counter 23 is selectively output. Further, when the selection signal H is a logic level, the selector 27 selectively outputs the count output (count f) of the address counter 23, and selects the selection signal H.
When is at logic O level, the count output (count f/2) of the address counter 22 is selectively output. The count outputs of these selectors 26 and 27 are respectively input to address terminals of line memories 28 and 29.

Also, in this state, the read/write control terminals W of the line memories 28 and 29 are controlled by the selection signal H. That is, line memory 2
8 is a write mode when the selection signal H is a logic level, and is a read mode when the selection signal H is a logic 0 level. On the other hand, since the read/write control terminal W of the line memory 29 is inverted once, it is in the read mode when the selection signal H is at the logic level, and is in the write mode when the selection signal H is at the logic O level. Therefore, the reading and writing phases of the line memories 28 and 29 are reversed, and reading and writing are repeated alternately for each main scanning line. Also, under such control, the line memory 28.
The image data to the line memories 28 and 29 are given for each main scan from the buffers 24 and 25, and the read data from the line memories 28 and 29 is selected by the selector 30 and sent to the line sensor 11.
are output in the order they are read.

Therefore, when performing image reduction processing, for example, the address of the line memory 28 is driven at a count f/2 to thin out the image data in the buffer 24, and then the address of the line memory 28 is driven at a count f/2. The image data is read out and output via the selector 30. Moreover, the line memory 29 operates in the opposite phase. Therefore selector 30
A series of 1/2 reduced image data VDC/VDE is output as shown in FIG.

When enlarging an image, for example, the address of the line memory 28 is driven at a count f to write data in the buffer 24, and then the address of the line memory 28 is driven at a count f/2 to duplicate the image data. Read and output via the selector 30. Also line memory 2
9 operates in the opposite phase, and the selector 30 outputs a series of image enlargement data.

Note that when the data in the line memories 28 and 29 are read, the outputs of the buffers 24 and 25 are kept at high impedance.

FIG. 4 is a block diagram of the image processing means 14, and FIG.
a) to (d) are diagrams showing the contents of various digital filters of the image processing means 14. The embodiment shows a case where it is configured by hardware.

The image data VDC input to the image processing means 14 is input to the line buffer 31. The line buffer 31 is, for example, a buffer memory for five main scanning lines. Although this is adapted to the 5×5 size digital filter shown in FIG. 5, it is not limited thereto. Five consecutive lines of image data in the sub-scanning direction can be read from the line buffer 31. This image data is input to a first-order differentiation circuit 32, an edge emphasis circuit 33, and a smoothing circuit 34. Smoothing circuit 34
Then, the image is smoothed by a digital filter as shown in FIG. 5(d). Further, in the edge emphasis circuit 33, the edges of the image are emphasized using a digital filter as shown in FIG. 5(C). Further, the −th order differentiating circuit 32 is the fifth
Figure (a).

It is equipped with a Z fffi type digital filter as shown in (b), and the absolute values of the results of first-order differential filtering in two directions, vertical and horizontal, are added together and output.

The outputs of the edge emphasis circuit 33 and the smoothing circuit 34 are input to a multiplier 36 and a multiplier 37, respectively.

Further, the predetermined numbers (α) and (1-α) output from the mixture ratio determination circuit 35 are input to the multipliers 36 and 37, and multiplication processing is performed. The mixture ratio determining circuit 35 includes a −th order differentiating circuit 32.
If the output of is input and the −th differential value is large, then (α
) is brought close to 1, and α=1 above a certain value. The outputs of the multipliers 36 and 37 are added together by an adder 38.

That is, when the first-order differential amount is large in the negative-order differentiating circuit 32, it is determined to be an edge portion, and a large amount of the output of the edge emphasizing circuit 33 is mixed, and a small amount of the output of the smoothing circuit 34 is mixed. Therefore, for an image of a portion that is not determined to be an edge portion, the adder 38 obtains an output in which many of the outputs of the smoothing circuit 34 are mixed. As a result, when the original read image is a halftone dot image, the periodicity of the halftone dots can be erased by the smoothing process, and moiré can be prevented from occurring during dither processing.

The effect of such filtering processing is exhibited when the spatial frequency of the input image and the spatial frequency of the digital filter are matched, and this is achieved by appropriately selecting the enlargement/reduction ratio n of the image enlargement/reduction means 13. This is achieved by That is, the image size can always be manually changed to match the size that allows the filter function to be performed.

In the present invention, the digital filters used in the -th order differentiating circuit 32, edge emphasizing circuit 33, and smoothing circuit 34 are not limited to those shown in FIG. However, the smaller the matrix size of the digital filter, the easier the electrical circuit configuration, and the software processing can be performed in a shorter time. [Second Embodiment] In the second embodiment, (α) of the mixture ratio determination circuit 35 of the image processing means 14 shown in FIG. 4 can be always set to 1 or always set to O from the outside. This makes it possible to easily obtain an output with only edge enhancement or only smoothing.

Further, since the image enlargement/reduction means 13 and 15 have the same circuit configuration, they are each controlled by the control section 18 and can freely perform image enlargement and reduction processing. Therefore, it is possible to perform filtering processing after enlarging or reducing an image, to perform enlarging or reducing an image after filtering processing, or to enlarge or reduce an image before or after filtering processing.

[Effects of the Invention] As described above, according to the present invention, for example, image smoothing processing can be performed after image reduction or before image enlargement, so that sufficient smoothing can always be performed using a digital filter of a small size or a predetermined size. Furthermore, even in the case of a halftone original, dither processing can be performed after sufficient smoothing, so that moiré in the image can be suppressed regardless of whether an enlarged or reduced image is ultimately obtained.

Furthermore, according to the present invention, enlargement/reduction processing can be performed both before and after various types of filtering processing of an image, so for example, when emphasizing edges, the edge width of the image can be adjusted to the predetermined filter size by performing the enlargement/reduction processing in advance. can be adjusted to Furthermore, by performing the enlargement/reduction processing later, the edge emphasis portion can be output at a desired enlargement/reduction ratio.

Furthermore, according to the present invention, it is possible to adjust the relationship between the spatial frequency characteristics of input image data and the spatial frequency characteristics of various digital filters, so that filtering can be adjusted depending on the situation, such as when edge enhancement tends to cause interference and cause moiré. Enlarging/reducing processing is performed before/after the image processing, and the spatial frequency characteristics of the image data manually input to various image processing means can be changed.

[Brief explanation of drawings]

1 is a block diagram of the image processing device of the embodiment; FIG. 2 is a block diagram of the image enlarging/reducing means 13.15; FIG. 3 is an operation timing chart of the image enlarging/reducing means 13.15; 4 is a block diagram of the image processing means 14, and FIG. 5 (
a) to (d) are diagrams showing the contents of various digital filters of the image processing means 14, and FIG. 6 is a configuration diagram of the document reading mechanism section including the image reading sensor 11. In the figure, 1...Original table, 2...Light source, 3...Reflector, 4...Short focus lens, 11...CCD line sensor, 12...A/D converter, 13 15... Image enlargement/reduction means, 14... Image processing means, 16... Dither processing means, 17... Image output device, 18... Control section. Patent applicant: Canon Corporation (C) Figure 5 (b) (d)

Claims (3)

[Claims] (1) comprising an image enlargement processing means for performing image enlargement processing, an image reduction processing means for performing image reduction processing, and an image processing means for performing image filtering processing, and before the image filtering processing by the image processing means; An image processing apparatus characterized by performing image enlargement processing or reduction processing after or before or after. (2) The scope of claims characterized in that the image reduction processing means performs image reduction processing, the image processing means performs smoothing processing on the image output, and the image enlargement processing means enlarges the image output. The image processing device according to item 1. (3) Image processing means for performing image enlargement processing, image reduction processing means for performing image reduction processing, and image processing means for performing image filtering processing using filter means of a predetermined size; An image processing device characterized in that the spatial frequency characteristics of the image input to the image processing means are changed by performing image enlargement processing or reduction processing before image filtering processing.